kopia lustrzana https://github.com/stlink-org/stlink
Breakpoint handling for Cortex M7
rodzic
aba9591b9a
commit
768fe88e6c
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@ -542,8 +542,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
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return -1;
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}
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#define CODE_BREAK_NUM 6
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#define CODE_LIT_NUM 2
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int code_break_num;
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int code_lit_num;
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#define CODE_BREAK_NUM_MAX 15
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#define CODE_BREAK_LOW 0x01
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#define CODE_BREAK_HIGH 0x02
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@ -552,37 +553,41 @@ struct code_hw_breakpoint {
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int type;
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};
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struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
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struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
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static void init_code_breakpoints(stlink_t *sl) {
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memset(sl->q_buf, 0, 4);
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stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
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unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
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if (((val & 3) != 1) ||
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((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) ||
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(((val >> 8) & 0xf) != CODE_LIT_NUM)){
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ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val,
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((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1);
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}
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code_break_num = ((val >> 4) & 0xf);
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code_lit_num = ((val >> 8) & 0xf);
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ILOG("Found %i hw breakpoint registers\n", code_break_num);
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for(int i = 0; i < CODE_BREAK_NUM; i++) {
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for(int i = 0; i < code_break_num; i++) {
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code_breaks[i].type = 0;
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stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0);
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}
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}
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static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
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stm32_addr_t fpb_addr = addr & ~0x3;
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int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
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stm32_addr_t fpb_addr;
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uint32_t mask;
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int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
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if(addr & 1) {
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ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
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return -1;
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}
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if (sl->chip_id==STM32_CHIPID_F7) {
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fpb_addr = addr;
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} else {
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fpb_addr = addr & ~0x3;
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}
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int id = -1;
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for(int i = 0; i < CODE_BREAK_NUM; i++) {
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for(int i = 0; i < code_break_num; i++) {
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if(fpb_addr == code_breaks[i].addr ||
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(set && code_breaks[i].type == 0)) {
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id = i;
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@ -599,16 +604,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
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brk->addr = fpb_addr;
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if(set) brk->type |= type;
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else brk->type &= ~type;
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if (sl->chip_id==STM32_CHIPID_F7) {
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if(set) brk->type = type;
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else brk->type = 0;
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mask = (brk->addr) | 1;
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} else {
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if(set) brk->type |= type;
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else brk->type &= ~type;
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mask = (brk->addr) | 1 | (brk->type << 30);
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}
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if(brk->type == 0) {
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DLOG("clearing hw break %d\n", id);
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stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
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} else {
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uint32_t mask = (brk->addr) | 1 | (brk->type << 30);
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DLOG("setting hw break %d at %08x (%d)\n",
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id, brk->addr, brk->type);
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DLOG("reg %08x \n",
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@ -701,6 +713,7 @@ static int flash_go(stlink_t *sl) {
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// Some kinds of clock settings do not allow writing to flash.
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stlink_reset(sl);
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stlink_force_debug(sl);
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for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
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DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
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