Merge pull request #86 from szczys/master

Added support for the STM32F0-Discovery board

example/blink/Makefile

@@ -12,8 +12,9 @@ DEF_CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000
 CFLAGS_VL=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1
 CFLAGS_L=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY
 CFLAGS_F4=$(DEF_CFLAGS) -mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1
+CFLAGS_F0=$(DEF_CFLAGS) -mcpu=cortex-m0 -DCONFIG_STM32F0_DISCOVERY=1
 
-all: blink_32VL.elf blink_32L.elf blink_F4.elf
+all: blink_32VL.elf blink_32L.elf blink_F4.elf blink_F0.elf
 
 %.bin: %.elf
 	$(OBJCOPY) -O binary $^ $@
@@ -24,6 +25,8 @@ blink_32L.elf: main.c
 	$(CC) $(CFLAGS_L) $^ -o $@
 blink_F4.elf: main.c
 	$(CC) $(CFLAGS_F4) $^ -o $@
+blink_F0.elf: main.c
+	$(CC) $(CFLAGS_F0) $^ -o $@
 
 clean:
 	rm -rf *.elf

example/blink/main.c

@@ -58,6 +58,26 @@ static inline void setup_leds(void)
   	(1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2));
 }
 
+#elif CONFIG_STM32F0_DISCOVERY
+
+#define GPIOC 0x48000800 /* port C */
+#define GPIOC_MODER (GPIOC + 0x00) /* port mode register */
+#define LED_PORT_ODR (GPIOC + 0x14) /* port output data register */
+
+#define LED_BLUE (1 << 8) /* port C, pin 8 */
+#define LED_GREEN (1 << 9) /* port C, pin 9 */
+#define LED_ORANGE 0
+#define LED_RED 0
+
+void _tmain(void) {
+	main();
+}
+static inline void setup_leds(void)
+{
+  /* configure port 8 and 9 as output */
+  *(volatile uint32_t*)GPIOC_MODER |= (1 << (9* 2)) | (1 << (8 * 2));
+}
+
 #else
 #error "Architecture must be defined!"
 #endif /* otherwise, error */

src/stlink-common.c

@@ -394,7 +394,7 @@ uint32_t stlink_core_id(stlink_t *sl) {
 
 uint32_t stlink_chip_id(stlink_t *sl) {
     uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
-    if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0xE000ED00);
+    if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800);	//Try Corex M0 DBGMCU_IDCODE register address
     return chip_id;
 }
 

src/stlink-common.h

@@ -221,6 +221,17 @@ extern "C" {
                     .sram_size = 0x18000,
                     .bootrom_base = 0x1fffe000,
                     .bootrom_size = 0x1800
+        },
+        {
+            //Use this as an example for mapping future chips:
+            //RM0091 document was used to find these paramaters
+            .chip_id = 0x440,
+                    .description = "F0 device",
+                    .flash_size_reg = 0x1ffff7cc,	// "Flash size data register" (pg735)
+                    .flash_pagesize = 0x400,		// Page sizes listed in Table 4
+                    .sram_size = 0x2000,		// "SRAM" byte size in hex from Table 2
+                    .bootrom_base = 0x1fffec00,		// "System memory" starting address from Table 2
+                    .bootrom_size = 0xC00 		// "System memory" byte size in hex from Table 2
         }
  };