kopia lustrzana https://github.com/stlink-org/stlink
[add] blink_flash example
Fabien Le Mentec
rodzic
ce9f2666e9
commit
6b9c19ceb8
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@ -0,0 +1,25 @@
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EXECUTABLE=blink.elf
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BIN_IMAGE=blink.bin
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CC=arm-none-eabi-gcc
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OBJCOPY=arm-none-eabi-objcopy
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CFLAGS=-O2 -mlittle-endian -mthumb
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CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
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# to run from FLASH
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CFLAGS+=-Wl,-T,stm32_flash.ld
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all: $(BIN_IMAGE)
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$(BIN_IMAGE): $(EXECUTABLE)
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$(OBJCOPY) -O binary $^ $@
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$(EXECUTABLE): main.c startup_stm32l1xx_md.s
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$(CC) $(CFLAGS) $^ -o $@
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clean:
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rm -rf $(EXECUTABLE)
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rm -rf $(BIN_IMAGE)
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.PHONY: all clean
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@ -0,0 +1,82 @@
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/* missing type */
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typedef unsigned int uint32_t;
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/* hardware configuration */
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#define CONFIG_STM32L_DISCOVERY 1
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#define CONFIG_STM32VL_DISCOVERY 0
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#if CONFIG_STM32VL_DISCOVERY
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# define GPIOC 0x40011000 /* port C */
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# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */
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# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */
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# define LED_BLUE (1 << 8) /* port C, pin 8 */
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# define LED_GREEN (1 << 9) /* port C, pin 9 */
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static inline void setup_leds(void)
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{
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*(volatile uint32_t*)GPIOC_CRH = 0x44444411;
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}
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static inline void switch_leds_on(void)
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{
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*(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN;
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}
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static inline void switch_leds_off(void)
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{
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*(volatile uint32_t*)GPIOC_ODR = 0;
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}
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#elif CONFIG_STM32L_DISCOVERY
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# define GPIOB 0x40020400 /* port B */
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# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */
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# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */
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# define LED_BLUE (1 << 6) /* port B, pin 6 */
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# define LED_GREEN (1 << 7) /* port B, pin 7 */
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static inline void setup_leds(void)
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{
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/* configure port 6 and 7 as output */
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*(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
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}
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static inline void switch_leds_on(void)
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{
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*(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN;
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}
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static inline void switch_leds_off(void)
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{
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*(volatile uint32_t*)GPIOB_ODR = 0;
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}
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#endif /* otherwise, error */
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#define delay() \
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do { \
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register unsigned int i; \
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for (i = 0; i < 1000000; ++i) \
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__asm__ __volatile__ ("nop\n\t":::"memory"); \
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} while (0)
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void main(void)
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{
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setup_leds();
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while (1)
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{
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switch_leds_on();
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delay();
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switch_leds_off();
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delay();
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}
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}
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@ -0,0 +1,366 @@
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/**
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******************************************************************************
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* @file startup_stm32l1xx_md.s
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* @author MCD Application Team
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* @version V1.0.0
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* @date 31-December-2010
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* @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for
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* RIDE7 toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M3 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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*******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m3
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.equ BootRAM, 0xF108F85F
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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/* let main do the system initialization */
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/* bl SystemInit */
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/*******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler
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.word PVD_IRQHandler
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.word TAMPER_STAMP_IRQHandler
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.word RTC_WKUP_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_IRQHandler
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.word DMA1_Channel3_IRQHandler
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.word DMA1_Channel4_IRQHandler
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.word DMA1_Channel5_IRQHandler
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word ADC1_IRQHandler
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.word USB_HP_IRQHandler
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.word USB_LP_IRQHandler
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.word DAC_IRQHandler
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.word COMP_IRQHandler
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.word EXTI9_5_IRQHandler
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.word LCD_IRQHandler
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.word TIM9_IRQHandler
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.word TIM10_IRQHandler
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.word TIM11_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word TIM4_IRQHandler
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.word I2C1_EV_IRQHandler
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.word I2C1_ER_IRQHandler
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.word I2C2_EV_IRQHandler
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.word I2C2_ER_IRQHandler
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.word SPI1_IRQHandler
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.word SPI2_IRQHandler
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.word USART1_IRQHandler
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.word USART2_IRQHandler
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.word USART3_IRQHandler
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.word EXTI15_10_IRQHandler
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.word RTC_Alarm_IRQHandler
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.word USB_FS_WKUP_IRQHandler
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.word TIM6_IRQHandler
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.word TIM7_IRQHandler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word BootRAM /* @0x108. This is for boot in RAM mode for
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STM32L15x ULtra Low Power Medium-density devices. */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak MemManage_Handler
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.thumb_set MemManage_Handler,Default_Handler
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.weak BusFault_Handler
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.thumb_set BusFault_Handler,Default_Handler
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_IRQHandler
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.thumb_set PVD_IRQHandler,Default_Handler
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.weak TAMPER_STAMP_IRQHandler
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.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
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.weak RTC_WKUP_IRQHandler
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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.weak DMA1_Channel1_IRQHandler
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.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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.weak DMA1_Channel2_IRQHandler
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.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
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.weak DMA1_Channel3_IRQHandler
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.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
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.weak DMA1_Channel4_IRQHandler
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.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
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.weak DMA1_Channel5_IRQHandler
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.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
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.weak DMA1_Channel6_IRQHandler
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.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
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.weak DMA1_Channel7_IRQHandler
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.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
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.weak ADC1_IRQHandler
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.thumb_set ADC1_IRQHandler,Default_Handler
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.weak USB_HP_IRQHandler
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.thumb_set USB_HP_IRQHandler,Default_Handler
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.weak USB_LP_IRQHandler
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.thumb_set USB_LP_IRQHandler,Default_Handler
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.weak DAC_IRQHandler
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.thumb_set DAC_IRQHandler,Default_Handler
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.weak COMP_IRQHandler
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.thumb_set COMP_IRQHandler,Default_Handler
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.weak EXTI9_5_IRQHandler
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.thumb_set EXTI9_5_IRQHandler,Default_Handler
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.weak LCD_IRQHandler
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.thumb_set LCD_IRQHandler,Default_Handler
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.weak TIM9_IRQHandler
|
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.thumb_set TIM9_IRQHandler,Default_Handler
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.weak TIM10_IRQHandler
|
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.thumb_set TIM10_IRQHandler,Default_Handler
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|
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.weak TIM11_IRQHandler
|
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.thumb_set TIM11_IRQHandler,Default_Handler
|
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|
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.weak TIM2_IRQHandler
|
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.thumb_set TIM2_IRQHandler,Default_Handler
|
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|
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.weak TIM3_IRQHandler
|
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.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
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.weak TIM4_IRQHandler
|
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.thumb_set TIM4_IRQHandler,Default_Handler
|
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|
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.weak I2C1_EV_IRQHandler
|
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.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
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|
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.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
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.weak I2C2_EV_IRQHandler
|
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.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_FS_WKUP_IRQHandler
|
||||
.thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/
|
||||
|
||||
|
|
@ -0,0 +1,173 @@
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|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32_flash.ld
|
||||
**
|
||||
** Abstract : Linker script for STM32L152RB Device with
|
||||
** 128KByte FLASH, 16KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Environment : Atollic TrueSTUDIO(R)
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
** (c)Copyright Atollic AB.
|
||||
** You may use this file as-is or modify it according to the needs of your
|
||||
** project. Distribution of this file (unmodified or modified) is not
|
||||
** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
|
||||
** rights to distribute the assembled, compiled & linked contents of this
|
||||
** file as part of an application binary file, provided that it is built
|
||||
** using the Atollic TrueSTUDIO(R) toolchain.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20004000; /* end of 16K RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x80; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
|
||||
RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = .;
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data : AT ( _sidata )
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
|
||||
/* MEMORY_bank1 section, code must be located here explicitly */
|
||||
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
|
||||
.memory_b1_text :
|
||||
{
|
||||
*(.mb1text) /* .mb1text sections (code) */
|
||||
*(.mb1text*) /* .mb1text* sections (code) */
|
||||
*(.mb1rodata) /* read-only data (constants) */
|
||||
*(.mb1rodata*)
|
||||
} >MEMORY_B1
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
.DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM
|
||||
}
|
||||
|
|
@ -0,0 +1,367 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32l1xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 2-June-2011
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32L1xx Ultra
|
||||
* Low Medium-density devices, and is generated by the clock configuration
|
||||
* tool "STM32L1xx_Clock_Configuration_V1.0.0.xls".
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32l1xx_md.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and MSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System Clock Configuration
|
||||
*=============================================================================
|
||||
* System clock source | HSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK | 16000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK | 16000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency | 8000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL DIV | Not Used
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL MUL | Not Used
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD | 3.3 V
|
||||
*-----------------------------------------------------------------------------
|
||||
* Vcore | 1.8 V (Range 1)
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency | 0 WS
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB clock | Disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l1xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/*!< Set MSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000100;
|
||||
|
||||
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0x88FFC00C;
|
||||
|
||||
/*!< Reset HSION, HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEEFEFFFE;
|
||||
|
||||
/*!< Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0xFF02FFFF;
|
||||
|
||||
/*!< Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock according to Clock Register Values
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
|
||||
* value as defined by the MSI range.
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock */
|
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
|
||||
SystemCoreClock = (32768 * (1 << (msirange + 1)));
|
||||
break;
|
||||
case 0x04: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x08: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x0C: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||||
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
|
||||
pllmul = PLLMulTable[(pllmul >> 18)];
|
||||
plldiv = (plldiv >> 22) + 1;
|
||||
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock selected as PLL clock entry */
|
||||
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSE selected as PLL clock entry */
|
||||
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
|
||||
}
|
||||
break;
|
||||
default: /* MSI used as system clock */
|
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
|
||||
SystemCoreClock = (32768 * (1 << (msirange + 1)));
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
|
||||
* settings.
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||||
/* Enable HSI */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSION);
|
||||
|
||||
/* Wait till HSI is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSIStatus = RCC->CR & RCC_CR_HSIRDY;
|
||||
} while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
|
||||
{
|
||||
HSIStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSIStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSIStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Flash 0 wait state */
|
||||
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
||||
|
||||
/* Disable Prefetch Buffer */
|
||||
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
|
||||
|
||||
/* Disable 64-bit access */
|
||||
FLASH->ACR &= ~FLASH_ACR_ACC64;
|
||||
|
||||
|
||||
/* Power enable */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
|
||||
/* Select the Voltage Range 1 (1.8 V) */
|
||||
PWR->CR = PWR_CR_VOS_0;
|
||||
|
||||
|
||||
/* Wait Until the Voltage Regulator is ready */
|
||||
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
||||
{
|
||||
}
|
||||
|
||||
/* HCLK = SYSCLK /1*/
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK /1*/
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK /1*/
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
||||
|
||||
/* Select HSI as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
|
||||
|
||||
/* Wait till HSI is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSI fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||
Ładowanie…
Reference in New Issue