From 6692fdc57cd087be84dbf831e85730cab58c7bf9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 00:50:50 +0100 Subject: [PATCH] Restored support for STM32-Clones -> CKS devices with Core ID 0x2ba01477 (Closes #756 #757 #761 #766 #769 #805) --- include/stm32.h | 1 + src/common.c | 5 ++++- src/flash_loader.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/stm32.h b/include/stm32.h index 8f8e7eb..9fb3e45 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -9,6 +9,7 @@ // cortex core ids #define STM32VL_CORE_ID 0x1ba01477 +#define CS32VL_CORE_ID 0x2ba01477 #define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures diff --git a/src/common.c b/src/common.c index bcce965..19155f7 100644 --- a/src/common.c +++ b/src/common.c @@ -2262,7 +2262,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t uint32_t flash_regs_base; uint32_t pagesize; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; pagesize = L0_WRITE_BLOCK_SIZE; } else { diff --git a/src/flash_loader.c b/src/flash_loader.c index 7479e05..1e125e9 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -267,6 +267,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == CS32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL ||