flash_loader: added reset of IWDG

If IWDG is enabled by hardware, then IWDG cannot be disabled by software

inc/stlink.h

@@ -138,6 +138,7 @@ typedef struct flash_loader {
     stm32_addr_t loader_addr; // loader sram addr
     stm32_addr_t buf_addr; // buffer sram address
     uint32_t rcc_dma_bkp; // backup RCC DMA enable state
+    uint32_t iwdg_kr; // IWDG key register address
 } flash_loader_t;
 
 typedef struct _cortex_m3_cpuid_ {

src/stlink-lib/flash_loader.c

@@ -9,6 +9,11 @@
 #define FLASH_REGS_BANK2_OFS 0x40
 #define FLASH_BANK2_START_ADDR 0x08080000
 
+#define STM32F0_WDG_KR            0x40003000
+#define STM32H7_WDG_KR            0x58004800
+
+#define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA
+
 /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */
 
 /* flashloaders/stm32f0.s -- compiled with thumb2 */
@@ -164,6 +169,13 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) {
     fl->buf_addr = fl->loader_addr + (uint32_t)size;
     ILOG("Successfully loaded flash loader in sram\n");
 
+    // set address of IWDG key register for reset it
+    if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
+        fl->iwdg_kr = STM32H7_WDG_KR;
+    } else {
+        fl->iwdg_kr = STM32F0_WDG_KR;
+    }
+
     /* Clear Fault Status Register for handling flash loader error */
     if (!stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr) && dfsr) {
         ILOG("Clear DFSR\n");
@@ -329,6 +341,11 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe
                                                // only used on VL/F1_XL, but harmless for others
     stlink_write_reg(sl, fl->loader_addr, 15); // pc register
 
+    /* Reset IWDG */
+    if (fl->iwdg_kr) {
+        stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD);
+    }
+
     /* Run loader */
     stlink_run(sl);