kopia lustrzana https://github.com/stlink-org/stlink
common.c: fix define - use Gx Base for Gx defines
avoid some potential issues later.pull/927/head
rodzic
e146a28a67
commit
3aaec273da
14
src/common.c
14
src/common.c
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@ -79,13 +79,13 @@
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// Flash registers common to STM32G0 and STM32G4 series.
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#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000)
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#define STM32Gx_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00)
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#define STM32Gx_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08)
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#define STM32Gx_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c)
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#define STM32Gx_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10)
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#define STM32Gx_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14)
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#define STM32Gx_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18)
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#define STM32Gx_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20)
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#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00)
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#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08)
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#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c)
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#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10)
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#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14)
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#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18)
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#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20)
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// G0 (RM0444 Table 1, sec 3.7)
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// Mostly the same as G4 chips, but the notation
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