kopia lustrzana https://github.com/stlink-org/stlink
Merge pull request #363 from gingold-adacore/cache
st-util: synchronize cache for stm32f7pull/366/head
texane
commit
37ecabf765
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@ -49,6 +49,7 @@ typedef struct _st_state_t {
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int serve(stlink_t *sl, st_state_t *st);
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char* make_memory_map(stlink_t *sl);
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static void init_cache (stlink_t *sl);
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static void cleanup(int signal __attribute__((unused))) {
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if (connected_stlink) {
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@ -208,6 +209,8 @@ int main(int argc, char** argv) {
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}
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#endif
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init_cache(sl);
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do {
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if (serve(sl, &state)) {
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sleep (1); // don't go bezurk if serve returns with error
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@ -750,6 +753,161 @@ error:
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return error;
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}
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#define CLIDR 0xE000ED78
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#define CTR 0xE000ED7C
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#define CCSIDR 0xE000ED80
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#define CSSELR 0xE000ED84
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#define CCR 0xE000ED14
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#define CCR_DC (1 << 16)
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#define CCR_IC (1 << 17)
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#define DCCSW 0xE000EF6C
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#define ICIALLU 0xE000EF50
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struct cache_level_desc
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{
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unsigned int nsets;
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unsigned int nways;
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unsigned int log2_nways;
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unsigned int width;
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};
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struct cache_desc_t
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{
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/* Minimal line size in bytes. */
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unsigned int dminline;
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unsigned int iminline;
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/* Last level of unification (uniprocessor). */
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unsigned int louu;
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struct cache_level_desc icache[7];
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struct cache_level_desc dcache[7];
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};
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static struct cache_desc_t cache_desc;
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/* Return the smallest R so that V <= (1 << R). Not performance critical. */
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static unsigned ceil_log2(unsigned v)
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{
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unsigned res;
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for (res = 0; (1 << res) < v; res++)
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;
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return res;
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}
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static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc)
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{
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unsigned int ccsidr;
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unsigned int log2_nsets;
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ccsidr = stlink_read_debug32(sl, CCSIDR);
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desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
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desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
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desc->log2_nways = ceil_log2 (desc->nways);
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log2_nsets = ceil_log2 (desc->nsets);
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desc->width = 4 + (ccsidr & 7) + log2_nsets;
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ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n",
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ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width);
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}
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static void init_cache (stlink_t *sl) {
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unsigned int clidr;
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unsigned int ccr;
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unsigned int ctr;
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int i;
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/* Assume only F7 has a cache. */
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if(sl->chip_id!=STM32_CHIPID_F7)
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return;
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clidr = stlink_read_debug32(sl, CLIDR);
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ccr = stlink_read_debug32(sl, CCR);
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ctr = stlink_read_debug32(sl, CTR);
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cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
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cache_desc.iminline = 4 << (ctr & 0x0f);
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cache_desc.louu = (clidr >> 27) & 7;
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ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n",
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clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off");
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ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n",
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(clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7);
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ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr,
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cache_desc.dminline, cache_desc.iminline);
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for(i = 0; i < 7; i++)
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{
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unsigned int ct = (clidr >> (3 * i)) & 0x07;
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cache_desc.dcache[i].width = 0;
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cache_desc.icache[i].width = 0;
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if(ct == 2 || ct == 3 || ct == 4)
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{
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/* Data. */
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stlink_write_debug32(sl, CSSELR, i << 1);
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ILOG("D-Cache L%d: ", i);
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read_cache_level_desc(sl, &cache_desc.dcache[i]);
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}
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if(ct == 1 || ct == 3)
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{
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/* Instruction. */
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stlink_write_debug32(sl, CSSELR, (i << 1) | 1);
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ILOG("I-Cache L%d: ", i);
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read_cache_level_desc(sl, &cache_desc.icache[i]);
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}
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}
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}
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static void cache_flush(stlink_t *sl, unsigned ccr) {
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int level;
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if (ccr & CCR_DC)
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for (level = cache_desc.louu - 1; level >= 0; level--)
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{
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struct cache_level_desc *desc = &cache_desc.dcache[level];
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unsigned addr;
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unsigned max_addr = 1 << desc->width;
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unsigned way_sh = 32 - desc->log2_nways;
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/* D-cache clean by set-ways. */
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for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline)
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{
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unsigned int way;
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for (way = 0; way < desc->nways; way++)
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stlink_write_debug32(sl, DCCSW, addr | (way << way_sh));
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}
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}
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/* Invalidate all I-cache to oPU. */
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if (ccr & CCR_IC)
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stlink_write_debug32(sl, ICIALLU, 0);
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}
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static int cache_modified;
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static void cache_change(stm32_addr_t start, unsigned count)
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{
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if (count == 0)
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return;
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(void)start;
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cache_modified = 1;
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}
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static void cache_sync(stlink_t *sl)
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{
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unsigned ccr;
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if(sl->chip_id!=STM32_CHIPID_F7)
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return;
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if (!cache_modified)
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return;
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cache_modified = 0;
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ccr = stlink_read_debug32(sl, CCR);
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if (ccr & (CCR_IC | CCR_DC))
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cache_flush(sl, ccr);
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}
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int serve(stlink_t *sl, st_state_t *st) {
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int sock = socket(AF_INET, SOCK_STREAM, 0);
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if(sock < 0) {
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@ -898,6 +1056,7 @@ int serve(stlink_t *sl, st_state_t *st) {
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if (!strncmp(params,"726573756d65",12)) {// resume
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DLOG("Rcmd: resume\n");
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cache_sync(sl);
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stlink_run(sl);
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reply = strdup("OK");
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@ -1016,6 +1175,7 @@ int serve(stlink_t *sl, st_state_t *st) {
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}
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case 'c':
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cache_sync(sl);
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stlink_run(sl);
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while(1) {
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@ -1045,6 +1205,7 @@ int serve(stlink_t *sl, st_state_t *st) {
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break;
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case 's':
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cache_sync(sl);
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stlink_step(sl);
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reply = strdup("S05"); // TRAP
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@ -1199,6 +1360,7 @@ int serve(stlink_t *sl, st_state_t *st) {
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sl->q_buf[i] = byte;
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}
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stlink_write_mem8(sl, start, align_count);
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cache_change(start, align_count);
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start += align_count;
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count -= align_count;
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hexdata += 2*align_count;
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@ -1213,6 +1375,7 @@ int serve(stlink_t *sl, st_state_t *st) {
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sl->q_buf[i] = byte;
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}
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stlink_write_mem32(sl, start, aligned_count);
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cache_change(start, aligned_count);
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count -= aligned_count;
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start += aligned_count;
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hexdata += 2*aligned_count;
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@ -1225,6 +1388,7 @@ int serve(stlink_t *sl, st_state_t *st) {
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sl->q_buf[i] = byte;
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}
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stlink_write_mem8(sl, start, count);
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cache_change(start, count);
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}
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reply = strdup("OK");
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break;
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