kopia lustrzana https://github.com/stlink-org/stlink
Merge pull request #49 from UweBonnes/master
Allow to write to ram and start loaded programs.pull/51/head
texane
commit
31d4134919
78
flash/main.c
78
flash/main.c
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@ -9,10 +9,10 @@
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#include <sys/types.h>
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#include "stlink-common.h"
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enum st_cmds {DO_WRITE = 0, DO_READ = 1, DO_ERASE = 2};
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struct opts
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{
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unsigned int do_read;
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enum st_cmds cmd;
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const char* devname;
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const char* filename;
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stm32_addr_t addr;
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@ -22,7 +22,9 @@ struct opts
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static void usage(void)
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{
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puts("stlinkv1 command line: ./flash {read|write} /dev/sgX path addr <size>");
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puts("stlinkv1 command line: ./flash /dev/sgX erase");
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puts("stlinkv2 command line: ./flash {read|write} path addr <size>");
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puts("stlinkv2 command line: ./flash erase");
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puts(" use hex format for addr and <size>");
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}
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@ -33,38 +35,52 @@ static int get_opts(struct opts* o, int ac, char** av)
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unsigned int i = 0;
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if (ac < 3) return -1;
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if (ac < 1) return -1;
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/* stlinkv2 */
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o->devname = NULL;
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if (strcmp(av[0], "read") == 0)
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if (strcmp(av[0], "erase") == 0)
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{
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o->do_read = 1;
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o->cmd = DO_ERASE;
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/* stlinkv1 mode */
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if (ac == 5)
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{
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o->devname = av[1];
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i = 1;
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}
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if (ac > 3)
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o->size = strtoul(av[i + 3], NULL, 16);
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}
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else if (strcmp(av[0], "write") == 0)
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{
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o->do_read = 0;
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/* stlinkv1 mode */
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if (ac == 4)
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if (ac == 2)
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{
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o->devname = av[1];
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i = 1;
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}
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}
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else
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{
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return -1;
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else {
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if (ac < 3) return -1;
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if (strcmp(av[0], "read") == 0)
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{
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o->cmd = DO_READ;
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/* stlinkv1 mode */
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if (ac == 5)
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{
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o->devname = av[1];
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i = 1;
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}
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if (ac > 3)
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o->size = strtoul(av[i + 3], NULL, 16);
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}
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else if (strcmp(av[0], "write") == 0)
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{
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o->cmd = DO_WRITE;
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/* stlinkv1 mode */
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if (ac == 4)
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{
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o->devname = av[1];
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i = 1;
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}
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}
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else
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{
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return -1;
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}
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}
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o->filename = av[i + 1];
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@ -107,9 +123,23 @@ int main(int ac, char** av)
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if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE)
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stlink_enter_swd_mode(sl);
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if (o.do_read == 0) /* write */
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if (o.cmd == DO_WRITE) /* write */
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{
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err = stlink_fwrite_flash(sl, o.filename, o.addr);
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if ((o.addr >= sl->flash_base) &&
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(o.addr < sl->flash_base + sl->flash_size))
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err = stlink_fwrite_flash(sl, o.filename, o.addr);
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else if ((o.addr >= sl->sram_base) &&
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(o.addr < sl->sram_base + sl->sram_size))
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err = stlink_fwrite_sram(sl, o.filename, o.addr);
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if (err == -1)
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{
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printf("stlink_fwrite_flash() == -1\n");
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goto on_error;
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}
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}
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else if (o.cmd == DO_ERASE)
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{
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err = stlink_erase_flash_mass(sl);
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if (err == -1)
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{
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printf("stlink_fwrite_flash() == -1\n");
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@ -265,15 +265,13 @@ static void init_data_watchpoints(stlink_t *sl) {
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#endif
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// set trcena in debug command to turn on dwt unit
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stlink_read_mem32(sl, 0xE000EDFC, 4);
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sl->q_buf[3] |= 1;
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stlink_write_mem32(sl, 0xE000EDFC, 4);
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stlink_write_debug32(sl, 0xE000EDFC,
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stlink_read_debug32(sl, 0xE000EDFC) | (1<<24));
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// make sure all watchpoints are cleared
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memset(sl->q_buf, 0, 4);
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for(int i = 0; i < DATA_WATCH_NUM; i++) {
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data_watches[i].fun = WATCHDISABLED;
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stlink_write_mem32(sl, 0xe0001028 + i * 16, 4);
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stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
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}
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}
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@ -306,25 +304,16 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr
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data_watches[i].mask = mask;
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// insert comparator address
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sl->q_buf[0] = (addr & 0xff);
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sl->q_buf[1] = ((addr >> 8) & 0xff);
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sl->q_buf[2] = ((addr >> 16) & 0xff);
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sl->q_buf[3] = ((addr >> 24) & 0xff);
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stlink_write_mem32(sl, 0xE0001020 + i * 16, 4);
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stlink_write_debug32(sl, 0xE0001020 + i * 16, addr);
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// insert mask
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memset(sl->q_buf, 0, 4);
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sl->q_buf[0] = mask;
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stlink_write_mem32(sl, 0xE0001024 + i * 16, 4);
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stlink_write_debug32(sl, 0xE0001024 + i * 16, mask);
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// insert function
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memset(sl->q_buf, 0, 4);
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sl->q_buf[0] = wf;
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stlink_write_mem32(sl, 0xE0001028 + i * 16, 4);
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stlink_write_debug32(sl, 0xE0001028 + i * 16, wf);
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// just to make sure the matched bit is clear !
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stlink_read_mem32(sl, 0xE0001028 + i * 16, 4);
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stlink_read_debug32(sl, 0xE0001028 + i * 16);
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return 0;
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}
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}
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@ -346,9 +335,8 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
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printf("delete watchpoint %d addr %x\n", i, addr);
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#endif
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memset(sl->q_buf, 0, 4);
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data_watches[i].fun = WATCHDISABLED;
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stlink_write_mem32(sl, 0xe0001028 + i * 16, 4);
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stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
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return 0;
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}
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@ -374,15 +362,13 @@ struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
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static void init_code_breakpoints(stlink_t *sl) {
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memset(sl->q_buf, 0, 4);
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sl->q_buf[0] = 0x03; // KEY | ENABLE
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stlink_write_mem32(sl, CM3_REG_FP_CTRL, 4);
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stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
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printf("KARL - should read back as 0x03, not 60 02 00 00\n");
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stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4);
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stlink_read_debug32(sl, CM3_REG_FP_CTRL);
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memset(sl->q_buf, 0, 4);
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for(int i = 0; i < CODE_BREAK_NUM; i++) {
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code_breaks[i].type = 0;
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stlink_write_mem32(sl, CM3_REG_FP_COMP0 + i * 4, 4);
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stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0);
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}
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}
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@ -416,28 +402,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
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if(set) brk->type |= type;
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else brk->type &= ~type;
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memset(sl->q_buf, 0, 4);
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if(brk->type == 0) {
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#ifdef DEBUG
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printf("clearing hw break %d\n", id);
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#endif
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stlink_write_mem32(sl, 0xe0002008 + id * 4, 4);
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stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
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} else {
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sl->q_buf[0] = ( brk->addr & 0xff) | 1;
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sl->q_buf[1] = ((brk->addr >> 8) & 0xff);
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sl->q_buf[2] = ((brk->addr >> 16) & 0xff);
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sl->q_buf[3] = ((brk->addr >> 24) & 0xff) | (brk->type << 6);
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uint32_t mask = (brk->addr) | 1 | (brk->type << 30);
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#ifdef DEBUG
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printf("setting hw break %d at %08x (%d)\n",
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id, brk->addr, brk->type);
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printf("reg %02x %02x %02x %02x\n",
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sl->q_buf[3], sl->q_buf[2], sl->q_buf[1], sl->q_buf[0]);
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printf("reg %08x \n",
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mask);
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#endif
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stlink_write_mem32(sl, 0xe0002008 + id * 4, 4);
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stlink_write_debug32(sl, 0xe0002008 + id * 4, mask);
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}
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return 0;
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@ -405,9 +405,9 @@ int stlink_load_device_params(stlink_t *sl) {
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chip_id = 0x413;
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}
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sl->chip_id = chip_id;
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sl->chip_id = chip_id & 0xfff;
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for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
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if(devices[i].chip_id == (chip_id & 0xFFF)) {
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if(devices[i].chip_id == sl->chip_id) {
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params = &devices[i];
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break;
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}
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@ -422,9 +422,9 @@ int stlink_load_device_params(stlink_t *sl) {
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sl->sram_base = STM32_SRAM_BASE;
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// read flash size from hardware, if possible...
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if ((chip_id & 0xFFF) == STM32_CHIPID_F2) {
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if (sl->chip_id == STM32_CHIPID_F2) {
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sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible?
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} else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) {
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} else if (sl->chip_id == STM32_CHIPID_F4) {
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sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
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} else {
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uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
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@ -799,6 +799,11 @@ int stlink_fwrite_sram
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/* success */
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error = 0;
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/* set stack*/
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stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
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/* Set PC to the reset routine*/
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stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
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stlink_run(sl);
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on_error:
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unmap_file(&mf);
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@ -1048,26 +1053,45 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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}
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int stlink_erase_flash_mass(stlink_t *sl) {
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/* wait for ongoing op to finish */
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wait_flash_busy(sl);
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/* unlock if locked */
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unlock_flash_if(sl);
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/* set the mass erase bit */
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set_flash_cr_mer(sl);
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/* start erase operation, reset by hw with bsy bit */
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set_flash_cr_strt(sl);
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/* wait for completion */
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wait_flash_busy(sl);
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/* relock the flash */
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lock_flash(sl);
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/* todo: verify the erased memory */
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if (sl->chip_id == STM32_CHIPID_F4) {
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DLOG("(FIXME) Mass erase of STM32F4\n");
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}
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else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
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/* erase each page */
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int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
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for (i = 0; i < num_pages; i++) {
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/* addr must be an addr inside the page */
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stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
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if (stlink_erase_flash_page(sl, addr) == -1) {
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WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
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return -1;
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}
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fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
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fflush(stdout);
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}
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fprintf(stdout, "\n");
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}
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else {
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/* wait for ongoing op to finish */
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wait_flash_busy(sl);
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/* unlock if locked */
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unlock_flash_if(sl);
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/* set the mass erase bit */
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set_flash_cr_mer(sl);
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/* start erase operation, reset by hw with bsy bit */
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set_flash_cr_strt(sl);
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/* wait for completion */
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wait_flash_busy(sl);
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/* relock the flash */
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lock_flash(sl);
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/* todo: verify the erased memory */
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}
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return 0;
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}
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@ -1185,7 +1209,7 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
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*/
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int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
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size_t off;
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if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) {
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if (sl->chip_id == STM32_CHIPID_F4) {
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DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n");
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return 0;
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}
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@ -1219,7 +1243,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns
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unsigned int count;
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uint32_t val;
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flash_loader_t fl;
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ILOG("Starting Half page flash write for STM32L core id\n");
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/* flash loader initialization */
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if (init_flash_loader(sl, &fl) == -1) {
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@ -1254,7 +1278,6 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns
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while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
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}
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}
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fprintf(stdout, "\n");
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
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val &= ~(1 << FLASH_L1_PROG);
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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@ -1386,16 +1409,29 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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fprintf(stderr, "pecr.prglock not clear\n");
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return -1;
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}
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off = 0;
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if (len > L1_WRITE_BLOCK_SIZE) {
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if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
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/* This may happen on a blank device! */
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WLOG("\nwrite_half_pages failed == -1\n");
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return -1;
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}
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}
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}
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else{
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off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
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}
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}
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/* write remainingword in program memory */
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for (off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; off < len; off += sizeof(uint32_t)) {
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for ( ; off < len; off += sizeof(uint32_t)) {
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uint32_t data;
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if (off > 254)
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fprintf(stdout, "\r");
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if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
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fprintf(stdout, "\r%3u/%u pages written",
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off/sl->flash_pgsz, len/sl->flash_pgsz);
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fflush(stdout);
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}
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write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
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stlink_write_debug32(sl, addr + off, data);
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@ -1514,6 +1550,11 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
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mf.len -= num_empty;
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}
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err = stlink_write_flash(sl, addr, mf.base, mf.len);
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/* set stack*/
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stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
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/* Set PC to the reset routine*/
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stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
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stlink_run(sl);
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unmap_file(&mf);
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return err;
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}
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@ -1562,12 +1603,12 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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stlink_run(sl);
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/* wait until done (reaches breakpoint) */
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while ((is_core_halted(sl) == 0) && (i <10000))
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while ((is_core_halted(sl) == 0) && (i <1000))
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{
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i++;
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}
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|
||||
if ( i > 9999) {
|
||||
if ( i > 999) {
|
||||
fprintf(stderr, "run error\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -363,6 +363,7 @@ extern "C" {
|
|||
int stlink_erase_flash_mass(stlink_t* sl);
|
||||
int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
|
||||
int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
|
||||
int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
|
||||
int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
|
||||
|
||||
// PUBLIC
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue