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Merge pull request #36 from UweBonnes/master 

This batch implements and exposes the single data word access, jJTAG NRST and makes the F107 work when in Sleep mode.
pull/39/head
texane 2011-12-13 11:53:08 -08:00
rodzic 195eced8c9 9953efb763
commit 2e6f2b6a65
5 zmienionych plików z 209 dodań i 119 usunięć
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4
flash/main.c
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@ -108,6 +108,7 @@ int main(int ac, char** av)
stlink_enter_swd_mode(sl);
stlink_reset(sl);
stlink_load_device_params(sl);
if (o.do_read == 0) /* write */
{
@ -134,8 +135,7 @@ int main(int ac, char** av)
on_error:
if (sl != NULL)
{
stlink_reset(sl);
stlink_run(sl);
stlink_exit_debug_mode(sl);
stlink_close(sl);
}

202
src/stlink-common.c
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@ -121,29 +121,27 @@ uint32_t read_uint32(const unsigned char *c, const int pt) {
}
static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
return read_uint32(sl->q_buf, 0) & 0xff;
return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
}
static inline uint32_t read_flash_wrpr(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
return read_uint32(sl->q_buf, 0);
return stlink_read_debug32(sl, FLASH_WRPR);
}
static inline uint32_t read_flash_obr(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
return read_uint32(sl->q_buf, 0);
return stlink_read_debug32(sl, FLASH_OBR);
}
static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
if(sl->chip_id==STM32F4_CHIP_ID)
stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
res = stlink_read_debug32(sl, FLASH_F4_CR);
else
stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
res = stlink_read_debug32(sl, FLASH_CR);
#if DEBUG_FLASH
fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf);
fprintf(stdout, "CR:0x%x\n", res);
#endif
return read_uint32(sl->q_buf, 0);
return res;
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
@ -161,16 +159,12 @@ static void unlock_flash(stlink_t *sl) {
the FPEC block until next reset.
*/
if(sl->chip_id==STM32F4_CHIP_ID) {
write_uint32(sl->q_buf, FLASH_KEY1);
stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
write_uint32(sl->q_buf, FLASH_KEY2);
stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
}
else {
write_uint32(sl->q_buf, FLASH_KEY1);
stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
write_uint32(sl->q_buf, FLASH_KEY2);
stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
}
}
@ -192,14 +186,12 @@ static int unlock_flash_if(stlink_t *sl) {
static void lock_flash(stlink_t *sl) {
if(sl->chip_id==STM32F4_CHIP_ID) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_CR, n);
}
else {
/* write to 1 only. reset by hw at unlock sequence */
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
}
@ -208,47 +200,40 @@ static void set_flash_cr_pg(stlink_t *sl) {
if(sl->chip_id==STM32F4_CHIP_ID) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
write_uint32(sl->q_buf, x);
stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
else {
const uint32_t n = 1 << FLASH_CR_PG;
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
}
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
write_uint32(sl->q_buf, n);
if(sl->chip_id==STM32F4_CHIP_ID)
stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_per(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_PER;
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_mer(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_MER;
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_strt(stlink_t *sl) {
@ -256,29 +241,27 @@ static void set_flash_cr_strt(stlink_t *sl) {
{
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
write_uint32(sl->q_buf, x);
stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
else {
/* assume come on the flash_cr_per path */
const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_CR, n);
}
}
static inline uint32_t read_flash_acr(stlink_t *sl) {
stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
return read_uint32(sl->q_buf, 0);
return stlink_read_debug32(sl, FLASH_ACR);
}
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
if(sl->chip_id==STM32F4_CHIP_ID)
stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t));
res = stlink_read_debug32(sl, FLASH_F4_SR);
else
stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
res = stlink_read_debug32(sl, FLASH_SR);
//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
return read_uint32(sl->q_buf, 0);
return res;
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
@ -300,8 +283,7 @@ static inline unsigned int is_flash_eop(stlink_t *sl) {
static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_SR, n);
}
static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
@ -311,8 +293,7 @@ static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
}
static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
write_uint32(sl->q_buf, n);
stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_AR, n);
}
static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
@ -322,8 +303,7 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
#if DEBUG_FLASH
fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
#endif
write_uint32(sl->q_buf, x);
stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
@ -335,8 +315,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
#if DEBUG_FLASH
fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
#endif
write_uint32(sl->q_buf, x);
stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
#if 0 /* todo */
@ -359,6 +338,7 @@ void stlink_close(stlink_t *sl) {
void stlink_exit_debug_mode(stlink_t *sl) {
DLOG("*** stlink_exit_debug_mode ***\n");
stlink_write_debug32(sl, DHCSR, DBGKEY);
sl->backend->exit_debug_mode(sl);
}
@ -470,6 +450,11 @@ void stlink_reset(stlink_t *sl) {
sl->backend->reset(sl);
}
void stlink_jtag_reset(stlink_t *sl, int value) {
DLOG("*** stlink_jtag_reset ***\n");
sl->backend->jtag_reset(sl, value);
}
void stlink_run(stlink_t *sl) {
DLOG("*** stlink_run ***\n");
sl->backend->run(sl);
@ -524,6 +509,17 @@ void stlink_version(stlink_t *sl) {
}
}
uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
uint32_t data = sl->backend->read_debug32(sl, addr);
DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
return data;
}
void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
sl->backend->write_debug32(sl, addr, data);
}
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
if (len % 4 != 0) {
@ -918,14 +914,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
uint32_t val;
/* disable pecr protection */
write_uint32(sl->q_buf, 0x89abcdef);
stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
write_uint32(sl->q_buf, 0x02030405);
stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
/* check pecr.pelock is cleared */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0);
val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 0))
{
WLOG("pecr.pelock not clear (%#x)\n", val);
@ -933,14 +926,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
}
/* unlock program memory */
write_uint32(sl->q_buf, 0x8c9daebf);
stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
write_uint32(sl->q_buf, 0x13141516);
stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
/* check pecr.prglock is cleared */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0);
val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 1))
{
WLOG("pecr.prglock not clear (%#x)\n", val);
@ -949,14 +939,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
/* unused: unlock the option byte block */
#if 0
write_uint32(sl->q_buf, 0xfbead9c8);
stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
write_uint32(sl->q_buf, 0x24252627);
stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
/* check pecr.optlock is cleared */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0);
val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 2))
{
fprintf(stderr, "pecr.prglock not clear\n");
@ -966,8 +953,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
/* set pecr.{erase,prog} */
val |= (1 << 9) | (1 << 3);
write_uint32(sl->q_buf, val);
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
#if 0 /* fix_to_be_confirmed */
@ -977,33 +963,27 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
TEXANE: ok, if experience says so and it works for you, we comment
it. If someone has a problem, please drop an email.
*/
while (1)
while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
{
stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
}
#endif /* fix_to_be_confirmed */
/* write 0 to the first word of the page to be erased */
memset(sl->q_buf, 0, sizeof(uint32_t));
stlink_write_mem32(sl, flashaddr, sizeof(uint32_t));
stlink_write_mem32(sl, flashaddr, 0);
/* MP: It is better to wait for clearing the busy bit after issuing
page erase command, even though PM0062 recommends to wait before it.
Test shows that a few iterations is performed in the following loop
before busy bit is cleared.*/
while (1)
while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
{
stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break;
}
/* reset lock bits */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
write_uint32(sl->q_buf, val);
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
| (1 << 0) | (1 << 1) | (1 << 2);
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
}
else if (sl->core_id == STM32VL_CORE_ID)
{
@ -1260,6 +1240,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
#define PROGRESS_CHUNK_SIZE 0x1000
/* write a word in program memory */
for (off = 0; off < len; off += sizeof(uint32_t)) {
uint32_t data;
if (sl->verbose >= 1) {
if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
/* show progress. writing procedure is slow
@ -1270,8 +1251,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
}
}
memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
stlink_write_debug32(sl, addr + off, data);
/* wait for sr.busy to be cleared */
wait_flash_busy(sl);
@ -1301,28 +1282,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
#endif /* todo: check write operation */
/* disable pecr protection */
write_uint32(sl->q_buf, 0x89abcdef);
stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
write_uint32(sl->q_buf, 0x02030405);
stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
/* check pecr.pelock is cleared */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0);
val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 0)) {
fprintf(stderr, "pecr.pelock not clear\n");
return -1;
}
/* unlock program memory */
write_uint32(sl->q_buf, 0x8c9daebf);
stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
write_uint32(sl->q_buf, 0x13141516);
stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
/* check pecr.prglock is cleared */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0);
val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 1)) {
fprintf(stderr, "pecr.prglock not clear\n");
return -1;
@ -1330,6 +1305,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
/* write a word in program memory */
for (off = 0; off < len; off += sizeof(uint32_t)) {
uint32_t data;
if (sl->verbose >= 1) {
if ((off & (sl->flash_pgsz - 1)) == 0) {
/* show progress. writing procedure is slow
@ -1340,20 +1316,18 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
}
}
memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
stlink_write_mem32(sl, addr + off, data);
/* wait for sr.busy to be cleared */
while (1) {
stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
while (stlink_read_debug32(sl, STM32L_FLASH_SR & (1 << 0)) != 0) {
}
#if 0 /* todo: check redo write operation */
/* check written bytes. todo: should be on a per page basis. */
stlink_read_mem32(sl, addr + off, sizeof(uint32_t));
if (memcmp(sl->q_buf, base + off, sizeof(uint32_t))) {
data = stlink_read_debug32(sl, addr + off);
if (data == *(uint32_t*)(base + off)) {
/* re erase the page and redo the write operation */
uint32_t page;
uint32_t val;
@ -1374,10 +1348,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
/* reset lock bits */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
write_uint32(sl->q_buf, val);
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
| (1 << 0) | (1 << 1) | (1 << 2);
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
stlink_erase_flash_page(sl, page);
@ -1390,10 +1363,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
#endif /* todo: check redo write operation */
}
/* reset lock bits */
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
write_uint32(sl->q_buf, val);
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
| (1 << 0) | (1 << 1) | (1 << 2);
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
} else if (sl->core_id == STM32VL_CORE_ID) {
ILOG("Starting Flash write for VL core id\n");
/* flash loader initialization */

15
src/stlink-common.h
Wyświetl plik

@ -70,6 +70,10 @@ extern "C" {
// TODO - possible poor names...
#define STLINK_SWD_ENTER 0x30
#define STLINK_SWD_READCOREID 0x32 // TBD
#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
#define STLINK_JTAG_READDEBUG_32BIT 0x36
#define STLINK_JTAG_DRIVE_NRST 0x3c
#define STLINK_JTAG_DRIVE_NRST 0x3c
// cortex m3 technical reference manual
#define CM3_REG_CPUID 0xE000ED00
@ -108,6 +112,11 @@ extern "C" {
/* using chip id for F4 ident, since core id is same as F1 */
#define STM32F4_CHIP_ID 0x413
/* Cortex™-M3 Technical Reference Manual */
/* Debug Halting Control and Status Register */
#define DHCSR 0xe000edf0
#define DBGKEY 0xa05f0000
/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
#define C_BUF_LEN 32
@ -267,10 +276,13 @@ extern "C" {
void (*exit_dfu_mode) (stlink_t * stl);
void (*core_id) (stlink_t * stl);
void (*reset) (stlink_t * stl);
void (*jtag_reset) (stlink_t * stl, int value);
void (*run) (stlink_t * stl);
void (*status) (stlink_t * stl);
void (*version) (stlink_t *sl);
uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
void (*read_all_regs) (stlink_t *sl, reg * regp);
@ -330,10 +342,13 @@ extern "C" {
void stlink_close(stlink_t *sl);
uint32_t stlink_core_id(stlink_t *sl);
void stlink_reset(stlink_t *sl);
void stlink_jtag_reset(stlink_t *sl, int value);
void stlink_run(stlink_t *sl);
void stlink_status(stlink_t *sl);
void stlink_version(stlink_t *sl);
uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_read_all_regs(stlink_t *sl, reg *regp);

45
src/stlink-sg.c
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@ -537,6 +537,19 @@ void _stlink_sg_reset(stlink_t *sl) {
stlink_stat(sl, "core reset");
}
// Arm-core reset -> halted state.
void _stlink_sg_jtag_reset(stlink_t *sl, int value) {
struct stlink_libsg *sg = sl->backend_data;
clear_cdb(sg);
sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST;
sg->cdb_cmd_blk[2] = (value)?0:1;
sl->q_len = 3;
sg->q_addr = 2;
stlink_q(sl);
stlink_stat(sl, "core reset");
}
// Arm-core status: halted or running.
void _stlink_sg_status(stlink_t *sl) {
@ -792,6 +805,34 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
stlink_print_data(sl);
}
// Write one DWORD data to memory
void _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
struct stlink_libsg *sg = sl->backend_data;
clear_cdb(sg);
sg->cdb_cmd_blk[1] = STLINK_JTAG_WRITEDEBUG_32BIT;
// 2-5: addr
write_uint32(sg->cdb_cmd_blk + 2, addr);
write_uint32(sg->cdb_cmd_blk + 6, data);
sl->q_len = 2;
stlink_q(sl);
}
// Read one DWORD data from memory
uint32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr) {
struct stlink_libsg *sg = sl->backend_data;
clear_cdb(sg);
sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT;
// 2-5: addr
write_uint32(sg->cdb_cmd_blk + 2, addr);
sl->q_len = 8;
stlink_q(sl);
return read_uint32(sl->q_buf, 4);
}
// Exit the jtag or swd mode and enter the mass mode.
void _stlink_sg_exit_debug_mode(stlink_t *stl) {
@ -820,10 +861,13 @@ stlink_backend_t _stlink_sg_backend = {
_stlink_sg_exit_dfu_mode,
_stlink_sg_core_id,
_stlink_sg_reset,
_stlink_sg_jtag_reset,
_stlink_sg_run,
_stlink_sg_status,
_stlink_sg_version,
_stlink_sg_read_debug32,
_stlink_sg_read_mem32,
_stlink_sg_write_debug32,
_stlink_sg_write_mem32,
_stlink_sg_write_mem8,
_stlink_sg_read_all_regs,
@ -981,7 +1025,6 @@ stlink_t* stlink_v1_open(const int verbose) {
}
// by now, it _must_ be fully open and in a useful mode....
stlink_enter_swd_mode(sl);
stlink_load_device_params(sl);
ILOG("Successfully opened a stlink v1 debugger\n");
return sl;
}

62
src/stlink-usb.c
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@ -189,6 +189,44 @@ void _stlink_usb_version(stlink_t *sl) {
}
}
uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const rdata = sl->q_buf;
unsigned char* const cmd = sl->c_buf;
ssize_t size;
const int rep_len = 8;
int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len);
cmd[i++] = STLINK_DEBUG_COMMAND;
cmd[i++] = STLINK_JTAG_READDEBUG_32BIT;
write_uint32(&cmd[i], addr);
size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len);
if (size == -1) {
printf("[!] send_recv\n");
return;
}
return read_uint32(rdata, 4);
}
void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const rdata = sl->q_buf;
unsigned char* const cmd = sl->c_buf;
ssize_t size;
const int rep_len = 2;
int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len);
cmd[i++] = STLINK_DEBUG_COMMAND;
cmd[i++] = STLINK_JTAG_WRITEDEBUG_32BIT;
write_uint32(&cmd[i], addr);
write_uint32(&cmd[i + 4], data);
size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len);
if (size == -1) {
printf("[!] send_recv\n");
return;
}
}
void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const data = sl->q_buf;
@ -348,6 +386,26 @@ void _stlink_usb_reset(stlink_t * sl) {
}
void _stlink_usb_jtag_reset(stlink_t * sl, int value) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const data = sl->q_buf;
unsigned char* const cmd = sl->c_buf;
ssize_t size;
int rep_len = 2;
int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len);
cmd[i++] = STLINK_DEBUG_COMMAND;
cmd[i++] = STLINK_JTAG_DRIVE_NRST;
cmd[i++] = (value)?0:1;
size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len);
if (size == -1) {
printf("[!] send_recv\n");
return;
}
}
void _stlink_usb_step(stlink_t* sl) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const data = sl->q_buf;
@ -533,10 +591,13 @@ stlink_backend_t _stlink_usb_backend = {
_stlink_usb_exit_dfu_mode,
_stlink_usb_core_id,
_stlink_usb_reset,
_stlink_usb_jtag_reset,
_stlink_usb_run,
_stlink_usb_status,
_stlink_usb_version,
_stlink_usb_read_debug32,
_stlink_usb_read_mem32,
_stlink_usb_write_debug32,
_stlink_usb_write_mem32,
_stlink_usb_write_mem8,
_stlink_usb_read_all_regs,
@ -641,7 +702,6 @@ stlink_t* stlink_open_usb(const int verbose) {
}
stlink_version(sl);
stlink_load_device_params(sl);
error = 0;