kopia lustrzana https://github.com/stlink-org/stlink
Flash loader for STM32L4
Dave Vandervies
rodzic
ab464492f7
commit
0419b8bec6
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@ -0,0 +1,39 @@
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.global start
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.syntax unified
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@ Adapted from stm32f4.s
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@ STM32L4's flash controller expects double-word writes, has the flash
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@ controller mapped in a different location with the registers we care about
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@ moved down from the base address, and has BSY moved to bit 16 of SR.
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@ r0 = source
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@ r1 = target
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@ r2 = wordcount
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@ r3 = flash_base
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@ r4 = temp
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@ r5 = temp
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start:
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ldr r3, flash_base
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next:
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cbz r2, done
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ldr r4, [r0] /* copy doubleword from source to target */
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ldr r5, [r0, #4]
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str r4, [r1]
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str r5, [r1, #4]
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wait:
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ldrh r4, [r3, #0x12] /* high half of status register */
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tst r4, #1 /* BSY = bit 16 */
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bne wait
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add r0, #8
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add r1, #8
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sub r2, #2
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b next
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done:
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bkpt
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.align 2
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flash_base:
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.word 0x40022000
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@ -1503,6 +1503,25 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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0x00, 0x3c, 0x02, 0x40,
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};
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static const uint8_t loader_code_stm32l4[] = {
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// flashloaders/stm32l4.s
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0x08, 0x4b, // start: ldr r3, [pc, #32] ; <flash_base>
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0x72, 0xb1, // next: cbz r2, <done>
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0x04, 0x68, // ldr r4, [r0, #0]
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0x45, 0x68, // ldr r5, [r0, #4]
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0x0c, 0x60, // str r4, [r1, #0]
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0x4d, 0x60, // str r5, [r1, #4]
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0x5c, 0x8a, // wait: ldrh r4, [r3, #18]
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0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1
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0xfb, 0xd1, // bne.n <wait>
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0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8
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0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8
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0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2
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0xef, 0xe7, // b.n <next>
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0x00, 0xbe, // done: bkpt 0x0000
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0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
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};
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const uint8_t* loader_code;
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size_t loader_size;
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@ -1535,6 +1554,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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} else if (sl->chip_id == STM32_CHIPID_L0) {
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loader_code = loader_code_stm32l0;
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loader_size = sizeof(loader_code_stm32l0);
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} else if (sl->chip_id == STM32_CHIPID_L4) {
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loader_code = loader_code_stm32l4;
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loader_size = sizeof(loader_code_stm32l4);
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} else {
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ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
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return -1;
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@ -1710,10 +1732,11 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
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(sl->chip_id == STM32_CHIPID_F4_LP) ||
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(sl->chip_id == STM32_CHIPID_F4_HD) ||
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(sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446)) {
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(sl->chip_id == STM32_CHIPID_F446) ||
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(sl->chip_id == STM32_CHIPID_L4)) {
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/* todo: check write operation */
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ILOG("Starting Flash write for F2/F4\n");
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ILOG("Starting Flash write for F2/F4/L4\n");
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/* flash loader initialization */
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if (init_flash_loader(sl, &fl) == -1) {
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ELOG("init_flash_loader() == -1\n");
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@ -1724,14 +1747,23 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
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unlock_flash_if(sl);
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/* TODO: Check that Voltage range is 2.7 - 3.6 V */
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/* set parallelisim to 32 bit*/
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int voltage = stlink_target_voltage(sl);
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if (voltage > 2700) {
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printf("enabling 32-bit flash writes\n");
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write_flash_cr_psiz(sl, 2);
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if (sl->chip_id != STM32_CHIPID_L4) {
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/* set parallelisim to 32 bit*/
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int voltage = stlink_target_voltage(sl);
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if (voltage > 2700) {
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printf("enabling 32-bit flash writes\n");
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write_flash_cr_psiz(sl, 2);
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} else {
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printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
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write_flash_cr_psiz(sl, 0);
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}
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} else {
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printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
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write_flash_cr_psiz(sl, 0);
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/* L4 does not have a byte-write mode */
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int voltage = stlink_target_voltage(sl);
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if (voltage <= 2700) {
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printf("Target voltage (%d mV) too low for flash writes!\n", voltage);
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return -1;
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}
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}
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/* set programming mode */
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@ -1960,10 +1992,13 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
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sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446)) {
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(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
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size_t count = size / sizeof(uint32_t);
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if (size % sizeof(uint32_t)) ++count;
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if (sl->chip_id == STM32_CHIPID_L4) {
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if (count % 2) ++count;
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}
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/* setup core */
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stlink_write_reg(sl, fl->buf_addr, 0); /* source */
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@ -2021,7 +2056,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
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sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446)) {
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(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
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stlink_read_reg(sl, 2, &rr);
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if (rr.r[2] != 0) {
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