kopia lustrzana https://github.com/stlink-org/stlink
Use the single WORD memory access
Uwe Bonnes
rodzic
9ef6d28cb5
commit
03e745140d
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@ -121,29 +121,27 @@ uint32_t read_uint32(const unsigned char *c, const int pt) {
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}
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static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
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stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
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return read_uint32(sl->q_buf, 0) & 0xff;
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return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
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}
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static inline uint32_t read_flash_wrpr(stlink_t *sl) {
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stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
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return read_uint32(sl->q_buf, 0);
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return stlink_read_debug32(sl, FLASH_WRPR);
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}
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static inline uint32_t read_flash_obr(stlink_t *sl) {
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stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
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return read_uint32(sl->q_buf, 0);
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return stlink_read_debug32(sl, FLASH_OBR);
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}
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static inline uint32_t read_flash_cr(stlink_t *sl) {
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uint32_t res;
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if(sl->chip_id==STM32F4_CHIP_ID)
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stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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res = stlink_read_debug32(sl, FLASH_F4_CR);
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else
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stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
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res = stlink_read_debug32(sl, FLASH_CR);
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#if DEBUG_FLASH
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fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf);
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fprintf(stdout, "CR:0x%x\n", res);
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#endif
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return read_uint32(sl->q_buf, 0);
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return res;
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}
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static inline unsigned int is_flash_locked(stlink_t *sl) {
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@ -161,16 +159,12 @@ static void unlock_flash(stlink_t *sl) {
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the FPEC block until next reset.
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*/
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if(sl->chip_id==STM32F4_CHIP_ID) {
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write_uint32(sl->q_buf, FLASH_KEY1);
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stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
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write_uint32(sl->q_buf, FLASH_KEY2);
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stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
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stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
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}
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else {
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write_uint32(sl->q_buf, FLASH_KEY1);
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stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
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write_uint32(sl->q_buf, FLASH_KEY2);
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stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
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stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
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}
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}
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@ -192,14 +186,12 @@ static int unlock_flash_if(stlink_t *sl) {
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static void lock_flash(stlink_t *sl) {
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if(sl->chip_id==STM32F4_CHIP_ID) {
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const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_CR, n);
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}
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else {
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/* write to 1 only. reset by hw at unlock sequence */
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const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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}
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@ -208,47 +200,40 @@ static void set_flash_cr_pg(stlink_t *sl) {
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if(sl->chip_id==STM32F4_CHIP_ID) {
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uint32_t x = read_flash_cr(sl);
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x |= (1 << FLASH_CR_PG);
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write_uint32(sl->q_buf, x);
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stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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}
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else {
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const uint32_t n = 1 << FLASH_CR_PG;
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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}
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static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
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const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
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write_uint32(sl->q_buf, n);
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if(sl->chip_id==STM32F4_CHIP_ID)
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stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_CR, n);
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else
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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static void set_flash_cr_per(stlink_t *sl) {
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const uint32_t n = 1 << FLASH_CR_PER;
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
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const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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static void set_flash_cr_mer(stlink_t *sl) {
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const uint32_t n = 1 << FLASH_CR_MER;
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
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const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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static void set_flash_cr_strt(stlink_t *sl) {
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@ -256,29 +241,27 @@ static void set_flash_cr_strt(stlink_t *sl) {
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{
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uint32_t x = read_flash_cr(sl);
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x |= (1 << FLASH_F4_CR_STRT);
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write_uint32(sl->q_buf, x);
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stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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}
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else {
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/* assume come on the flash_cr_per path */
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const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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}
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static inline uint32_t read_flash_acr(stlink_t *sl) {
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stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
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return read_uint32(sl->q_buf, 0);
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return stlink_read_debug32(sl, FLASH_ACR);
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}
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static inline uint32_t read_flash_sr(stlink_t *sl) {
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uint32_t res;
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if(sl->chip_id==STM32F4_CHIP_ID)
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stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t));
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res = stlink_read_debug32(sl, FLASH_F4_SR);
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else
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stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
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res = stlink_read_debug32(sl, FLASH_SR);
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//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
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return read_uint32(sl->q_buf, 0);
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return res;
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}
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static inline unsigned int is_flash_busy(stlink_t *sl) {
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@ -300,8 +283,7 @@ static inline unsigned int is_flash_eop(stlink_t *sl) {
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static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
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const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_SR, n);
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}
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static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
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@ -311,8 +293,7 @@ static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
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}
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static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
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write_uint32(sl->q_buf, n);
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stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_AR, n);
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}
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static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
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@ -322,8 +303,7 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
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#if DEBUG_FLASH
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fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
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#endif
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write_uint32(sl->q_buf, x);
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stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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}
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@ -335,8 +315,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
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#if DEBUG_FLASH
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fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
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#endif
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write_uint32(sl->q_buf, x);
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stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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}
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#if 0 /* todo */
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@ -935,14 +914,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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uint32_t val;
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/* disable pecr protection */
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write_uint32(sl->q_buf, 0x89abcdef);
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stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
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write_uint32(sl->q_buf, 0x02030405);
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stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
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stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
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stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
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/* check pecr.pelock is cleared */
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stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = read_uint32(sl->q_buf, 0);
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
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if (val & (1 << 0))
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{
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WLOG("pecr.pelock not clear (%#x)\n", val);
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@ -950,14 +926,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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}
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/* unlock program memory */
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write_uint32(sl->q_buf, 0x8c9daebf);
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stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
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write_uint32(sl->q_buf, 0x13141516);
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stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
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stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
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stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
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/* check pecr.prglock is cleared */
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stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = read_uint32(sl->q_buf, 0);
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
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if (val & (1 << 1))
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{
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WLOG("pecr.prglock not clear (%#x)\n", val);
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@ -966,14 +939,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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/* unused: unlock the option byte block */
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#if 0
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write_uint32(sl->q_buf, 0xfbead9c8);
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stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
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write_uint32(sl->q_buf, 0x24252627);
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stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
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stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
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stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
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/* check pecr.optlock is cleared */
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stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = read_uint32(sl->q_buf, 0);
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
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if (val & (1 << 2))
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{
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fprintf(stderr, "pecr.prglock not clear\n");
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@ -983,8 +953,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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/* set pecr.{erase,prog} */
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val |= (1 << 9) | (1 << 3);
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write_uint32(sl->q_buf, val);
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stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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#if 0 /* fix_to_be_confirmed */
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@ -994,33 +963,27 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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TEXANE: ok, if experience says so and it works for you, we comment
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it. If someone has a problem, please drop an email.
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*/
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while (1)
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while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
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{
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stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
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if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
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}
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#endif /* fix_to_be_confirmed */
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/* write 0 to the first word of the page to be erased */
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memset(sl->q_buf, 0, sizeof(uint32_t));
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stlink_write_mem32(sl, flashaddr, sizeof(uint32_t));
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stlink_write_mem32(sl, flashaddr, 0);
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/* MP: It is better to wait for clearing the busy bit after issuing
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page erase command, even though PM0062 recommends to wait before it.
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Test shows that a few iterations is performed in the following loop
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before busy bit is cleared.*/
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while (1)
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while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
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{
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stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
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if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break;
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}
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/* reset lock bits */
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stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
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write_uint32(sl->q_buf, val);
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stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
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| (1 << 0) | (1 << 1) | (1 << 2);
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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}
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else if (sl->core_id == STM32VL_CORE_ID)
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{
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@ -1318,28 +1281,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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#endif /* todo: check write operation */
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/* disable pecr protection */
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write_uint32(sl->q_buf, 0x89abcdef);
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stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
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write_uint32(sl->q_buf, 0x02030405);
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stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
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stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
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stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
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/* check pecr.pelock is cleared */
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stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = read_uint32(sl->q_buf, 0);
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
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if (val & (1 << 0)) {
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fprintf(stderr, "pecr.pelock not clear\n");
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return -1;
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}
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/* unlock program memory */
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write_uint32(sl->q_buf, 0x8c9daebf);
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stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
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write_uint32(sl->q_buf, 0x13141516);
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stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
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stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
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stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
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/* check pecr.prglock is cleared */
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stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
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val = read_uint32(sl->q_buf, 0);
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
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if (val & (1 << 1)) {
|
||||
fprintf(stderr, "pecr.prglock not clear\n");
|
||||
return -1;
|
||||
|
|
@ -1361,9 +1318,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
|
|||
stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
|
||||
|
||||
/* wait for sr.busy to be cleared */
|
||||
while (1) {
|
||||
stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
|
||||
if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
|
||||
while (stlink_read_debug32(sl, STM32L_FLASH_SR & (1 << 0)) != 0) {
|
||||
}
|
||||
|
||||
#if 0 /* todo: check redo write operation */
|
||||
|
|
@ -1391,10 +1346,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
|
|||
page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
|
||||
|
||||
/* reset lock bits */
|
||||
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
|
||||
val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
|
||||
write_uint32(sl->q_buf, val);
|
||||
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
|
||||
val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
|
||||
| (1 << 0) | (1 << 1) | (1 << 2);
|
||||
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
|
||||
|
||||
stlink_erase_flash_page(sl, page);
|
||||
|
||||
|
|
@ -1407,10 +1361,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
|
|||
#endif /* todo: check redo write operation */
|
||||
}
|
||||
/* reset lock bits */
|
||||
stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
|
||||
val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
|
||||
write_uint32(sl->q_buf, val);
|
||||
stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
|
||||
val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
|
||||
| (1 << 0) | (1 << 1) | (1 << 2);
|
||||
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
|
||||
} else if (sl->core_id == STM32VL_CORE_ID) {
|
||||
ILOG("Starting Flash write for VL core id\n");
|
||||
/* flash loader initialization */
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue