2019-03-20 13:01:11 +00:00
|
|
|
/*
|
2020-06-12 20:28:16 +00:00
|
|
|
* File: stm32.h
|
2019-03-20 13:01:11 +00:00
|
|
|
*
|
2020-06-12 20:28:16 +00:00
|
|
|
* STM32-specific defines
|
2019-03-20 13:01:11 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef STM32_H
|
|
|
|
#define STM32_H
|
|
|
|
|
2020-06-12 20:28:16 +00:00
|
|
|
/* Cortex core ids */
|
2019-03-20 13:01:11 +00:00
|
|
|
#define STM32VL_CORE_ID 0x1ba01477
|
|
|
|
#define STM32F7_CORE_ID 0x5ba02477
|
2020-10-27 06:41:39 +00:00
|
|
|
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065)
|
2019-03-20 13:01:11 +00:00
|
|
|
|
2020-06-12 20:28:16 +00:00
|
|
|
/* Constant STM32 memory map figures */
|
2019-03-20 13:01:11 +00:00
|
|
|
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
|
2020-11-09 08:41:51 +00:00
|
|
|
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
|
|
|
|
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
|
2019-03-20 13:01:11 +00:00
|
|
|
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
|
|
|
|
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
|
2020-04-06 12:01:35 +00:00
|
|
|
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
|
2020-04-14 15:35:15 +00:00
|
|
|
#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
|
2019-10-07 05:46:36 +00:00
|
|
|
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000)
|
2020-04-14 15:35:15 +00:00
|
|
|
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
|
2020-02-21 00:07:52 +00:00
|
|
|
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
|
2020-10-27 09:28:48 +00:00
|
|
|
#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14)
|
2020-06-25 08:48:51 +00:00
|
|
|
#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000)
|
2020-10-19 12:29:54 +00:00
|
|
|
#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C)
|
2020-02-21 00:07:52 +00:00
|
|
|
|
2020-06-12 20:28:16 +00:00
|
|
|
#endif // STM32_H
|