stlink/config/chips/F401xD_xE.chip

# Chip-ID file for STM32F401xD/xE device
#
dev_type STM32F401xD_xE
ref_manual_id 0368
chip_id 0x433                // STM32_CHIPID_F4_DE
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000        // 16 KB
sram_size 0x18000            // 96 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800          // 30 KB
option_base 0x40023C14       // STM32_F4_OPTION_BYTES_BASE
option_size 0x4              // 4 B
flags swo
[refactoring] Clean-up & update for chipid files - F0, F1, F2, F3, F4, F7 - G0, G4 - H7 - L0, L5, U5 - WB, WL 2022-01-06 18:30:49 +00:00			`# Chip-ID file for STM32F401xD/xE device`
			`#`
			`dev_type STM32F401xD_xE`
			`ref_manual_id 0368`
[refactoring] Clean-up for headers & defines - Removed additional extern "C" linkage specs - Removed commented sections - Moved out further device specific defines - Renamed defines STM32_CHIP_ID_* 2022-01-16 18:31:22 +00:00			`chip_id 0x433 // STM32_CHIPID_F4_DE`
Updated device parametres - Human-readable FLASH_TYPE in .chip files - Added enum for STM32_CORE_IDs 2022-01-20 22:19:10 +00:00			`flash_type F2_F4`
[refactoring] Clean-up & update for chipid files - F0, F1, F2, F3, F4, F7 - G0, G4 - H7 - L0, L5, U5 - WB, WL 2022-01-06 18:30:49 +00:00			`flash_size_reg 0x1fff7a22`
			`flash_pagesize 0x4000 // 16 KB`
			`sram_size 0x18000 // 96 KB`
			`bootrom_base 0x1fff0000`
			`bootrom_size 0x7800 // 30 KB`
Minor fixes & additions - [doc] Update on OS version support - Minor fixes for G0-series from #1293 - [doc] Added core-IDs for WB/WL-series - [doc] Correction for G0/L0-series core-IDs - Set option_size to 128 B for G0-series (#1194) 2023-03-18 20:53:27 +00:00			`option_base 0x40023C14 // STM32_F4_OPTION_BYTES_BASE`
			`option_size 0x4 // 4 B`
[refactoring] Clean-up & update for chipid files - F0, F1, F2, F3, F4, F7 - G0, G4 - H7 - L0, L5, U5 - WB, WL 2022-01-06 18:30:49 +00:00			`flags swo`