From a195408a11d72f57783aea21bd78ab047d668cc8 Mon Sep 17 00:00:00 2001 From: Conor Patrick Date: Tue, 26 Feb 2019 01:51:07 -0500 Subject: [PATCH] scale up to 24 MHz only for register --- targets/stm32l432/src/init.c | 8 ++++---- targets/stm32l432/src/nfc.c | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/targets/stm32l432/src/init.c b/targets/stm32l432/src/init.c index c7dfcb5..6272f97 100644 --- a/targets/stm32l432/src/init.c +++ b/targets/stm32l432/src/init.c @@ -49,7 +49,7 @@ #include APP_CONFIG // KHz -#define CLOCK_RATE 24000 +#define CLOCK_RATE 16000 USBD_HandleTypeDef Solo_USBD_Device; @@ -360,7 +360,7 @@ void SystemClock_Config_LF16(void) { Error_Handler(); } - LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2); LL_RCC_LSI_Enable(); @@ -423,7 +423,7 @@ void SystemClock_Config_LF24(void) { Error_Handler(); } - LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2); LL_RCC_LSI_Enable(); @@ -927,7 +927,7 @@ void init_spi(void) SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; - SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; SPI_InitStruct.CRCPoly = 7; diff --git a/targets/stm32l432/src/nfc.c b/targets/stm32l432/src/nfc.c index 2eb76d5..0299d13 100644 --- a/targets/stm32l432/src/nfc.c +++ b/targets/stm32l432/src/nfc.c @@ -485,8 +485,9 @@ void nfc_process_iblock(uint8_t * buf, int len) // WTX_on(WTX_TIME_DEFAULT); // SystemClock_Config_LF32(); // delay(300); + SystemClock_Config_LF24(); u2f_request_nfc(&buf[1], len, &ctap_resp); - // SystemClock_Config_LF16(); + SystemClock_Config_LF16(); // if (!WTX_off()) // return;