kopia lustrzana https://github.com/solokeys/solo1
add rng
Conor Patrick
rodzic
b9220defcc
commit
271d7f81f0
File diff suppressed because one or more lines are too long
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@ -1,6 +1,7 @@
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<?xml version="1.0" encoding="ASCII"?>
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<device:XMLDevice xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:device="http://www.silabs.com/ss/hwconfig/document/device.ecore" name="EFM32PG1B200F256GM48" partId="mcu.arm.efm32.pg1.efm32pg1b200f256gm48" contextId="%DEFAULT%">
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<mode name="DefaultMode">
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<property object="ADC0" propertyId="ABPeripheral.included" value="true"/>
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<property object="CMU" propertyId="ABPeripheral.included" value="true"/>
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<property object="CMU" propertyId="clocksettings.hfrcosettings.hfrcofrequency" value="38 MHz"/>
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<property object="CMU" propertyId="clocksettings.lfclocksettings.lfrcorequired" value="Yes"/>
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Plik diff jest za duży
Load Diff
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@ -0,0 +1,355 @@
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/***************************************************************************//**
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* @file em_ldma.c
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* @brief Direct memory access (LDMA) module peripheral API
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* @version 5.2.2
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*******************************************************************************
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* # License
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* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
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*******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.@n
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.@n
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
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* obligation to support this Software. Silicon Labs is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Silicon Labs will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#include "em_ldma.h"
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#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
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#include <stddef.h>
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#include "em_assert.h"
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#include "em_bus.h"
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#include "em_cmu.h"
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#include "em_core.h"
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/***************************************************************************//**
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* @addtogroup emlib
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup LDMA
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* @{
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******************************************************************************/
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#if defined(LDMA_IRQ_HANDLER_TEMPLATE)
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/***************************************************************************//**
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* @brief
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* Template for an LDMA IRQ handler.
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******************************************************************************/
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void LDMA_IRQHandler(void)
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{
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uint32_t ch;
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/* Get all pending and enabled interrupts. */
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uint32_t pending = LDMA_IntGetEnabled();
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/* Loop here on an LDMA error to enable debugging. */
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while (pending & LDMA_IF_ERROR) {
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}
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/* Iterate over all LDMA channels. */
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for (ch = 0; ch < DMA_CHAN_COUNT; ch++) {
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uint32_t mask = 0x1 << ch;
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if (pending & mask) {
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/* Clear interrupt flag. */
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LDMA->IFC = mask;
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/* Do more stuff here, execute callbacks etc. */
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}
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}
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}
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#endif
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/***************************************************************************//**
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* @brief
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* De-initialize the LDMA controller.
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*
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* LDMA interrupts are disabled and the LDMA clock is stopped.
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******************************************************************************/
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void LDMA_DeInit(void)
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{
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NVIC_DisableIRQ(LDMA_IRQn);
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LDMA->IEN = 0;
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LDMA->CHEN = 0;
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CMU_ClockEnable(cmuClock_LDMA, false);
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}
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/***************************************************************************//**
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* @brief
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* Enable or disable a LDMA channel request.
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*
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* @details
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* Use this function to enable or disable a LDMA channel request. This will
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* prevent the LDMA from proceeding after its current transaction if disabled.
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*
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* @param[in] channel
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* LDMA channel to enable or disable requests on.
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*
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* @param[in] enable
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* If 'true' request will be enabled. If 'false' request will be disabled.
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******************************************************************************/
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void LDMA_EnableChannelRequest(int ch, bool enable)
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{
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EFM_ASSERT(ch < DMA_CHAN_COUNT);
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BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable);
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}
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/***************************************************************************//**
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* @brief
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* Initialize the LDMA controller.
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*
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* @details
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* This function will disable all the LDMA channels and enable the LDMA bus
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* clock in the CMU. This function will also enable the LDMA IRQ in the NVIC
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* and set the LDMA IRQ priority to a user configurable priority. The LDMA
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* interrupt priority is configured using the @ref LDMA_Init_t structure.
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*
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* @note
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* Since this function enables the LDMA IRQ you should always add a custom
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* LDMA_IRQHandler to the application in order to handle any interrupts
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* from LDMA.
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*
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* @param[in] init
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* Pointer to initialization structure used to configure the LDMA.
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******************************************************************************/
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void LDMA_Init(const LDMA_Init_t *init)
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{
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EFM_ASSERT(init != NULL);
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EFM_ASSERT(!((init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT)
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& ~_LDMA_CTRL_NUMFIXED_MASK));
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EFM_ASSERT(!((init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT)
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& ~_LDMA_CTRL_SYNCPRSCLREN_MASK));
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EFM_ASSERT(!((init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT)
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& ~_LDMA_CTRL_SYNCPRSSETEN_MASK));
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EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS));
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CMU_ClockEnable(cmuClock_LDMA, true);
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LDMA->CTRL = (init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT)
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| (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT)
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| (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
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LDMA->CHEN = 0;
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LDMA->DBGHALT = 0;
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LDMA->REQDIS = 0;
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/* Enable LDMA error interrupt. */
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LDMA->IEN = LDMA_IEN_ERROR;
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LDMA->IFC = 0xFFFFFFFF;
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NVIC_ClearPendingIRQ(LDMA_IRQn);
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/* Range is 0..7, 0 is highest priority. */
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NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority);
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NVIC_EnableIRQ(LDMA_IRQn);
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}
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/***************************************************************************//**
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* @brief
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* Start a DMA transfer.
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*
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* @param[in] ch
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* DMA channel.
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*
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* @param[in] transfer
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* Initialization structure used to configure the transfer.
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*
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* @param[in] descriptor
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* Transfer descriptor, can be an array of descriptors linked together.
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******************************************************************************/
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void LDMA_StartTransfer(int ch,
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const LDMA_TransferCfg_t *transfer,
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const LDMA_Descriptor_t *descriptor)
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{
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uint32_t tmp;
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CORE_DECLARE_IRQ_STATE;
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uint32_t chMask = 1 << ch;
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EFM_ASSERT(ch < DMA_CHAN_COUNT);
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EFM_ASSERT(transfer != NULL);
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EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK));
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EFM_ASSERT(!((transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT)
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& ~_LDMA_CTRL_SYNCPRSCLREN_MASK));
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EFM_ASSERT(!((transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT)
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& ~_LDMA_CTRL_SYNCPRSCLREN_MASK));
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EFM_ASSERT(!((transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT)
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& ~_LDMA_CTRL_SYNCPRSSETEN_MASK));
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EFM_ASSERT(!((transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT)
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& ~_LDMA_CTRL_SYNCPRSSETEN_MASK));
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EFM_ASSERT(!((transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT)
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& ~_LDMA_CH_CFG_ARBSLOTS_MASK));
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EFM_ASSERT(!((transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT)
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& ~_LDMA_CH_CFG_SRCINCSIGN_MASK) );
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EFM_ASSERT(!((transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT)
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& ~_LDMA_CH_CFG_DSTINCSIGN_MASK));
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EFM_ASSERT(!((transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT)
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& ~_LDMA_CH_LOOP_LOOPCNT_MASK));
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LDMA->CH[ch].REQSEL = transfer->ldmaReqSel;
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LDMA->CH[ch].LOOP = (transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT);
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LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT)
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| (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT)
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| (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT);
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/* Set descriptor address. */
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LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK;
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/* Clear pending channel interrupt. */
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LDMA->IFC = chMask;
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/* Critical region. */
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CORE_ENTER_ATOMIC();
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/* Enable channel interrupt. */
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LDMA->IEN |= chMask;
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if (transfer->ldmaReqDis) {
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LDMA->REQDIS |= chMask;
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}
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if (transfer->ldmaDbgHalt) {
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LDMA->DBGHALT |= chMask;
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}
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tmp = LDMA->CTRL;
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if (transfer->ldmaCtrlSyncPrsClrOff) {
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tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK
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| (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT);
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}
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if (transfer->ldmaCtrlSyncPrsClrOn) {
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tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT;
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}
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if (transfer->ldmaCtrlSyncPrsSetOff) {
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tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK
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| (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
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}
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if (transfer->ldmaCtrlSyncPrsSetOn) {
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tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT;
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}
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LDMA->CTRL = tmp;
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BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */
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LDMA->LINKLOAD = chMask; /* Start transfer by loading descriptor. */
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/* Critical region end. */
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CORE_EXIT_ATOMIC();
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}
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/***************************************************************************//**
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* @brief
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* Stop a DMA transfer.
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*
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* @note
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* The DMA will complete the current AHB burst transfer before stopping.
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*
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* @param[in] ch
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* DMA channel to stop.
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******************************************************************************/
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void LDMA_StopTransfer(int ch)
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{
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uint32_t chMask = 1 << ch;
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EFM_ASSERT(ch < DMA_CHAN_COUNT);
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CORE_ATOMIC_SECTION(
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LDMA->IEN &= ~chMask;
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BUS_RegMaskedClear(&LDMA->CHEN, chMask);
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)
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}
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/***************************************************************************//**
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* @brief
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* Check if a DMA transfer has completed.
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*
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* @param[in] ch
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* DMA channel to check.
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*
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* @return
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* True if transfer has completed, false if not.
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******************************************************************************/
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bool LDMA_TransferDone(int ch)
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{
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bool retVal = false;
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uint32_t chMask = 1 << ch;
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EFM_ASSERT(ch < DMA_CHAN_COUNT);
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CORE_ATOMIC_SECTION(
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if (((LDMA->CHEN & chMask) == 0)
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&& ((LDMA->CHDONE & chMask) == chMask)) {
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retVal = true;
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}
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)
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return retVal;
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}
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/***************************************************************************//**
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* @brief
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* Get number of items remaining in a transfer.
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*
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* @note
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* This function is does not take into account that a DMA transfers with
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* a chain of linked transfers might be ongoing. It will only check the
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* count for the current transfer.
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*
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* @param[in] ch
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* The channel number of the transfer to check.
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*
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* @return
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* Number of items remaining in the transfer.
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******************************************************************************/
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uint32_t LDMA_TransferRemainingCount(int ch)
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{
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uint32_t remaining, done, iflag;
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uint32_t chMask = 1 << ch;
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EFM_ASSERT(ch < DMA_CHAN_COUNT);
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CORE_ATOMIC_SECTION(
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iflag = LDMA->IF;
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done = LDMA->CHDONE;
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remaining = LDMA->CH[ch].CTRL;
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)
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iflag &= chMask;
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done &= chMask;
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remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK)
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>> _LDMA_CH_CTRL_XFERCNT_SHIFT;
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if (done || ((remaining == 0) && iflag)) {
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return 0;
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}
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return remaining + 1;
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}
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/** @} (end addtogroup LDMA) */
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/** @} (end addtogroup emlib) */
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#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
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@ -253,7 +253,7 @@
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#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT
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#define MBEDTLS_ECP_DEVICE_ADD_MIXED_ALT
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//#define MBEDTLS_ENTROPY_ALT
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//#define MBEDTLS_MPI_MUL_MPI_ALT // doesnt seem to be implemented
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//#define MBEDTLS_MPI_MUL_INT_ALT // makes no difference or slightly slower
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@ -19,6 +19,7 @@
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#include "em_device.h"
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#include "em_chip.h"
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#include "em_assert.h"
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#include "em_adc.h"
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#include "em_cryotimer.h"
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#include "em_crypto.h"
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#include "em_gpio.h"
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|
@ -35,6 +36,7 @@ extern void enter_DefaultMode_from_RESET(void) {
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EMU_enter_DefaultMode_from_RESET();
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CMU_enter_DefaultMode_from_RESET();
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ADC0_enter_DefaultMode_from_RESET();
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USART0_enter_DefaultMode_from_RESET();
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USART1_enter_DefaultMode_from_RESET();
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LDMA_enter_DefaultMode_from_RESET();
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@ -127,6 +129,9 @@ extern void CMU_enter_DefaultMode_from_RESET(void) {
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/* Enable clock for HF peripherals */
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CMU_ClockEnable(cmuClock_HFPER, true);
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/* Enable clock for ADC0 */
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CMU_ClockEnable(cmuClock_ADC0, true);
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/* Enable clock for CRYOTIMER */
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CMU_ClockEnable(cmuClock_CRYOTIMER, true);
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|
|
@ -171,6 +176,16 @@ extern void CMU_enter_DefaultMode_from_RESET(void) {
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extern void ADC0_enter_DefaultMode_from_RESET(void) {
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// $[ADC0_Init]
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ADC_Init_TypeDef ADC0_init = ADC_INIT_DEFAULT;
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ADC0_init.ovsRateSel = adcOvsRateSel2;
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ADC0_init.warmUpMode = adcWarmupNormal;
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ADC0_init.timebase = ADC_TimebaseCalc(0);
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ADC0_init.prescale = ADC_PrescaleCalc(7000000, 0);
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ADC0_init.tailgate = 0;
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ADC0_init.em2ClockConfig = adcEm2Disabled;
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ADC_Init(ADC0, &ADC0_init);
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// [ADC0_Init]$
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// $[ADC0_InputConfiguration]
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|
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|
@ -8,12 +8,14 @@
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#include "util.h"
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#include "crypto.h"
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||||
#include "em_adc.h"
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#include "sha256.h"
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#include "uECC.h"
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#include "aes.h"
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#include "ctap.h"
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#include "log.h"
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#include MBEDTLS_CONFIG_FILE
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#include "sha256_alt.h"
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|
|
@ -26,8 +28,8 @@ const uint8_t attestation_key[];
|
|||
const uint16_t attestation_key_size;
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||||
|
||||
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||||
static SHA256_CTX sha256_ctx;
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||||
mbedtls_sha256_context embed_sha256_ctx;
|
||||
static mbedtls_sha256_context embed_sha256_ctx;
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||||
static mbedtls_ctr_drbg_context ctr_drbg;
|
||||
|
||||
static const struct uECC_Curve_t * _es256_curve = NULL;
|
||||
static const uint8_t * _signing_key = NULL;
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||||
|
|
@ -132,13 +134,51 @@ void crypto_sha256_hmac_final(uint8_t * key, uint32_t klen, uint8_t * hmac)
|
|||
crypto_sha256_final(hmac);
|
||||
}
|
||||
|
||||
mbedtls_ctr_drbg_context ctr_drbg;
|
||||
|
||||
|
||||
|
||||
uint8_t adc_rng(void)
|
||||
{
|
||||
int i;
|
||||
uint8_t random = 0;
|
||||
|
||||
/* Random number generation */
|
||||
for (i=0; i<3; i++)
|
||||
{
|
||||
ADC_Start(ADC0, adcStartSingle);
|
||||
while ((ADC0->IF & ADC_IF_SINGLE) == 0);
|
||||
random |= ((ADC_DataSingleGet(ADC0) & 0x07) << (i * 3));
|
||||
}
|
||||
|
||||
return random;
|
||||
}
|
||||
|
||||
// Generate @num bytes of random numbers to @dest
|
||||
// return 1 if success, error otherwise
|
||||
int ctap_generate_rng(uint8_t * dst, size_t num)
|
||||
{
|
||||
return mbedtls_ctr_drbg_random(&ctr_drbg,dst,num) == 0;
|
||||
}
|
||||
|
||||
int adc_entropy_func( void *data, unsigned char *output, size_t len )
|
||||
{
|
||||
while(len--)
|
||||
*output++ = adc_rng();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void crypto_ecc256_init()
|
||||
{
|
||||
uECC_set_rng((uECC_RNG_Function)ctap_generate_rng);
|
||||
_es256_curve = uECC_secp256r1();
|
||||
mbedtls_ctr_drbg_init(&ctr_drbg);
|
||||
|
||||
if ( mbedtls_ctr_drbg_seed(&ctr_drbg, adc_entropy_func, NULL,
|
||||
master_secret,32 ) != 0 ) {
|
||||
printf2(TAG_ERR, "mbedtls_ctr_drbg_seed failed\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -507,6 +547,7 @@ void crypto_aes256_encrypt(uint8_t * buf, int length)
|
|||
}
|
||||
|
||||
|
||||
|
||||
const uint8_t attestation_cert_der[] =
|
||||
"\x30\x82\x01\xfb\x30\x82\x01\xa1\xa0\x03\x02\x01\x02\x02\x01\x00\x30\x0a\x06\x08"
|
||||
"\x2a\x86\x48\xce\x3d\x04\x03\x02\x30\x2c\x31\x0b\x30\x09\x06\x03\x55\x04\x06\x13"
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
#include "em_chip.h"
|
||||
#include "em_gpio.h"
|
||||
#include "em_usart.h"
|
||||
#include "em_adc.h"
|
||||
#include "em_cmu.h"
|
||||
|
||||
#include "cbor.h"
|
||||
#include "log.h"
|
||||
|
|
@ -21,17 +23,6 @@
|
|||
#define RDY_PIN gpioPortC,10
|
||||
#define RW_PIN gpioPortD,11
|
||||
|
||||
// Generate @num bytes of random numbers to @dest
|
||||
// return 1 if success, error otherwise
|
||||
int ctap_generate_rng(uint8_t * dst, size_t num)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
*dst++ = rand();
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
uint32_t _c1 = 0, _c2 = 0;
|
||||
uint32_t ctap_atomic_count(int sel)
|
||||
|
|
@ -185,6 +176,29 @@ void GPIO_ODD_IRQHandler()
|
|||
|
||||
}
|
||||
|
||||
void init_adc()
|
||||
{
|
||||
/* Enable ADC Clock */
|
||||
CMU_ClockEnable(cmuClock_ADC0, true);
|
||||
ADC_Init_TypeDef init = ADC_INIT_DEFAULT;
|
||||
ADC_InitSingle_TypeDef singleInit = ADC_INITSINGLE_DEFAULT;
|
||||
|
||||
/* Initialize the ADC with the required values */
|
||||
init.timebase = ADC_TimebaseCalc(0);
|
||||
init.prescale = ADC_PrescaleCalc(7000000, 0);
|
||||
ADC_Init(ADC0, &init);
|
||||
|
||||
/* Initialize for single conversion specific to RNG */
|
||||
singleInit.reference = adcRefVEntropy;
|
||||
singleInit.diff = true;
|
||||
singleInit.posSel = adcPosSelVSS;
|
||||
singleInit.negSel = adcNegSelVSS;
|
||||
ADC_InitSingle(ADC0, &singleInit);
|
||||
|
||||
/* Set VINATT to maximum value and clear FIFO */
|
||||
ADC0->SINGLECTRLX |= _ADC_SINGLECTRLX_VINATT_MASK;
|
||||
ADC0->SINGLEFIFOCLEAR = ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR;
|
||||
}
|
||||
void device_init(void)
|
||||
{
|
||||
/* Chip errata */
|
||||
|
|
@ -218,12 +232,18 @@ void device_init(void)
|
|||
|
||||
printing_init();
|
||||
|
||||
init_adc();
|
||||
|
||||
CborEncoder test;
|
||||
uint8_t buf[20];
|
||||
uint8_t buf[64];
|
||||
cbor_encoder_init(&test, buf, 20, 0);
|
||||
|
||||
printf("Device init\r\n");
|
||||
int i=0;
|
||||
|
||||
|
||||
for (i = 0; i < sizeof(buf); i++)
|
||||
{
|
||||
buf[i] = adc_rng();
|
||||
}
|
||||
dump_hex(buf,sizeof(buf));
|
||||
}
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue