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1 405 Commity
3 Gałęzie
369 Tagi
192 MiB
Wykres commitów

222 Commity (dbbbfa12eed1f2a9c82589ce56a9b51e9ac113f4)

Autor SHA1 Wiadomość Data
f4exb dbbbfa12ee Changed USE_SIMD flag to USE_SSE 2016-11-06 02:08:38 +01:00
f4exb af0a0896d4 IntHalfBandFilterEO2: fixed (x,y) method 2016-11-06 01:19:39 +01:00
f4exb bc3dfb19cd IntHalfBandFilterEO2: use dual forward and backward buffers to avoid byte shuffling in SIMD instructions. Implemented in the up channelizer 2016-11-06 01:07:13 +01:00
f4exb de8640caae IntHalfBandFilterEO1: rename size attribute 2016-11-06 00:23:08 +01:00
f4exb 3410d289d1 Use even/odd FIR filter based half band decimators for the device decimators 2016-11-05 21:52:13 +01:00
f4exb f2a50c0c0f Use even/odd FIR filter half band interpolator only if SIMD is available 2016-11-04 22:47:09 +01:00
f4exb 9f74c82715 IntHalfBand FIR filter SSE optimizations 2016-11-04 01:12:39 +01:00
f4exb 2f02d9dd69 IntHalgBandFilterDB: changed some attributes name 2016-11-03 00:30:55 +01:00
f4exb 942f897978 Use the double buffer FIR filter with the front end decimators 2016-11-02 09:15:32 +01:00
f4exb 86c148ab10 DownChannelizer: use more efficient double buffer half band decvimator 2016-11-01 17:57:46 +01:00
f4exb 5d5593bda7 Tx ph.2: put the double buffered FIR interpolator and decimator in its own class 2016-11-01 15:02:50 +01:00
f4exb ded1d3c298 Place the halfband filter traits in their own class 2016-11-01 11:55:16 +01:00
f4exb bd4d224166 Tx ph.2: IntHalfBandFilter: use double buffer technique for interpolation. Use it with the UpChannelizer and increase order to 96 for better spur rejection. Moreover it is still more CPU efficient 2016-11-01 05:54:25 +01:00
f4exb 3173bc0b07 Tx ph.2: Interpolator polyphase filter: add possibility to specify the number of taps per phase 2016-10-31 23:40:46 +01:00
f4exb 004cbcb060 Tx ph.2: UpChannelizer: use order 64 filter as longer orders do not improve image rejection 2016-10-31 00:33:20 +01:00
f4exb 06b2c4930e IntHalBandFilter: added order 96 2016-10-30 23:04:54 +01:00
f4exb f5bbbb7cab Tx ph.2: UpChannelizer: allow any sample rate 2016-10-30 22:01:20 +01:00
f4exb 91315913b4 Tx ph.2: change UpChannelizer filter chain from std::list to std::vector 2016-10-30 18:22:33 +01:00
f4exb 31add4919d IntHalfbandFilter: corrected shift left factor for the Samples version of the FIR 2016-10-30 12:50:06 +01:00
f4exb fb2346aba8 Added original half band FIR coefficients as comments 2016-10-30 10:15:47 +01:00
f4exb 4a001350d3 Tx ph.2: Templatized IntHalfbandFilter and improved coefficients. Changed to order 80 for upsamplers and 48 for downsamplers 2016-10-29 17:01:02 +02:00
f4exb 4ab45f4768 Tx ph.2: Fixed half-band interpolators and set the order to 64 (for all) 2016-10-29 12:29:24 +02:00
f4exb e9f0bb0d45 Tx ph.2: UpChannelizer: interpolator (1) draft 2016-10-28 18:39:45 +02:00
f4exb 1f58b6ece7 DV serial: removed useless parameter 2016-10-28 09:09:19 +02:00
f4exb 0305605bbc DV Serial: fall back multi slot support 2016-10-28 08:37:27 +02:00
f4exb 4d273d8a13 Tx ph.2: use a specialized interpolator similar to the decimator derived from the ancient interpolator 2016-10-28 03:18:24 +02:00
f4exb 4618e007de Tx ph.2: restored ancient interpolator 2016-10-27 18:05:40 +02:00
f4exb 0fc6d95357 Tx ph.1: fixed read pointer management when getting new samples 2016-10-25 03:31:36 +02:00
f4exb ee55747c0b Tx ph.1: FileSink: set sample source FIFO size depending on sample rate 2016-10-25 02:34:29 +02:00
f4exb 5021d15162 Tx ph.1: Connect sample source FIFO read signal with forwarding samples to spectrum sink 2016-10-24 18:31:14 +02:00
f4exb 289c1a203f Tx ph.1: Sample source FIFO read with signal. Use a specific spectrum sink (vis) reference in Device sink engine for main spectrum rendering 2016-10-24 18:06:44 +02:00
f4exb 9f1b801d1a Tx ph.1: fixed AM modulator 2016-10-24 01:27:23 +02:00
f4exb 8f70840561 Tx ph.1: fixed sample source FIFO 2016-10-23 23:27:19 +02:00
f4exb 4e446b9c7a Tx ph.1: fixed source sink initialization 2016-10-23 14:14:32 +02:00
f4exb e42a717c69 Tx ph.1: Fixed sample rate and center frequency handling in File Sink 2016-10-23 10:38:44 +02:00
f4exb 119127fdab Tx ph.1: Fixes to file sink GUI and some debug messages 2016-10-23 02:22:00 +02:00
f4exb 4b02072fe4 Tx ph.1: add Tx tab (2). Fixed core dump 2016-10-22 05:07:48 +02:00
f4exb 9fff2b8477 Tx ph.1: new AM modulator plugin (3). Implemented actual modulation code. 2016-10-20 19:34:30 +02:00
f4exb 9f3fec7600 Tx ph.1: added device sinks list to DSP engine 2016-10-19 14:29:23 +02:00
f4exb 940cfbe94e DSPDeviceSourceEngine: stop threaded baseband sample sinks 2016-10-17 22:40:02 +02:00
f4exb 0f7ac00a71 Tx ph.1: Added the DSPDeviceSinkEngine class 2016-10-17 18:15:08 +02:00
f4exb b56c2d9a2c Tx ph.1: new classes (1) 2016-10-17 08:58:49 +02:00
f4exb 52b618469c Tx ph.1: refactored source sample FIFO. StarUML model: added Tx classes 2016-10-15 09:53:06 +02:00
f4exb 4709ba9e01 TX ph.1: Baseband sample sources and Device sample sinks (1) 2016-10-14 18:47:19 +02:00
f4exb 9303a63931 DV Serial: prepare multi slot (4) 2016-10-12 00:53:26 +02:00
f4exb 01c901a8fe DV Serial: prepare multi slot (3) 2016-10-12 00:19:44 +02:00
f4exb 413ba162c7 DV Serial: prepare multi slot (2) 2016-10-12 00:02:36 +02:00
f4exb 20c5ec3f76 DV Serial: removed useless parameter 2016-10-11 23:54:27 +02:00
f4exb 2caf76b746 DV Serial: prepare multi slot (1) 2016-10-11 23:51:18 +02:00
f4exb 18a8e7c903 DV Serial: implement FIFO slots 2016-10-11 22:52:45 +02:00