sdrangel

Autor	SHA1	Wiadomość	Data
f4exb	b04cc965e1	Fixed center interpolator by 64 missing some code. Fixes #884	2021-05-04 16:59:14 +02:00
f4exb	c3a8c14517	Interpolators: added invert I/Q parameter. Default false	2019-04-12 00:17:49 +02:00
f4exb	fc49bd2855	ixed incomplete copyright headers (3): sdrbase	2019-04-11 14:32:15 +02:00
f4exb	bfcfe8f87c	Implemented shifted interpolators by 64 and fixed some shifted interpolators inf/sup chains	2019-04-01 03:24:45 +02:00
f4exb	b3b7c54b78	Implemented shifted interpolation up to 32	2019-04-01 02:12:50 +02:00
f4exb	8e6f9d8d24	HackRF output: implementation of Fc position selection in the GUI	2019-03-31 23:09:50 +02:00
f4exb	ca24d8e9f6	Shifted interpolators by 2	2019-03-31 11:14:40 +02:00
f4exb	61a16eade9	Use always 16 bit DSP on Tx side	2018-01-22 10:46:57 +01:00
f4exb	bacc6659b0	24 bit DSP: use a different define for Tx chain so that it can stay on 16 bit DSP	2018-01-22 03:00:08 +01:00
f4exb	732561152b	24 bit DSP fix	2018-01-22 02:49:06 +01:00
f4exb	ad219d50cc	Implemented 24 bit internal DSP (with bugs ...)	2018-01-21 21:48:36 +01:00
f4exb	08ce7f423b	Templatize the accumulator type of integer half-band filters (non SIMD)	2018-01-21 19:39:51 +01:00
f4exb	3a3d8e3dcb	activated compiler warnings	2017-05-25 20:13:34 +02:00
f4exb	3479559859	Tx support: optimize final interpolator stages	2017-01-03 23:25:20 +01:00
f4exb	fa0afb6c92	Tx support: implemented final interpolation stage in FileSink plugin	2017-01-02 03:14:46 +01:00