Wykres commitów

23 Commity (613a5b0f1df14e76a41c47fd6e8e20354d7ce485)

Autor SHA1 Wiadomość Data
f4exb 6533df15f5 Sample source FIFO: limit read count to FIFO size 2019-11-17 03:16:50 +01:00
f4exb 3b74153ec6 SampleSourceFifo refactoring and Tx code reorganization 2019-11-15 01:05:32 +01:00
f4exb e6a929470f Renamed SampleSourceFifo to SampleSourceFifoDB to mark double buffered nature of FIFO 2019-11-02 11:03:07 +01:00
f4exb 7a1b727a36 MIMO: device engine Tx handling (1) 2019-10-19 05:07:40 +02:00
f4exb 68e4eaac68 PVS-Studio analys fixes: core package minor issues 2019-06-15 07:00:09 +02:00
f4exb ddde7a925f MIMO: copied test source as multiple input. Adaptation of main classes 2019-05-18 06:30:37 +02:00
f4exb ba4c8d7a68 Added the Local Source plugin 2019-05-10 13:20:30 +02:00
f4exb fc49bd2855 ixed incomplete copyright headers (3): sdrbase 2019-04-11 14:32:15 +02:00
f4exb f01b90094b PVS-Studio static analysis corrections (1) issue #137 2018-02-21 18:54:59 +01:00
f4exb 9a2ae892ed Sample source FIFO: moved emit data write at top of method so that samples can be written with no delay 2018-01-02 01:04:04 +01:00
f4exb 09856b5941 Sample source FIFO: write ahead the exact same amount of samples that were read. This smoothes out the process and avoids hickups 2017-01-09 02:13:27 +01:00
f4exb 5598265e66 Multiple modulators support: works with two modulators 2016-12-26 12:11:51 +01:00
f4exb e05822ba02 Implement own FIFO in BasebandSampleSource. SampleSourceFIFO: remove useless chunk size completely and set initial fill to only half the FIFO size 2016-12-23 14:29:42 +01:00
f4exb 1afd8df5f9 Modulators: changed single Tx channel samples feed handling 2016-12-22 23:39:06 +01:00
f4exb 441c2c1817 Send number of samples to write in the writeData signal. Ask for half the buffer size when more than half of it is consumed 2016-12-21 02:24:49 +01:00
f4exb 0fc6d95357 Tx ph.1: fixed read pointer management when getting new samples 2016-10-25 03:31:36 +02:00
f4exb ee55747c0b Tx ph.1: FileSink: set sample source FIFO size depending on sample rate 2016-10-25 02:34:29 +02:00
f4exb 289c1a203f Tx ph.1: Sample source FIFO read with signal. Use a specific spectrum sink (vis) reference in Device sink engine for main spectrum rendering 2016-10-24 18:06:44 +02:00
f4exb 8f70840561 Tx ph.1: fixed sample source FIFO 2016-10-23 23:27:19 +02:00
f4exb 4e446b9c7a Tx ph.1: fixed source sink initialization 2016-10-23 14:14:32 +02:00
f4exb 4b02072fe4 Tx ph.1: add Tx tab (2). Fixed core dump 2016-10-22 05:07:48 +02:00
f4exb 52b618469c Tx ph.1: refactored source sample FIFO. StarUML model: added Tx classes 2016-10-15 09:53:06 +02:00
f4exb 6e82cb37b8 Tx support: added a sample source FIFO class 2016-10-10 01:13:12 +02:00