sdrangel

Autor	SHA1	Wiadomość	Data
f4exb	053e4a31cd	Add label to SampleSinkFifo to mention controlling component in error messages	2022-03-18 21:53:53 +01:00
f4exb	09599e145e	Added signals to SampleSinkFifo including samples timings. Implements #1143 and part of #1139	2022-03-15 22:21:06 +01:00
f4exb	e3910c0aa1	Revision of mutex locks in FIFOs	2021-04-26 19:33:02 +02:00
f4exb	8c9f5ff14c	SampleSinkFIFO: read/write return immediately if size is zero. Fixes #868	2021-04-25 11:06:21 +02:00
f4exb	5b83b2a4a8	Rx plugins: refactoring of classes (1)	2019-11-23 07:40:36 +01:00
f4exb	aeaba8b378	Reformat sample sink FIFO code	2019-10-09 07:39:52 +02:00
f4exb	ddde7a925f	MIMO: copied test source as multiple input. Adaptation of main classes	2019-05-18 06:30:37 +02:00
f4exb	fc49bd2855	ixed incomplete copyright headers (3): sdrbase	2019-04-11 14:32:15 +02:00
f4exb	3d77c9af9b	SDRDaemon input: adaptation for 24 bit Rx DSP	2018-01-24 08:49:18 +01:00
f4exb	5168fbf416	RxTx semantic move: updated debug message and displayed class names	2016-10-08 10:35:07 +02:00
f4exb	36aeaa3ea5	RxTx semantic move: renamed SampleFifo to SampleSinkFifo	2016-10-06 19:18:02 +02:00