kopia lustrzana https://gitlab.com/sane-project/backends
384 wiersze
10 KiB
C++
384 wiersze
10 KiB
C++
/* sane - Scanner Access Now Easy.
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Copyright (C) 2010-2016 Stéphane Voltz <stef.dev@free.fr>
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This file is part of the SANE package.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA.
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As a special exception, the authors of SANE give permission for
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additional uses of the libraries contained in this release of SANE.
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The exception is that, if you link a SANE library with other files
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to produce an executable, this does not by itself cause the
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resulting executable to be covered by the GNU General Public
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License. Your use of that executable is in no way restricted on
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account of linking the SANE library code into it.
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This exception does not, however, invalidate any other reasons why
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the executable file might be covered by the GNU General Public
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License.
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If you submit changes to SANE to the maintainers to be included in
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a subsequent release, you agree by submitting the changes that
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those changes may be distributed with this exception intact.
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If you write modifications of your own for SANE, it is your choice
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whether to permit this exception to apply to your modifications.
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If you do not wish that, delete this exception notice.
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*/
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#include "genesys.h"
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#define REG01 0x01
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#define REG01_CISSET 0x80
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#define REG01_DOGENB 0x40
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#define REG01_DVDSET 0x20
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#define REG01_STAGGER 0x10
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#define REG01_COMPENB 0x08
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#define REG01_TRUEGRAY 0x04
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#define REG01_SHDAREA 0x02
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#define REG01_SCAN 0x01
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#define REG02 0x02
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#define REG02_NOTHOME 0x80
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#define REG02_ACDCDIS 0x40
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#define REG02_AGOHOME 0x20
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#define REG02_MTRPWR 0x10
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#define REG02_FASTFED 0x08
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#define REG02_MTRREV 0x04
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#define REG02_HOMENEG 0x02
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#define REG02_LONGCURV 0x01
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#define REG03 0x03
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#define REG03_LAMPDOG 0x80
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#define REG03_AVEENB 0x40
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#define REG03_XPASEL 0x20
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#define REG03_LAMPPWR 0x10
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#define REG03_LAMPTIM 0x0f
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#define REG04 0x04
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#define REG04_LINEART 0x80
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#define REG04_BITSET 0x40
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#define REG04_FILTER 0x30
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#define REG04_AFEMOD 0x07
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#define REG05 0x05
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#define REG05_DPIHW 0xc0
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#define REG05_DPIHW_600 0x00
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#define REG05_DPIHW_1200 0x40
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#define REG05_DPIHW_2400 0x80
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#define REG05_DPIHW_4800 0xc0
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#define REG05_MTLLAMP 0x30
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#define REG05_GMMENB 0x08
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#define REG05_ENB20M 0x04
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#define REG05_MTLBASE 0x03
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#define REG06 0x06
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#define REG06_SCANMOD 0xe0
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#define REG06S_SCANMOD 5
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#define REG06_PWRBIT 0x10
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#define REG06_GAIN4 0x08
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#define REG06_OPTEST 0x07
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#define REG07_LAMPSIM 0x80
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#define REG08_DRAM2X 0x80
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#define REG08_MPENB 0x20
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#define REG08_CIS_LINE 0x10
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#define REG08_IR2_ENB 0x08
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#define REG08_IR1_ENB 0x04
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#define REG08_ENB24M 0x01
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#define REG09_MCNTSET 0xc0
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#define REG09_EVEN1ST 0x20
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#define REG09_BLINE1ST 0x10
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#define REG09_BACKSCAN 0x08
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#define REG09_OUTINV 0x04
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#define REG09_SHORTTG 0x02
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#define REG09S_MCNTSET 6
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#define REG09S_CLKSET 4
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#define REG0A 0x0a
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#define REG0A_SIFSEL 0xc0
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#define REG0AS_SIFSEL 6
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#define REG0A_SHEETFED 0x20
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#define REG0A_LPWMEN 0x10
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#define REG0B 0x0b
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#define REG0B_DRAMSEL 0x07
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#define REG0B_16M 0x01
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#define REG0B_64M 0x02
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#define REG0B_128M 0x03
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#define REG0B_256M 0x04
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#define REG0B_512M 0x05
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#define REG0B_1G 0x06
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#define REG0B_ENBDRAM 0x08
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#define REG0B_RFHDIS 0x10
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#define REG0B_CLKSET 0xe0
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#define REG0B_24MHZ 0x00
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#define REG0B_30MHZ 0x20
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#define REG0B_40MHZ 0x40
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#define REG0B_48MHZ 0x60
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#define REG0B_60MHZ 0x80
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#define REG0D 0x0d
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#define REG0D_MTRP_RDY 0x80
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#define REG0D_FULLSTP 0x10
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#define REG0D_CLRMCNT 0x04
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#define REG0D_CLRDOCJM 0x02
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#define REG0D_CLRLNCNT 0x01
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#define REG0F 0x0f
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#define REG16_CTRLHI 0x80
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#define REG16_TOSHIBA 0x40
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#define REG16_TGINV 0x20
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#define REG16_CK1INV 0x10
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#define REG16_CK2INV 0x08
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#define REG16_CTRLINV 0x04
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#define REG16_CKDIS 0x02
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#define REG16_CTRLDIS 0x01
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#define REG17_TGMODE 0xc0
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#define REG17_SNRSYN 0x0f
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#define REG18 0x18
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#define REG18_CNSET 0x80
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#define REG18_DCKSEL 0x60
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#define REG18_CKTOGGLE 0x10
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#define REG18_CKDELAY 0x0c
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#define REG18_CKSEL 0x03
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#define REG1A_SW2SET 0x80
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#define REG1A_SW1SET 0x40
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#define REG1A_MANUAL3 0x02
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#define REG1A_MANUAL1 0x01
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#define REG1A_CK4INV 0x08
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#define REG1A_CK3INV 0x04
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#define REG1A_LINECLP 0x02
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#define REG1C_TBTIME 0x07
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#define REG1D 0x1d
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#define REG1D_CK4LOW 0x80
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#define REG1D_CK3LOW 0x40
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#define REG1D_CK1LOW 0x20
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#define REG1D_LINESEL 0x1f
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#define REG1DS_LINESEL 0
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#define REG1E 0x1e
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#define REG1E_WDTIME 0xf0
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#define REG1ES_WDTIME 4
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#define REG1E_WDTIME 0xf0
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#define REG30 0x30
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#define REG31 0x31
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#define REG32 0x32
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#define REG32_GPIO16 0x80
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#define REG32_GPIO15 0x40
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#define REG32_GPIO14 0x20
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#define REG32_GPIO13 0x10
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#define REG32_GPIO12 0x08
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#define REG32_GPIO11 0x04
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#define REG32_GPIO10 0x02
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#define REG32_GPIO9 0x01
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#define REG33 0x33
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#define REG34 0x34
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#define REG35 0x35
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#define REG36 0x36
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#define REG37 0x37
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#define REG38 0x38
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#define REG39 0x39
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#define REG60 0x60
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#define REG60_LED4TG 0x80
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#define REG60_YENB 0x40
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#define REG60_YBIT 0x20
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#define REG60_ACYNCNRLC 0x10
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#define REG60_ENOFFSET 0x08
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#define REG60_LEDADD 0x04
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#define REG60_CK4ADC 0x02
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#define REG60_AUTOCONF 0x01
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#define REG80 0x80
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#define REG81 0x81
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#define REGA0 0xa0
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#define REGA0_FSTPSEL 0x28
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#define REGA0S_FSTPSEL 3
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#define REGA0_STEPSEL 0x03
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#define REGA0S_STEPSEL 0
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#define REGA1 0xa1
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#define REGA2 0xa2
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#define REGA3 0xa3
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#define REGA4 0xa4
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#define REGA5 0xa5
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#define REGA6 0xa6
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#define REGA7 0xa7
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#define REGA8 0xa8
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#define REGA9 0xa9
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#define REGAA 0xaa
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#define REGAB 0xab
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#define REGAC 0xac
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#define REGAD 0xad
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#define REGAE 0xae
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#define REGAF 0xaf
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#define REGB0 0xb0
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#define REGB1 0xb1
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#define REGB2 0xb2
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#define REGB2_Z1MOD 0x1f
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#define REGB3 0xb3
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#define REGB3_Z1MOD 0xff
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#define REGB4 0xb4
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#define REGB4_Z1MOD 0xff
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#define REGB5 0xb5
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#define REGB5_Z2MOD 0x1f
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#define REGB6 0xb6
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#define REGB6_Z2MOD 0xff
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#define REGB7 0xb7
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#define REGB7_Z2MOD 0xff
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#define REG100 0x100
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#define REG100_DOCSNR 0x80
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#define REG100_ADFSNR 0x40
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#define REG100_COVERSNR 0x20
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#define REG100_CHKVER 0x10
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#define REG100_DOCJAM 0x08
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#define REG100_HISPDFLG 0x04
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#define REG100_MOTMFLG 0x02
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#define REG100_DATAENB 0x01
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#define REG114 0x114
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#define REG115 0x115
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#define REG_LINCNT 0x25
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#define REG_MAXWD 0x28
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#define REG_DPISET 0x2c
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#define REG_FEEDL 0x3d
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#define REG_CK1MAP 0x74
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#define REG_CK3MAP 0x77
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#define REG_CK4MAP 0x7a
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#define REG_LPERIOD 0x7d
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#define REG_DUMMY 0x80
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#define REG_STRPIXEL 0x82
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#define REG_ENDPIXEL 0x85
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#define REG_EXPDMY 0x88
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#define REG_EXPR 0x8a
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#define REG_EXPG 0x8d
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#define REG_EXPB 0x90
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#define REG_SEGCNT 0x93
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#define REG_TG0CNT 0x96
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#define REG_SCANFED 0xa2
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#define REG_STEPNO 0xa4
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#define REG_FWDSTEP 0xa6
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#define REG_BWDSTEP 0xa8
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#define REG_FASTNO 0xaa
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#define REG_FSHDEC 0xac
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#define REG_FMOVNO 0xae
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#define REG_FMOVDEC 0xb0
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#define REG_Z1MOD 0xb2
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#define REG_Z2MOD 0xb5
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#define REG_TRUER 0x110
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#define REG_TRUEG 0x111
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#define REG_TRUEB 0x112
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#define SETREG(adr,val) { dev->reg.init_reg(adr, val); }
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typedef struct
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{
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uint8_t r31;
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uint8_t r32;
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uint8_t r33;
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uint8_t r34;
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uint8_t r35;
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uint8_t r36;
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uint8_t r38;
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} Gpio_layout;
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/** @brief gpio layout
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* describes initial gpio settings for a given model
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* registers 0x31 to 0x38
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*/
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static Gpio_layout gpios[]={
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/* LiDE 110 */
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{ /* 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x38 */
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0x9f, 0x59, 0x01, 0x80, 0x5f, 0x01, 0x00
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},
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/* LiDE 210 */
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{
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0x9f, 0x59, 0x01, 0x80, 0x5f, 0x01, 0x00
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},
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/* LiDE 120 */
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{
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0x9f, 0x53, 0x01, 0x80, 0x5f, 0x01, 0x00
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},
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};
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typedef struct
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{
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uint8_t rd0;
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uint8_t rd1;
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uint8_t rd2;
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uint8_t re0;
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uint8_t re1;
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uint8_t re2;
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uint8_t re3;
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uint8_t re4;
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uint8_t re5;
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uint8_t re6;
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uint8_t re7;
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} Memory_layout;
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static Memory_layout layouts[]={
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/* LIDE 110, 120 */
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{ /* 0xd0 0xd1 0xd2 */
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0x0a, 0x15, 0x20,
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/* 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 */
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0x00, 0xac, 0x08, 0x55, 0x08, 0x56, 0x0f, 0xff
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},
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/* LIDE 210, 220 */
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{
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0x0a, 0x1f, 0x34,
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0x01, 0x24, 0x08, 0x91, 0x08, 0x92, 0x0f, 0xff
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}
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};
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#define MOVE_DPI 200
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#define MOVE_EXPOSURE 2304
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static void gl124_start_action(Genesys_Device* dev);
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static void gl124_begin_scan(Genesys_Device* dev, const Genesys_Sensor& sensor,
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Genesys_Register_Set* reg, SANE_Bool start_motor);
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static void gl124_end_scan(Genesys_Device* dev, Genesys_Register_Set* reg, SANE_Bool check_stop);
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static void gl124_slow_back_home(Genesys_Device* dev, SANE_Bool wait_until_home);
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static void gl124_init(Genesys_Device* dev);
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static void gl124_send_shading_data(Genesys_Device* dev, const Genesys_Sensor& sensor,
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uint8_t* data, int size);
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static void gl124_feed(Genesys_Device* dev, unsigned int steps, int reverse);
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static void gl124_stop_action(Genesys_Device* dev);
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static void gl124_send_slope_table(Genesys_Device* dev, int table_nr,
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const std::vector<uint16_t>& slope_table, int steps);
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