kopia lustrzana https://gitlab.com/sane-project/backends
492 wiersze
10 KiB
C
492 wiersze
10 KiB
C
/* sane - Scanner Access Now Easy.
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Copyright (C) 2010 Stéphane Voltz <stef.dev@free.fr>
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This file is part of the SANE package.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA.
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As a special exception, the authors of SANE give permission for
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additional uses of the libraries contained in this release of SANE.
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The exception is that, if you link a SANE library with other files
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to produce an executable, this does not by itself cause the
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resulting executable to be covered by the GNU General Public
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License. Your use of that executable is in no way restricted on
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account of linking the SANE library code into it.
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This exception does not, however, invalidate any other reasons why
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the executable file might be covered by the GNU General Public
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License.
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If you submit changes to SANE to the maintainers to be included in
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a subsequent release, you agree by submitting the changes that
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those changes may be distributed with this exception intact.
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If you write modifications of your own for SANE, it is your choice
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whether to permit this exception to apply to your modifications.
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If you do not wish that, delete this exception notice.
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*/
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#include "../include/sane/config.h"
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#include <errno.h>
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#include <string.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <math.h>
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#include "../include/sane/sane.h"
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#include "../include/sane/sanei.h"
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#include "../include/sane/saneopts.h"
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#undef BACKEND_NAME
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#define BACKEND_NAME genesys_gl847
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#include "../include/sane/sanei_backend.h"
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#include "../include/sane/sanei_config.h"
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#include "../include/sane/sanei_usb.h"
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#include "../include/_stdint.h"
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#include "genesys.h"
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#define DBGSTART DBG (DBG_proc, "%s start\n", __FUNCTION__);
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#define DBGCOMPLETED DBG (DBG_proc, "%s completed\n", __FUNCTION__);
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#define REG01 0x01
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#define REG01_CISSET 0x80
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#define REG01_DOGENB 0x40
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#define REG01_DVDSET 0x20
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#define REG01_STAGGER 0x10
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#define REG01_COMPENB 0x08
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#define REG01_TRUEGRAY 0x04
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#define REG01_SHDAREA 0x02
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#define REG01_SCAN 0x01
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#define REG02 0x02
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#define REG02_NOTHOME 0x80
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#define REG02_ACDCDIS 0x40
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#define REG02_AGOHOME 0x20
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#define REG02_MTRPWR 0x10
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#define REG02_FASTFED 0x08
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#define REG02_MTRREV 0x04
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#define REG02_HOMENEG 0x02
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#define REG02_LONGCURV 0x01
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#define REG03 0x03
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#define REG03_LAMPDOG 0x80
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#define REG03_AVEENB 0x40
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#define REG03_XPASEL 0x20
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#define REG03_LAMPPWR 0x10
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#define REG03_LAMPTIM 0x0f
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#define REG04 0x04
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#define REG04_LINEART 0x80
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#define REG04_BITSET 0x40
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#define REG04_AFEMOD 0x30
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#define REG04_FILTER 0x0c
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#define REG04_FESET 0x03
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#define REG04S_AFEMOD 4
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#define REG05 0x05
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#define REG05_DPIHW 0xc0
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#define REG05_DPIHW_600 0x00
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#define REG05_DPIHW_1200 0x40
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#define REG05_DPIHW_2400 0x80
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#define REG05_DPIHW_4800 0xc0
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#define REG05_MTLLAMP 0x30
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#define REG05_GMMENB 0x08
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#define REG05_MTLBASE 0x03
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#define REG06_SCANMOD 0xe0
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#define REG06S_SCANMOD 5
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#define REG06_PWRBIT 0x10
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#define REG06_GAIN4 0x08
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#define REG06_OPTEST 0x07
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#define REG07_LAMPSIM 0x80
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#define REG08_DRAM2X 0x80
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#define REG08_MPENB 0x20
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#define REG08_CIS_LINE 0x10
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#define REG08_IR1ENB 0x08
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#define REG08_IR2ENB 0x04
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#define REG08_ENB24M 0x01
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#define REG09_MCNTSET 0xc0
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#define REG09_EVEN1ST 0x20
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#define REG09_BLINE1ST 0x10
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#define REG09_BACKSCAN 0x08
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#define REG09_ENHANCE 0x04
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#define REG09_SHORTTG 0x02
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#define REG09_NWAIT 0x01
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#define REG09S_MCNTSET 6
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#define REG09S_CLKSET 4
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#define REG0A_LPWMEN 0x10
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#define REG0B 0x0b
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#define REG0B_DRAMSEL 0x07
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#define REG0B_ENBDRAM 0x08
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#define REG0B_ENBDRAM 0x08
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#define REG0B_RFHDIS 0x10
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#define REG0B_CLKSET 0xe0
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#define REG0B_24MHZ 0x00
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#define REG0B_30MHZ 0x20
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#define REG0B_40MHZ 0x40
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#define REG0B_48MHZ 0x60
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#define REG0B_60MHZ 0x80
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#define REG0D 0x0d
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#define REG0D_FULLSTP 0x10
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#define REG0D_SEND 0x80
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#define REG0D_CLRMCNT 0x04
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#define REG0D_CLRDOCJM 0x02
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#define REG0D_CLRLNCNT 0x01
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#define REG0F 0x0f
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#define REG16_CTRLHI 0x80
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#define REG16_TOSHIBA 0x40
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#define REG16_TGINV 0x20
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#define REG16_CK1INV 0x10
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#define REG16_CK2INV 0x08
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#define REG16_CTRLINV 0x04
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#define REG16_CKDIS 0x02
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#define REG16_CTRLDIS 0x01
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#define REG17_TGMODE 0xc0
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#define REG17_TGMODE_NO_DUMMY 0x00
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#define REG17_TGMODE_REF 0x40
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#define REG17_TGMODE_XPA 0x80
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#define REG17_TGW 0x3f
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#define REG17S_TGW 0
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#define REG18_CNSET 0x80
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#define REG18_DCKSEL 0x60
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#define REG18_CKTOGGLE 0x10
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#define REG18_CKDELAY 0x0c
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#define REG18_CKSEL 0x03
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#define REG1A_SW2SET 0x80
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#define REG1A_SW1SET 0x40
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#define REG1A_MANUAL3 0x02
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#define REG1A_MANUAL1 0x01
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#define REG1A_CK4INV 0x08
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#define REG1A_CK3INV 0x04
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#define REG1A_LINECLP 0x02
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#define REG1C_TGTIME 0x07
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#define REG1D_CK4LOW 0x80
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#define REG1D_CK3LOW 0x40
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#define REG1D_CK1LOW 0x20
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#define REG1D_TGSHLD 0x1f
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#define REG1DS_TGSHLD 0
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#define REG1E_WDTIME 0xf0
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#define REG1ES_WDTIME 4
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#define REG1E_LINESEL 0x0f
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#define REG1ES_LINESEL 0
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#define REG40 0x40
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#define REG40_CHKVER 0x10
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#define REG40_HISPDFLG 0x04
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#define REG40_MOTMFLG 0x02
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#define REG40_DATAENB 0x01
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#define REG41_PWRBIT 0x80
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#define REG41_BUFEMPTY 0x40
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#define REG41_FEEDFSH 0x20
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#define REG41_SCANFSH 0x10
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#define REG41_HOMESNR 0x08
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#define REG41_LAMPSTS 0x04
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#define REG41_FEBUSY 0x02
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#define REG41_MOTORENB 0x01
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#define REG58_VSMP 0xf8
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#define REG58S_VSMP 3
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#define REG58_VSMPW 0x07
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#define REG58S_VSMPW 0
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#define REG59_BSMP 0xf8
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#define REG59S_BSMP 3
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#define REG59_BSMPW 0x07
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#define REG59S_BSMPW 0
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#define REG5A_ADCLKINV 0x80
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#define REG5A_RLCSEL 0x40
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#define REG5A_CDSREF 0x30
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#define REG5AS_CDSREF 4
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#define REG5A_RLC 0x0f
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#define REG5AS_RLC 0
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#define REG5E_DECSEL 0xe0
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#define REG5ES_DECSEL 5
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#define REG5E_STOPTIM 0x1f
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#define REG5ES_STOPTIM 0
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#define REG60 0x60
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#define REG60_Z1MOD 0x1f
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#define REG61 0x61
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#define REG61_Z1MOD 0xff
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#define REG62 0x62
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#define REG62_Z1MOD 0xff
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#define REG63 0x63
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#define REG63_Z2MOD 0x1f
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#define REG64 0x64
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#define REG64_Z2MOD 0xff
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#define REG65 0x65
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#define REG65_Z2MOD 0xff
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#define REG60S_STEPSEL 5
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#define REG60_STEPSEL 0xe0
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#define REG60_FULLSTEP 0x00
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#define REG60_HALFSTEP 0x20
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#define REG60_EIGHTHSTEP 0x60
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#define REG60_16THSTEP 0x80
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#define REG63S_FSTPSEL 5
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#define REG63_FSTPSEL 0xe0
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#define REG63_FULLSTEP 0x00
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#define REG63_HALFSTEP 0x20
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#define REG63_EIGHTHSTEP 0x60
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#define REG63_16THSTEP 0x80
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#define REG67 0x67
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#define REG67_MTRPWM 0x80
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#define REG68 0x68
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#define REG68_FASTPWM 0x80
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#define REG6B 0x6b
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#define REG6B_MULTFILM 0x80
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#define REG6B_GPOM13 0x40
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#define REG6B_GPOM12 0x20
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#define REG6B_GPOM11 0x10
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#define REG6B_GPO18 0x02
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#define REG6B_GPO17 0x01
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#define REG6C 0x6c
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#define REG6C_GPIO16 0x80
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#define REG6C_GPIO15 0x40
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#define REG6C_GPIO14 0x20
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#define REG6C_GPIO13 0x10
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#define REG6C_GPIO12 0x08
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#define REG6C_GPIO11 0x04
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#define REG6C_GPIO10 0x02
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#define REG6C_GPIO9 0x01
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#define REG6C_GPIOH 0xff
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#define REG6C_GPIOL 0xff
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#define REG6D 0x6d
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#define REG6E 0x6e
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#define REG6F 0x6f
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#define REG87_LEDADD 0x04
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#define REGA6 0xa6
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#define REGA7 0xa7
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#define REGA9 0xa9
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#define SCAN_FLAG_SINGLE_LINE 0x01
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#define SCAN_FLAG_DISABLE_SHADING 0x02
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#define SCAN_FLAG_DISABLE_GAMMA 0x04
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#define SCAN_FLAG_DISABLE_BUFFER_FULL_MOVE 0x08
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#define SCAN_FLAG_IGNORE_LINE_DISTANCE 0x10
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#define SCAN_FLAG_USE_OPTICAL_RES 0x20
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#define SCAN_FLAG_DISABLE_LAMP 0x40
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#define SCAN_FLAG_DYNAMIC_LINEART 0x80
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/**
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* writable scanner registers */
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enum
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{
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reg_0x01 = 0,
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reg_0x02,
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reg_0x03,
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reg_0x04,
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reg_0x05,
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reg_0x06,
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reg_0x08,
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reg_0x09,
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reg_0x0a,
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reg_0x0b,
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reg_0x0c,
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reg_0x0d,
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reg_0x0e,
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reg_0x0f,
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reg_0x10,
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reg_0x11,
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reg_0x12,
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reg_0x13,
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reg_0x14,
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reg_0x15,
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reg_0x16,
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reg_0x17,
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reg_0x18,
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reg_0x19,
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reg_0x1a,
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reg_0x1b,
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reg_0x1c,
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reg_0x1d,
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reg_0x1e,
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reg_0x1f,
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reg_0x20,
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reg_0x21,
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reg_0x22,
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reg_0x23,
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reg_0x24,
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reg_0x25,
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reg_0x26,
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reg_0x27,
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reg_0x2c,
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reg_0x2d,
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reg_0x2e,
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reg_0x2f,
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reg_0x30,
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reg_0x31,
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reg_0x32,
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reg_0x33,
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reg_0x34,
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reg_0x35,
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reg_0x36,
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reg_0x37,
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reg_0x38,
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reg_0x39,
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reg_0x3a,
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reg_0x3b,
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reg_0x3d,
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reg_0x3e,
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reg_0x3f,
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reg_0x51,
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reg_0x52,
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reg_0x53,
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reg_0x54,
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reg_0x55,
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reg_0x56,
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reg_0x57,
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reg_0x58,
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reg_0x59,
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reg_0x5a,
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reg_0x5e,
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reg_0x5f,
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reg_0x60,
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reg_0x61,
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reg_0x62,
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reg_0x63,
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reg_0x64,
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reg_0x65,
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reg_0x67,
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reg_0x68,
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reg_0x69,
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reg_0x6a,
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reg_0x6b,
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reg_0x6c,
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reg_0x6d,
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reg_0x6e,
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reg_0x6f,
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reg_0x74,
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reg_0x75,
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reg_0x76,
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reg_0x77,
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reg_0x78,
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reg_0x79,
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reg_0x7a,
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reg_0x7b,
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reg_0x7c,
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reg_0x7d,
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reg_0x87,
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reg_0x9d,
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reg_0xa2,
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reg_0xa6,
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reg_0xa7,
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reg_0xa8,
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reg_0xa9,
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reg_0xbd,
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reg_0xbe,
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reg_0xc5,
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reg_0xc6,
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reg_0xc7,
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reg_0xc8,
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reg_0xc9,
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reg_0xca,
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reg_0xd0,
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reg_0xd1,
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reg_0xd2,
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reg_0xe0,
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reg_0xe1,
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reg_0xe2,
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reg_0xe3,
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reg_0xe4,
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reg_0xe5,
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reg_0xe6,
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reg_0xe7,
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reg_0xe8,
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reg_0xe9,
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reg_0xea,
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reg_0xeb,
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reg_0xec,
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reg_0xed,
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reg_0xee,
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reg_0xef,
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reg_0xf0,
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reg_0xf1,
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reg_0xf2,
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reg_0xf3,
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reg_0xf4,
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reg_0xf5,
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reg_0xf6,
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reg_0xf7,
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reg_0xf8,
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reg_0xfe,
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GENESYS_GL847_MAX_REGS
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};
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#define SETREG(adr,val) {dev->reg[reg_##adr].address=adr;dev->reg[reg_##adr].value=val;}
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typedef struct
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{
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uint8_t rd0;
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uint8_t rd1;
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uint8_t rd2;
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uint8_t re0;
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uint8_t re1;
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uint8_t re2;
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uint8_t re3;
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uint8_t re4;
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uint8_t re5;
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uint8_t re6;
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uint8_t re7;
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} Memory_layout;
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static Memory_layout layouts[]={
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/* LIDE 100 */
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{
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0x0a, 0x15, 0x20,
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0x00, 0xac, 0x02, 0x55, 0x02, 0x56, 0x03, 0xff
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},
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/* LIDE 200 */
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{
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0x0a, 0x1f, 0x34,
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0x01, 0x24, 0x02, 0x91, 0x02, 0x92, 0x03, 0xff
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}
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};
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