kopia lustrzana https://gitlab.com/sane-project/backends
genesys: Don't overwrite RAM settings
rodzic
ea5047466c
commit
ee2e026f2a
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@ -1204,12 +1204,6 @@ void CommandSetGl846::asic_boot(Genesys_Device* dev, bool cold) const
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// Write initial registers
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dev->interface->write_registers(dev->reg);
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/* Enable DRAM by setting a rising edge on bit 3 of reg 0x0b */
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val = dev->reg.find_reg(0x0b).value & REG_0x0B_DRAMSEL;
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val = (val | REG_0x0B_ENBDRAM);
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dev->interface->write_register(REG_0x0B, val);
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dev->reg.find_reg(0x0b).value = val;
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/* CIS_LINE */
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if (dev->model->is_cis)
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{
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