kopia lustrzana https://gitlab.com/sane-project/backends
about to scan: slow back home to tackle
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3dba8c1d66
commit
530ebc8d3e
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@ -699,7 +699,7 @@ Genesys_Register_Set *
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sanei_genesys_get_address (Genesys_Register_Set * regs, SANE_Byte addr)
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{
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int i;
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for (i = 0; i < GENESYS_MAX_REGS && regs[i].address; i++)
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for (i = 0; i < GENESYS_MAX_REGS; i++)
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{
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if (regs[i].address == addr)
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return ®s[i];
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@ -887,8 +887,9 @@ static Genesys_Model canon_lide_200_model = {
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GENESYS_GL847,
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NULL,
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{1200, 600, 300, 150, 75, 50, 0}, /* possible x-resolutions */
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{2400, 1200, 600, 300, 150, 75, 50, 0}, /* possible y-resolutions */
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/* XXX STEF XXX add 75 dpi mode at least, look at 2400 for motor */
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{1200, 600, 300, 150, 0}, /* possible x-resolutions */
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{1200, 600, 300, 150, 0}, /* possible y-resolutions */
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{16, 8, 0}, /* possible depths in gray mode */
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{16, 8, 0}, /* possible depths in color mode */
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@ -923,6 +924,7 @@ static Genesys_Model canon_lide_200_model = {
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GPO_CANONLIDE200,
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MOTOR_CANONLIDE200,
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GENESYS_FLAG_LAZY_INIT /* Which flags are needed for this scanner? */
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| GENESYS_FLAG_NO_CALIBRATION
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| GENESYS_FLAG_SKIP_WARMUP
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| GENESYS_FLAG_OFFSET_CALIBRATION
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| GENESYS_FLAG_DARK_WHITE_CALIBRATION
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File diff suppressed because one or more lines are too long
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@ -65,8 +65,9 @@
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#define REG01_CISSET 0x80
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#define REG01_DOGENB 0x40
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#define REG01_DVDSET 0x20
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#define REG01_M16DRAM 0x08
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#define REG01_DRAMSEL 0x04
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#define REG01_STAGGER 0x10
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#define REG01_COMPENB 0x08
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#define REG01_TRUEGRAY 0x04
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#define REG01_SHDAREA 0x02
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#define REG01_SCAN 0x01
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@ -79,6 +80,7 @@
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#define REG02_HOMENEG 0x02
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#define REG02_LONGCURV 0x01
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#define REG03 0x03
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#define REG03_LAMPDOG 0x80
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#define REG03_AVEENB 0x40
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#define REG03_XPASEL 0x20
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@ -107,10 +109,7 @@
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#define REG06_GAIN4 0x08
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#define REG06_OPTEST 0x07
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#define REG07_SRAMSEL 0x08
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#define REG07_FASTDMA 0x04
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#define REG07_DMASEL 0x02
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#define REG07_DMARDWR 0x01
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#define REG07_LAMPSIM 0x80
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#define REG08_DRAM2X 0x80
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#define REG08_MPENB 0x20
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@ -120,7 +119,8 @@
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#define REG08_ENB24M 0x01
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#define REG09_MCNTSET 0xc0
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#define REG09_CLKSET 0x30
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#define REG09_EVEN1ST 0x20
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#define REG09_BLINE1ST 0x10
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#define REG09_BACKSCAN 0x08
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#define REG09_ENHANCE 0x04
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#define REG09_SHORTTG 0x02
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@ -130,7 +130,7 @@
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#define REG09S_CLKSET 4
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#define REG0A_SRAMBUF 0x01
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#define REG0A_LPWMEN 0x10
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#define REG0B_DRAMSEL 0x07
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#define REG0B_ENBDRAM 0x08
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@ -167,6 +167,8 @@
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#define REG18_CKDELAY 0x0c
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#define REG18_CKSEL 0x03
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#define REG1A_SW2SET 0x80
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#define REG1A_SW1SET 0x40
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#define REG1A_MANUAL3 0x02
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#define REG1A_MANUAL1 0x01
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#define REG1A_CK4INV 0x08
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@ -222,24 +224,35 @@
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#define REG5E_STOPTIM 0x1f
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#define REG5ES_STOPTIM 0
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#define REG60_ZIMOD 0x1f
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#define REG60 0x60
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#define REG60_Z1MOD 0x1f
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#define REG61 0x61
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#define REG61_Z1MOD 0xff
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#define REG62 0x62
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#define REG62_Z1MOD 0xff
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#define REG63 0x63
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#define REG63_Z2MOD 0x1f
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#define REG64 0x64
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#define REG64_Z2MOD 0xff
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#define REG65 0x65
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#define REG65_Z2MOD 0xff
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#define REG67_STEPSEL 0xc0
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#define REG67_FULLSTEP 0x00
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#define REG67_HALFSTEP 0x40
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#define REG67_QUATERSTEP 0x80
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#define REG60S_STEPSEL 5
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#define REG60_FSTPSEL 0xe0
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#define REG60_FULLSTEP 0x00
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#define REG60_HALFSTEP 0x20
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#define REG60_EIGHTHSTEP 0x60
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#define REG60_16THSTEP 0x80
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#define REG63_FSTPSEL 0xe0
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#define REG63_FULLSTEP 0x00
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#define REG63_HALFSTEP 0x20
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#define REG63_EIGHTHSTEP 0x60
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#define REG63_16THSTEP 0x80
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#define REG67_MTRPWM 0x3f
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#define REG68_FSTPSEL 0xc0
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#define REG68_FULLSTEP 0x00
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#define REG68_HALFSTEP 0x40
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#define REG68_QUATERSTEP 0x80
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#define REG68_FASTPWM 0x3f
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#define REG6B_MULTFILM 0x80
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