diff --git a/backend/genesys/gl124_registers.h b/backend/genesys/gl124_registers.h index 623539e41..1daa97406 100644 --- a/backend/genesys/gl124_registers.h +++ b/backend/genesys/gl124_registers.h @@ -44,266 +44,271 @@ #ifndef BACKEND_GENESYS_GL124_REGISTERS_H #define BACKEND_GENESYS_GL124_REGISTERS_H +#include + namespace genesys { namespace gl124 { -#define REG_0x01 0x01 -#define REG_0x01_CISSET 0x80 -#define REG_0x01_DOGENB 0x40 -#define REG_0x01_DVDSET 0x20 -#define REG_0x01_STAGGER 0x10 -#define REG_0x01_COMPENB 0x08 -#define REG_0x01_TRUEGRAY 0x04 -#define REG_0x01_SHDAREA 0x02 -#define REG_0x01_SCAN 0x01 +using RegAddr = std::uint16_t; +using RegMask = std::uint8_t; +using RegShift = unsigned; -#define REG_0x02 0x02 -#define REG_0x02_NOTHOME 0x80 -#define REG_0x02_ACDCDIS 0x40 -#define REG_0x02_AGOHOME 0x20 -#define REG_0x02_MTRPWR 0x10 -#define REG_0x02_FASTFED 0x08 -#define REG_0x02_MTRREV 0x04 -#define REG_0x02_HOMENEG 0x02 -#define REG_0x02_LONGCURV 0x01 +static constexpr RegAddr REG_0x01 = 0x01; +static constexpr RegMask REG_0x01_CISSET = 0x80; +static constexpr RegMask REG_0x01_DOGENB = 0x40; +static constexpr RegMask REG_0x01_DVDSET = 0x20; +static constexpr RegMask REG_0x01_STAGGER = 0x10; +static constexpr RegMask REG_0x01_COMPENB = 0x08; +static constexpr RegMask REG_0x01_TRUEGRAY = 0x04; +static constexpr RegMask REG_0x01_SHDAREA = 0x02; +static constexpr RegMask REG_0x01_SCAN = 0x01; -#define REG_0x03 0x03 -#define REG_0x03_LAMPDOG 0x80 -#define REG_0x03_AVEENB 0x40 -#define REG_0x03_XPASEL 0x20 -#define REG_0x03_LAMPPWR 0x10 -#define REG_0x03_LAMPTIM 0x0f +static constexpr RegAddr REG_0x02 = 0x02; +static constexpr RegMask REG_0x02_NOTHOME = 0x80; +static constexpr RegMask REG_0x02_ACDCDIS = 0x40; +static constexpr RegMask REG_0x02_AGOHOME = 0x20; +static constexpr RegMask REG_0x02_MTRPWR = 0x10; +static constexpr RegMask REG_0x02_FASTFED = 0x08; +static constexpr RegMask REG_0x02_MTRREV = 0x04; +static constexpr RegMask REG_0x02_HOMENEG = 0x02; +static constexpr RegMask REG_0x02_LONGCURV = 0x01; -#define REG_0x04 0x04 -#define REG_0x04_LINEART 0x80 -#define REG_0x04_BITSET 0x40 -#define REG_0x04_FILTER 0x30 -#define REG_0x04_AFEMOD 0x07 +static constexpr RegAddr REG_0x03 = 0x03; +static constexpr RegMask REG_0x03_LAMPDOG = 0x80; +static constexpr RegMask REG_0x03_AVEENB = 0x40; +static constexpr RegMask REG_0x03_XPASEL = 0x20; +static constexpr RegMask REG_0x03_LAMPPWR = 0x10; +static constexpr RegMask REG_0x03_LAMPTIM = 0x0f; -#define REG_0x05 0x05 -#define REG_0x05_DPIHW 0xc0 -#define REG_0x05_DPIHW_600 0x00 -#define REG_0x05_DPIHW_1200 0x40 -#define REG_0x05_DPIHW_2400 0x80 -#define REG_0x05_DPIHW_4800 0xc0 -#define REG_0x05_MTLLAMP 0x30 -#define REG_0x05_GMMENB 0x08 -#define REG_0x05_ENB20M 0x04 -#define REG_0x05_MTLBASE 0x03 +static constexpr RegAddr REG_0x04 = 0x04; +static constexpr RegMask REG_0x04_LINEART = 0x80; +static constexpr RegMask REG_0x04_BITSET = 0x40; +static constexpr RegMask REG_0x04_FILTER = 0x30; +static constexpr RegMask REG_0x04_AFEMOD = 0x07; -#define REG_0x06 0x06 -#define REG_0x06_SCANMOD 0xe0 -#define REG_0x06S_SCANMOD 5 -#define REG_0x06_PWRBIT 0x10 -#define REG_0x06_GAIN4 0x08 -#define REG_0x06_OPTEST 0x07 +static constexpr RegAddr REG_0x05 = 0x05; +static constexpr RegMask REG_0x05_DPIHW = 0xc0; +static constexpr RegMask REG_0x05_DPIHW_600 = 0x00; +static constexpr RegMask REG_0x05_DPIHW_1200 = 0x40; +static constexpr RegMask REG_0x05_DPIHW_2400 = 0x80; +static constexpr RegMask REG_0x05_DPIHW_4800 = 0xc0; +static constexpr RegMask REG_0x05_MTLLAMP = 0x30; +static constexpr RegMask REG_0x05_GMMENB = 0x08; +static constexpr RegMask REG_0x05_ENB20M = 0x04; +static constexpr RegMask REG_0x05_MTLBASE = 0x03; -#define REG_0x07_LAMPSIM 0x80 +static constexpr RegAddr REG_0x06 = 0x06; +static constexpr RegMask REG_0x06_SCANMOD = 0xe0; +static constexpr RegMask REG_0x06S_SCANMOD = 5; +static constexpr RegMask REG_0x06_PWRBIT = 0x10; +static constexpr RegMask REG_0x06_GAIN4 = 0x08; +static constexpr RegMask REG_0x06_OPTEST = 0x07; -#define REG_0x08_DRAM2X 0x80 -#define REG_0x08_MPENB 0x20 -#define REG_0x08_CIS_LINE 0x10 -#define REG_0x08_IR2_ENB 0x08 -#define REG_0x08_IR1_ENB 0x04 -#define REG_0x08_ENB24M 0x01 +static constexpr RegMask REG_0x07_LAMPSIM = 0x80; -#define REG_0x09_MCNTSET 0xc0 -#define REG_0x09_EVEN1ST 0x20 -#define REG_0x09_BLINE1ST 0x10 -#define REG_0x09_BACKSCAN 0x08 -#define REG_0x09_OUTINV 0x04 -#define REG_0x09_SHORTTG 0x02 +static constexpr RegMask REG_0x08_DRAM2X = 0x80; +static constexpr RegMask REG_0x08_MPENB = 0x20; +static constexpr RegMask REG_0x08_CIS_LINE = 0x10; +static constexpr RegMask REG_0x08_IR2_ENB = 0x08; +static constexpr RegMask REG_0x08_IR1_ENB = 0x04; +static constexpr RegMask REG_0x08_ENB24M = 0x01; -#define REG_0x09S_MCNTSET 6 -#define REG_0x09S_CLKSET 4 +static constexpr RegMask REG_0x09_MCNTSET = 0xc0; +static constexpr RegMask REG_0x09_EVEN1ST = 0x20; +static constexpr RegMask REG_0x09_BLINE1ST = 0x10; +static constexpr RegMask REG_0x09_BACKSCAN = 0x08; +static constexpr RegMask REG_0x09_OUTINV = 0x04; +static constexpr RegMask REG_0x09_SHORTTG = 0x02; -#define REG_0x0A 0x0a -#define REG_0x0A_SIFSEL 0xc0 -#define REG_0x0AS_SIFSEL 6 -#define REG_0x0A_SHEETFED 0x20 -#define REG_0x0A_LPWMEN 0x10 +static constexpr RegShift REG_0x09S_MCNTSET = 6; +static constexpr RegShift REG_0x09S_CLKSET = 4; -#define REG_0x0B 0x0b -#define REG_0x0B_DRAMSEL 0x07 -#define REG_0x0B_16M 0x01 -#define REG_0x0B_64M 0x02 -#define REG_0x0B_128M 0x03 -#define REG_0x0B_256M 0x04 -#define REG_0x0B_512M 0x05 -#define REG_0x0B_1G 0x06 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_RFHDIS 0x10 -#define REG_0x0B_CLKSET 0xe0 -#define REG_0x0B_24MHZ 0x00 -#define REG_0x0B_30MHZ 0x20 -#define REG_0x0B_40MHZ 0x40 -#define REG_0x0B_48MHZ 0x60 -#define REG_0x0B_60MHZ 0x80 +static constexpr RegAddr REG_0x0A = 0x0a; +static constexpr RegMask REG_0x0A_SIFSEL = 0xc0; +static constexpr RegShift REG_0x0AS_SIFSEL = 6; +static constexpr RegMask REG_0x0A_SHEETFED = 0x20; +static constexpr RegMask REG_0x0A_LPWMEN = 0x10; -#define REG_0x0D 0x0d -#define REG_0x0D_MTRP_RDY 0x80 -#define REG_0x0D_FULLSTP 0x10 -#define REG_0x0D_CLRMCNT 0x04 -#define REG_0x0D_CLRDOCJM 0x02 -#define REG_0x0D_CLRLNCNT 0x01 +static constexpr RegAddr REG_0x0B = 0x0b; +static constexpr RegMask REG_0x0B_DRAMSEL = 0x07; +static constexpr RegMask REG_0x0B_16M = 0x01; +static constexpr RegMask REG_0x0B_64M = 0x02; +static constexpr RegMask REG_0x0B_128M = 0x03; +static constexpr RegMask REG_0x0B_256M = 0x04; +static constexpr RegMask REG_0x0B_512M = 0x05; +static constexpr RegMask REG_0x0B_1G = 0x06; +static constexpr RegMask REG_0x0B_ENBDRAM = 0x08; +static constexpr RegMask REG_0x0B_RFHDIS = 0x10; +static constexpr RegMask REG_0x0B_CLKSET = 0xe0; +static constexpr RegMask REG_0x0B_24MHZ = 0x00; +static constexpr RegMask REG_0x0B_30MHZ = 0x20; +static constexpr RegMask REG_0x0B_40MHZ = 0x40; +static constexpr RegMask REG_0x0B_48MHZ = 0x60; +static constexpr RegMask REG_0x0B_60MHZ = 0x80; -#define REG_0x0F 0x0f +static constexpr RegAddr REG_0x0D = 0x0d; +static constexpr RegMask REG_0x0D_MTRP_RDY = 0x80; +static constexpr RegMask REG_0x0D_FULLSTP = 0x10; +static constexpr RegMask REG_0x0D_CLRMCNT = 0x04; +static constexpr RegMask REG_0x0D_CLRDOCJM = 0x02; +static constexpr RegMask REG_0x0D_CLRLNCNT = 0x01; -#define REG_0x16_CTRLHI 0x80 -#define REG_0x16_TOSHIBA 0x40 -#define REG_0x16_TGINV 0x20 -#define REG_0x16_CK1INV 0x10 -#define REG_0x16_CK2INV 0x08 -#define REG_0x16_CTRLINV 0x04 -#define REG_0x16_CKDIS 0x02 -#define REG_0x16_CTRLDIS 0x01 +static constexpr RegAddr REG_0x0F = 0x0f; -#define REG_0x17_TGMODE 0xc0 -#define REG_0x17_SNRSYN 0x0f +static constexpr RegMask REG_0x16_CTRLHI = 0x80; +static constexpr RegMask REG_0x16_TOSHIBA = 0x40; +static constexpr RegMask REG_0x16_TGINV = 0x20; +static constexpr RegMask REG_0x16_CK1INV = 0x10; +static constexpr RegMask REG_0x16_CK2INV = 0x08; +static constexpr RegMask REG_0x16_CTRLINV = 0x04; +static constexpr RegMask REG_0x16_CKDIS = 0x02; +static constexpr RegMask REG_0x16_CTRLDIS = 0x01; -#define REG_0x18 0x18 -#define REG_0x18_CNSET 0x80 -#define REG_0x18_DCKSEL 0x60 -#define REG_0x18_CKTOGGLE 0x10 -#define REG_0x18_CKDELAY 0x0c -#define REG_0x18_CKSEL 0x03 +static constexpr RegMask REG_0x17_TGMODE = 0xc0; +static constexpr RegMask REG_0x17_SNRSYN = 0x0f; -#define REG_0x1A_SW2SET 0x80 -#define REG_0x1A_SW1SET 0x40 -#define REG_0x1A_MANUAL3 0x02 -#define REG_0x1A_MANUAL1 0x01 -#define REG_0x1A_CK4INV 0x08 -#define REG_0x1A_CK3INV 0x04 -#define REG_0x1A_LINECLP 0x02 +static constexpr RegAddr REG_0x18 = 0x18; +static constexpr RegMask REG_0x18_CNSET = 0x80; +static constexpr RegMask REG_0x18_DCKSEL = 0x60; +static constexpr RegMask REG_0x18_CKTOGGLE = 0x10; +static constexpr RegMask REG_0x18_CKDELAY = 0x0c; +static constexpr RegMask REG_0x18_CKSEL = 0x03; -#define REG_0x1C_TBTIME 0x07 +static constexpr RegMask REG_0x1A_SW2SET = 0x80; +static constexpr RegMask REG_0x1A_SW1SET = 0x40; +static constexpr RegMask REG_0x1A_MANUAL3 = 0x02; +static constexpr RegMask REG_0x1A_MANUAL1 = 0x01; +static constexpr RegMask REG_0x1A_CK4INV = 0x08; +static constexpr RegMask REG_0x1A_CK3INV = 0x04; +static constexpr RegMask REG_0x1A_LINECLP = 0x02; -#define REG_0x1D 0x1d -#define REG_0x1D_CK4LOW 0x80 -#define REG_0x1D_CK3LOW 0x40 -#define REG_0x1D_CK1LOW 0x20 -#define REG_0x1D_LINESEL 0x1f -#define REG_0x1DS_LINESEL 0 +static constexpr RegMask REG_0x1C_TBTIME = 0x07; -#define REG_0x1E 0x1e -#define REG_0x1E_WDTIME 0xf0 -#define REG_0x1ES_WDTIME 4 -#define REG_0x1E_WDTIME 0xf0 +static constexpr RegAddr REG_0x1D = 0x1d; +static constexpr RegMask REG_0x1D_CK4LOW = 0x80; +static constexpr RegMask REG_0x1D_CK3LOW = 0x40; +static constexpr RegMask REG_0x1D_CK1LOW = 0x20; +static constexpr RegMask REG_0x1D_LINESEL = 0x1f; +static constexpr RegShift REG_0x1DS_LINESEL = 0; -#define REG_0x30 0x30 -#define REG_0x31 0x31 -#define REG_0x32 0x32 -#define REG_0x32_GPIO16 0x80 -#define REG_0x32_GPIO15 0x40 -#define REG_0x32_GPIO14 0x20 -#define REG_0x32_GPIO13 0x10 -#define REG_0x32_GPIO12 0x08 -#define REG_0x32_GPIO11 0x04 -#define REG_0x32_GPIO10 0x02 -#define REG_0x32_GPIO9 0x01 -#define REG_0x33 0x33 -#define REG_0x34 0x34 -#define REG_0x35 0x35 -#define REG_0x36 0x36 -#define REG_0x37 0x37 -#define REG_0x38 0x38 -#define REG_0x39 0x39 +static constexpr RegAddr REG_0x1E = 0x1e; +static constexpr RegMask REG_0x1E_WDTIME = 0xf0; +static constexpr RegShift REG_0x1ES_WDTIME = 4; -#define REG_0x60 0x60 -#define REG_0x60_LED4TG 0x80 -#define REG_0x60_YENB 0x40 -#define REG_0x60_YBIT 0x20 -#define REG_0x60_ACYNCNRLC 0x10 -#define REG_0x60_ENOFFSET 0x08 -#define REG_0x60_LEDADD 0x04 -#define REG_0x60_CK4ADC 0x02 -#define REG_0x60_AUTOCONF 0x01 +static constexpr RegAddr REG_0x30 = 0x30; +static constexpr RegAddr REG_0x31 = 0x31; +static constexpr RegAddr REG_0x32 = 0x32; +static constexpr RegMask REG_0x32_GPIO16 = 0x80; +static constexpr RegMask REG_0x32_GPIO15 = 0x40; +static constexpr RegMask REG_0x32_GPIO14 = 0x20; +static constexpr RegMask REG_0x32_GPIO13 = 0x10; +static constexpr RegMask REG_0x32_GPIO12 = 0x08; +static constexpr RegMask REG_0x32_GPIO11 = 0x04; +static constexpr RegMask REG_0x32_GPIO10 = 0x02; +static constexpr RegMask REG_0x32_GPIO9 = 0x01; +static constexpr RegAddr REG_0x33 = 0x33; +static constexpr RegAddr REG_0x34 = 0x34; +static constexpr RegAddr REG_0x35 = 0x35; +static constexpr RegAddr REG_0x36 = 0x36; +static constexpr RegAddr REG_0x37 = 0x37; +static constexpr RegAddr REG_0x38 = 0x38; +static constexpr RegAddr REG_0x39 = 0x39; -#define REG_0x80 0x80 -#define REG_0x81 0x81 +static constexpr RegAddr REG_0x60 = 0x60; +static constexpr RegMask REG_0x60_LED4TG = 0x80; +static constexpr RegMask REG_0x60_YENB = 0x40; +static constexpr RegMask REG_0x60_YBIT = 0x20; +static constexpr RegMask REG_0x60_ACYNCNRLC = 0x10; +static constexpr RegMask REG_0x60_ENOFFSET = 0x08; +static constexpr RegMask REG_0x60_LEDADD = 0x04; +static constexpr RegMask REG_0x60_CK4ADC = 0x02; +static constexpr RegMask REG_0x60_AUTOCONF = 0x01; -#define REG_0xA0 0xa0 -#define REG_0xA0_FSTPSEL 0x28 -#define REG_0xA0S_FSTPSEL 3 -#define REG_0xA0_STEPSEL 0x03 -#define REG_0xA0S_STEPSEL 0 +static constexpr RegAddr REG_0x80 = 0x80; +static constexpr RegAddr REG_0x81 = 0x81; -#define REG_0xA1 0xa1 -#define REG_0xA2 0xa2 -#define REG_0xA3 0xa3 -#define REG_0xA4 0xa4 -#define REG_0xA5 0xa5 -#define REG_0xA6 0xa6 -#define REG_0xA7 0xa7 -#define REG_0xA8 0xa8 -#define REG_0xA9 0xa9 -#define REG_0xAA 0xaa -#define REG_0xAB 0xab -#define REG_0xAC 0xac -#define REG_0xAD 0xad -#define REG_0xAE 0xae -#define REG_0xAF 0xaf -#define REG_0xB0 0xb0 -#define REG_0xB1 0xb1 +static constexpr RegAddr REG_0xA0 = 0xa0; +static constexpr RegMask REG_0xA0_FSTPSEL = 0x28; +static constexpr RegShift REG_0xA0S_FSTPSEL = 3; +static constexpr RegMask REG_0xA0_STEPSEL = 0x03; +static constexpr RegShift REG_0xA0S_STEPSEL = 0; -#define REG_0xB2 0xb2 -#define REG_0xB2_Z1MOD 0x1f -#define REG_0xB3 0xb3 -#define REG_0xB3_Z1MOD 0xff -#define REG_0xB4 0xb4 -#define REG_0xB4_Z1MOD 0xff +static constexpr RegAddr REG_0xA1 = 0xa1; +static constexpr RegAddr REG_0xA2 = 0xa2; +static constexpr RegAddr REG_0xA3 = 0xa3; +static constexpr RegAddr REG_0xA4 = 0xa4; +static constexpr RegAddr REG_0xA5 = 0xa5; +static constexpr RegAddr REG_0xA6 = 0xa6; +static constexpr RegAddr REG_0xA7 = 0xa7; +static constexpr RegAddr REG_0xA8 = 0xa8; +static constexpr RegAddr REG_0xA9 = 0xa9; +static constexpr RegAddr REG_0xAA = 0xaa; +static constexpr RegAddr REG_0xAB = 0xab; +static constexpr RegAddr REG_0xAC = 0xac; +static constexpr RegAddr REG_0xAD = 0xad; +static constexpr RegAddr REG_0xAE = 0xae; +static constexpr RegAddr REG_0xAF = 0xaf; +static constexpr RegAddr REG_0xB0 = 0xb0; +static constexpr RegAddr REG_0xB1 = 0xb1; -#define REG_0xB5 0xb5 -#define REG_0xB5_Z2MOD 0x1f -#define REG_0xB6 0xb6 -#define REG_0xB6_Z2MOD 0xff -#define REG_0xB7 0xb7 -#define REG_0xB7_Z2MOD 0xff +static constexpr RegAddr REG_0xB2 = 0xb2; +static constexpr RegMask REG_0xB2_Z1MOD = 0x1f; +static constexpr RegAddr REG_0xB3 = 0xb3; +static constexpr RegMask REG_0xB3_Z1MOD = 0xff; +static constexpr RegAddr REG_0xB4 = 0xb4; +static constexpr RegMask REG_0xB4_Z1MOD = 0xff; -#define REG_0x100 0x100 -#define REG_0x100_DOCSNR 0x80 -#define REG_0x100_ADFSNR 0x40 -#define REG_0x100_COVERSNR 0x20 -#define REG_0x100_CHKVER 0x10 -#define REG_0x100_DOCJAM 0x08 -#define REG_0x100_HISPDFLG 0x04 -#define REG_0x100_MOTMFLG 0x02 -#define REG_0x100_DATAENB 0x01 +static constexpr RegAddr REG_0xB5 = 0xb5; +static constexpr RegMask REG_0xB5_Z2MOD = 0x1f; +static constexpr RegAddr REG_0xB6 = 0xb6; +static constexpr RegMask REG_0xB6_Z2MOD = 0xff; +static constexpr RegAddr REG_0xB7 = 0xb7; +static constexpr RegMask REG_0xB7_Z2MOD = 0xff; -#define REG_0x114 0x114 -#define REG_0x115 0x115 +static constexpr RegAddr REG_0x100 = 0x100; +static constexpr RegMask REG_0x100_DOCSNR = 0x80; +static constexpr RegMask REG_0x100_ADFSNR = 0x40; +static constexpr RegMask REG_0x100_COVERSNR = 0x20; +static constexpr RegMask REG_0x100_CHKVER = 0x10; +static constexpr RegMask REG_0x100_DOCJAM = 0x08; +static constexpr RegMask REG_0x100_HISPDFLG = 0x04; +static constexpr RegMask REG_0x100_MOTMFLG = 0x02; +static constexpr RegMask REG_0x100_DATAENB = 0x01; -#define REG_LINCNT 0x25 -#define REG_MAXWD 0x28 -#define REG_DPISET 0x2c -#define REG_FEEDL 0x3d -#define REG_CK1MAP 0x74 -#define REG_CK3MAP 0x77 -#define REG_CK4MAP 0x7a -#define REG_LPERIOD 0x7d -#define REG_DUMMY 0x80 -#define REG_STRPIXEL 0x82 -#define REG_ENDPIXEL 0x85 -#define REG_EXPDMY 0x88 -#define REG_EXPR 0x8a -#define REG_EXPG 0x8d -#define REG_EXPB 0x90 -#define REG_SEGCNT 0x93 -#define REG_TG0CNT 0x96 -#define REG_SCANFED 0xa2 -#define REG_STEPNO 0xa4 -#define REG_FWDSTEP 0xa6 -#define REG_BWDSTEP 0xa8 -#define REG_FASTNO 0xaa -#define REG_FSHDEC 0xac -#define REG_FMOVNO 0xae -#define REG_FMOVDEC 0xb0 -#define REG_Z1MOD 0xb2 -#define REG_Z2MOD 0xb5 +static constexpr RegAddr REG_0x114 = 0x114; +static constexpr RegAddr REG_0x115 = 0x115; -#define REG_TRUER 0x110 -#define REG_TRUEG 0x111 -#define REG_TRUEB 0x112 +static constexpr RegAddr REG_LINCNT = 0x25; +static constexpr RegAddr REG_MAXWD = 0x28; +static constexpr RegAddr REG_DPISET = 0x2c; +static constexpr RegAddr REG_FEEDL = 0x3d; +static constexpr RegAddr REG_CK1MAP = 0x74; +static constexpr RegAddr REG_CK3MAP = 0x77; +static constexpr RegAddr REG_CK4MAP = 0x7a; +static constexpr RegAddr REG_LPERIOD = 0x7d; +static constexpr RegAddr REG_DUMMY = 0x80; +static constexpr RegAddr REG_STRPIXEL = 0x82; +static constexpr RegAddr REG_ENDPIXEL = 0x85; +static constexpr RegAddr REG_EXPDMY = 0x88; +static constexpr RegAddr REG_EXPR = 0x8a; +static constexpr RegAddr REG_EXPG = 0x8d; +static constexpr RegAddr REG_EXPB = 0x90; +static constexpr RegAddr REG_SEGCNT = 0x93; +static constexpr RegAddr REG_TG0CNT = 0x96; +static constexpr RegAddr REG_SCANFED = 0xa2; +static constexpr RegAddr REG_STEPNO = 0xa4; +static constexpr RegAddr REG_FWDSTEP = 0xa6; +static constexpr RegAddr REG_BWDSTEP = 0xa8; +static constexpr RegAddr REG_FASTNO = 0xaa; +static constexpr RegAddr REG_FSHDEC = 0xac; +static constexpr RegAddr REG_FMOVNO = 0xae; +static constexpr RegAddr REG_FMOVDEC = 0xb0; +static constexpr RegAddr REG_Z1MOD = 0xb2; +static constexpr RegAddr REG_Z2MOD = 0xb5; + +static constexpr RegAddr REG_TRUER = 0x110; +static constexpr RegAddr REG_TRUEG = 0x111; +static constexpr RegAddr REG_TRUEB = 0x112; } // namespace gl124 } // namespace genesys diff --git a/backend/genesys/gl646_registers.h b/backend/genesys/gl646_registers.h index 80f5aabf0..76ed24dc6 100644 --- a/backend/genesys/gl646_registers.h +++ b/backend/genesys/gl646_registers.h @@ -44,123 +44,129 @@ #ifndef BACKEND_GENESYS_GL646_REGISTERS_H #define BACKEND_GENESYS_GL646_REGISTERS_H +#include + namespace genesys { namespace gl646 { -#define REG_0x01_CISSET 0x80 -#define REG_0x01_DOGENB 0x40 -#define REG_0x01_DVDSET 0x20 -#define REG_0x01_FASTMOD 0x10 -#define REG_0x01_COMPENB 0x08 -#define REG_0x01_DRAMSEL 0x04 -#define REG_0x01_SHDAREA 0x02 -#define REG_0x01_SCAN 0x01 +using RegAddr = std::uint16_t; +using RegMask = std::uint8_t; +using RegShift = unsigned; -#define REG_0x02_NOTHOME 0x80 -#define REG_0x02_ACDCDIS 0x40 -#define REG_0x02_AGOHOME 0x20 -#define REG_0x02_MTRPWR 0x10 -#define REG_0x02_FASTFED 0x08 -#define REG_0x02_MTRREV 0x04 -#define REG_0x02_STEPSEL 0x03 +static constexpr RegMask REG_0x01_CISSET = 0x80; +static constexpr RegMask REG_0x01_DOGENB = 0x40; +static constexpr RegMask REG_0x01_DVDSET = 0x20; +static constexpr RegMask REG_0x01_FASTMOD = 0x10; +static constexpr RegMask REG_0x01_COMPENB = 0x08; +static constexpr RegMask REG_0x01_DRAMSEL = 0x04; +static constexpr RegMask REG_0x01_SHDAREA = 0x02; +static constexpr RegMask REG_0x01_SCAN = 0x01; -#define REG_0x02_FULLSTEP 0x00 -#define REG_0x02_HALFSTEP 0x01 -#define REG_0x02_QUATERSTEP 0x02 +static constexpr RegMask REG_0x02_NOTHOME = 0x80; +static constexpr RegMask REG_0x02_ACDCDIS = 0x40; +static constexpr RegMask REG_0x02_AGOHOME = 0x20; +static constexpr RegMask REG_0x02_MTRPWR = 0x10; +static constexpr RegMask REG_0x02_FASTFED = 0x08; +static constexpr RegMask REG_0x02_MTRREV = 0x04; +static constexpr RegMask REG_0x02_STEPSEL = 0x03; -#define REG_0x03_TG3 0x80 -#define REG_0x03_AVEENB 0x40 -#define REG_0x03_XPASEL 0x20 -#define REG_0x03_LAMPPWR 0x10 -#define REG_0x03_LAMPDOG 0x08 -#define REG_0x03_LAMPTIM 0x07 +static constexpr RegMask REG_0x02_FULLSTEP = 0x00; +static constexpr RegMask REG_0x02_HALFSTEP = 0x01; +static constexpr RegMask REG_0x02_QUATERSTEP = 0x02; -#define REG_0x04_LINEART 0x80 -#define REG_0x04_BITSET 0x40 -#define REG_0x04_ADTYPE 0x30 -#define REG_0x04_FILTER 0x0c -#define REG_0x04_FESET 0x03 +static constexpr RegMask REG_0x03_TG3 = 0x80; +static constexpr RegMask REG_0x03_AVEENB = 0x40; +static constexpr RegMask REG_0x03_XPASEL = 0x20; +static constexpr RegMask REG_0x03_LAMPPWR = 0x10; +static constexpr RegMask REG_0x03_LAMPDOG = 0x08; +static constexpr RegMask REG_0x03_LAMPTIM = 0x07; -#define REG_0x05_DPIHW 0xc0 -#define REG_0x05_DPIHW_600 0x00 -#define REG_0x05_DPIHW_1200 0x40 -#define REG_0x05_DPIHW_2400 0x80 -#define REG_0x05_DPIHW_4800 0xc0 -#define REG_0x05_GMMTYPE 0x30 -#define REG_0x05_GMM14BIT 0x10 -#define REG_0x05_GMMENB 0x08 -#define REG_0x05_LEDADD 0x04 -#define REG_0x05_BASESEL 0x03 +static constexpr RegMask REG_0x04_LINEART = 0x80; +static constexpr RegMask REG_0x04_BITSET = 0x40; +static constexpr RegMask REG_0x04_ADTYPE = 0x30; +static constexpr RegMask REG_0x04_FILTER = 0x0c; +static constexpr RegMask REG_0x04_FESET = 0x03; -#define REG_0x06_PWRBIT 0x10 -#define REG_0x06_GAIN4 0x08 -#define REG_0x06_OPTEST 0x07 +static constexpr RegMask REG_0x05_DPIHW = 0xc0; +static constexpr RegMask REG_0x05_DPIHW_600 = 0x00; +static constexpr RegMask REG_0x05_DPIHW_1200 = 0x40; +static constexpr RegMask REG_0x05_DPIHW_2400 = 0x80; +static constexpr RegMask REG_0x05_DPIHW_4800 = 0xc0; +static constexpr RegMask REG_0x05_GMMTYPE = 0x30; +static constexpr RegMask REG_0x05_GMM14BIT = 0x10; +static constexpr RegMask REG_0x05_GMMENB = 0x08; +static constexpr RegMask REG_0x05_LEDADD = 0x04; +static constexpr RegMask REG_0x05_BASESEL = 0x03; -#define REG_0x07_DMASEL 0x02 -#define REG_0x07_DMARDWR 0x01 +static constexpr RegMask REG_0x06_PWRBIT = 0x10; +static constexpr RegMask REG_0x06_GAIN4 = 0x08; +static constexpr RegMask REG_0x06_OPTEST = 0x07; -#define REG_0x16_CTRLHI 0x80 -#define REG_0x16_SELINV 0x40 -#define REG_0x16_TGINV 0x20 -#define REG_0x16_CK1INV 0x10 -#define REG_0x16_CK2INV 0x08 -#define REG_0x16_CTRLINV 0x04 -#define REG_0x16_CKDIS 0x02 -#define REG_0x16_CTRLDIS 0x01 +static constexpr RegMask REG_0x07_DMASEL = 0x02; +static constexpr RegMask REG_0x07_DMARDWR = 0x01; -#define REG_0x17_TGMODE 0xc0 -#define REG_0x17_TGMODE_NO_DUMMY 0x00 -#define REG_0x17_TGMODE_REF 0x40 -#define REG_0x17_TGMODE_XPA 0x80 -#define REG_0x17_TGW 0x3f +static constexpr RegMask REG_0x16_CTRLHI = 0x80; +static constexpr RegMask REG_0x16_SELINV = 0x40; +static constexpr RegMask REG_0x16_TGINV = 0x20; +static constexpr RegMask REG_0x16_CK1INV = 0x10; +static constexpr RegMask REG_0x16_CK2INV = 0x08; +static constexpr RegMask REG_0x16_CTRLINV = 0x04; +static constexpr RegMask REG_0x16_CKDIS = 0x02; +static constexpr RegMask REG_0x16_CTRLDIS = 0x01; -#define REG_0x18_CNSET 0x80 -#define REG_0x18_DCKSEL 0x60 -#define REG_0x18_CKTOGGLE 0x10 -#define REG_0x18_CKDELAY 0x0c -#define REG_0x18_CKSEL 0x03 +static constexpr RegMask REG_0x17_TGMODE = 0xc0; +static constexpr RegMask REG_0x17_TGMODE_NO_DUMMY = 0x00; +static constexpr RegMask REG_0x17_TGMODE_REF = 0x40; +static constexpr RegMask REG_0x17_TGMODE_XPA = 0x80; +static constexpr RegMask REG_0x17_TGW = 0x3f; -#define REG_0x1D_CKMANUAL 0x80 +static constexpr RegMask REG_0x18_CNSET = 0x80; +static constexpr RegMask REG_0x18_DCKSEL = 0x60; +static constexpr RegMask REG_0x18_CKTOGGLE = 0x10; +static constexpr RegMask REG_0x18_CKDELAY = 0x0c; +static constexpr RegMask REG_0x18_CKSEL = 0x03; -#define REG_0x1E_WDTIME 0xf0 -#define REG_0x1E_LINESEL 0x0f +static constexpr RegMask REG_0x1D_CKMANUAL = 0x80; -#define REG_0x41_PWRBIT 0x80 -#define REG_0x41_BUFEMPTY 0x40 -#define REG_0x41_FEEDFSH 0x20 -#define REG_0x41_SCANFSH 0x10 -#define REG_0x41_HOMESNR 0x08 -#define REG_0x41_LAMPSTS 0x04 -#define REG_0x41_FEBUSY 0x02 -#define REG_0x41_MOTMFLG 0x01 +static constexpr RegMask REG_0x1E_WDTIME = 0xf0; +static constexpr RegMask REG_0x1E_LINESEL = 0x0f; -#define REG_0x66_LOW_CURRENT 0x10 +static constexpr RegMask REG_0x41_PWRBIT = 0x80; +static constexpr RegMask REG_0x41_BUFEMPTY = 0x40; +static constexpr RegMask REG_0x41_FEEDFSH = 0x20; +static constexpr RegMask REG_0x41_SCANFSH = 0x10; +static constexpr RegMask REG_0x41_HOMESNR = 0x08; +static constexpr RegMask REG_0x41_LAMPSTS = 0x04; +static constexpr RegMask REG_0x41_FEBUSY = 0x02; +static constexpr RegMask REG_0x41_MOTMFLG = 0x01; -#define REG_0x6A_FSTPSEL 0xc0 -#define REG_0x6A_FASTPWM 0x3f +static constexpr RegMask REG_0x66_LOW_CURRENT = 0x10; -#define REG_0x6C_TGTIME 0xc0 -#define REG_0x6C_Z1MOD 0x38 -#define REG_0x6C_Z2MOD 0x07 +static constexpr RegMask REG_0x6A_FSTPSEL = 0xc0; +static constexpr RegMask REG_0x6A_FASTPWM = 0x3f; -#define REG_EXPR 0x10 -#define REG_EXPG 0x12 -#define REG_EXPB 0x14 -#define REG_SCANFED 0x1f -#define REG_BUFSEL 0x20 -#define REG_LINCNT 0x25 -#define REG_DPISET 0x2c -#define REG_STRPIXEL 0x30 -#define REG_ENDPIXEL 0x32 -#define REG_DUMMY 0x34 -#define REG_MAXWD 0x35 -#define REG_LPERIOD 0x38 -#define REG_FEEDL 0x3d -#define REG_VALIDWORD 0x42 -#define REG_FEDCNT 0x48 -#define REG_SCANCNT 0x4b -#define REG_Z1MOD 0x60 -#define REG_Z2MOD 0x62 +static constexpr RegMask REG_0x6C_TGTIME = 0xc0; +static constexpr RegMask REG_0x6C_Z1MOD = 0x38; +static constexpr RegMask REG_0x6C_Z2MOD = 0x07; + +static constexpr RegAddr REG_EXPR = 0x10; +static constexpr RegAddr REG_EXPG = 0x12; +static constexpr RegAddr REG_EXPB = 0x14; +static constexpr RegAddr REG_SCANFED = 0x1f; +static constexpr RegAddr REG_BUFSEL = 0x20; +static constexpr RegAddr REG_LINCNT = 0x25; +static constexpr RegAddr REG_DPISET = 0x2c; +static constexpr RegAddr REG_STRPIXEL = 0x30; +static constexpr RegAddr REG_ENDPIXEL = 0x32; +static constexpr RegAddr REG_DUMMY = 0x34; +static constexpr RegAddr REG_MAXWD = 0x35; +static constexpr RegAddr REG_LPERIOD = 0x38; +static constexpr RegAddr REG_FEEDL = 0x3d; +static constexpr RegAddr REG_VALIDWORD = 0x42; +static constexpr RegAddr REG_FEDCNT = 0x48; +static constexpr RegAddr REG_SCANCNT = 0x4b; +static constexpr RegAddr REG_Z1MOD = 0x60; +static constexpr RegAddr REG_Z2MOD = 0x62; } // namespace gl646 } // namespace genesys diff --git a/backend/genesys/gl841_registers.h b/backend/genesys/gl841_registers.h index 7f5b9120f..0e45db644 100644 --- a/backend/genesys/gl841_registers.h +++ b/backend/genesys/gl841_registers.h @@ -44,217 +44,222 @@ #ifndef BACKEND_GENESYS_GL841_REGISTERS_H #define BACKEND_GENESYS_GL841_REGISTERS_H +#include + namespace genesys { namespace gl841 { -/* Individual bits */ -#define REG_0x01 0x01 -#define REG_0x01_CISSET 0x80 -#define REG_0x01_DOGENB 0x40 -#define REG_0x01_DVDSET 0x20 -#define REG_0x01_M16DRAM 0x08 -#define REG_0x01_DRAMSEL 0x04 -#define REG_0x01_SHDAREA 0x02 -#define REG_0x01_SCAN 0x01 +using RegAddr = std::uint16_t; +using RegMask = std::uint8_t; +using RegShift = unsigned; -#define REG_0x02 0x02 -#define REG_0x02_NOTHOME 0x80 -#define REG_0x02_ACDCDIS 0x40 -#define REG_0x02_AGOHOME 0x20 -#define REG_0x02_MTRPWR 0x10 -#define REG_0x02_FASTFED 0x08 -#define REG_0x02_MTRREV 0x04 -#define REG_0x02_HOMENEG 0x02 -#define REG_0x02_LONGCURV 0x01 +static constexpr RegAddr REG_0x01 = 0x01; +static constexpr RegMask REG_0x01_CISSET = 0x80; +static constexpr RegMask REG_0x01_DOGENB = 0x40; +static constexpr RegMask REG_0x01_DVDSET = 0x20; +static constexpr RegMask REG_0x01_M16DRAM = 0x08; +static constexpr RegMask REG_0x01_DRAMSEL = 0x04; +static constexpr RegMask REG_0x01_SHDAREA = 0x02; +static constexpr RegMask REG_0x01_SCAN = 0x01; -#define REG_0x03_LAMPDOG 0x80 -#define REG_0x03_AVEENB 0x40 -#define REG_0x03_XPASEL 0x20 -#define REG_0x03_LAMPPWR 0x10 -#define REG_0x03_LAMPTIM 0x0f +static constexpr RegAddr REG_0x02 = 0x02; +static constexpr RegMask REG_0x02_NOTHOME = 0x80; +static constexpr RegMask REG_0x02_ACDCDIS = 0x40; +static constexpr RegMask REG_0x02_AGOHOME = 0x20; +static constexpr RegMask REG_0x02_MTRPWR = 0x10; +static constexpr RegMask REG_0x02_FASTFED = 0x08; +static constexpr RegMask REG_0x02_MTRREV = 0x04; +static constexpr RegMask REG_0x02_HOMENEG = 0x02; +static constexpr RegMask REG_0x02_LONGCURV = 0x01; -#define REG_0x04_LINEART 0x80 -#define REG_0x04_BITSET 0x40 -#define REG_0x04_AFEMOD 0x30 -#define REG_0x04_FILTER 0x0c -#define REG_0x04_FESET 0x03 +static constexpr RegMask REG_0x03_LAMPDOG = 0x80; +static constexpr RegMask REG_0x03_AVEENB = 0x40; +static constexpr RegMask REG_0x03_XPASEL = 0x20; +static constexpr RegMask REG_0x03_LAMPPWR = 0x10; +static constexpr RegMask REG_0x03_LAMPTIM = 0x0f; -#define REG_0x04S_AFEMOD 4 +static constexpr RegMask REG_0x04_LINEART = 0x80; +static constexpr RegMask REG_0x04_BITSET = 0x40; +static constexpr RegMask REG_0x04_AFEMOD = 0x30; +static constexpr RegMask REG_0x04_FILTER = 0x0c; +static constexpr RegMask REG_0x04_FESET = 0x03; -#define REG_0x05 0x05 -#define REG_0x05_DPIHW 0xc0 -#define REG_0x05_DPIHW_600 0x00 -#define REG_0x05_DPIHW_1200 0x40 -#define REG_0x05_DPIHW_2400 0x80 -#define REG_0x05_MTLLAMP 0x30 -#define REG_0x05_GMMENB 0x08 -#define REG_0x05_MTLBASE 0x03 +static constexpr RegShift REG_0x04S_AFEMOD = 4; -#define REG_0x06_SCANMOD 0xe0 -#define REG_0x06S_SCANMOD 5 -#define REG_0x06_PWRBIT 0x10 -#define REG_0x06_GAIN4 0x08 -#define REG_0x06_OPTEST 0x07 +static constexpr RegAddr REG_0x05 = 0x05; +static constexpr RegMask REG_0x05_DPIHW = 0xc0; +static constexpr RegMask REG_0x05_DPIHW_600 = 0x00; +static constexpr RegMask REG_0x05_DPIHW_1200 = 0x40; +static constexpr RegMask REG_0x05_DPIHW_2400 = 0x80; +static constexpr RegMask REG_0x05_MTLLAMP = 0x30; +static constexpr RegMask REG_0x05_GMMENB = 0x08; +static constexpr RegMask REG_0x05_MTLBASE = 0x03; -#define REG_0x07_SRAMSEL 0x08 -#define REG_0x07_FASTDMA 0x04 -#define REG_0x07_DMASEL 0x02 -#define REG_0x07_DMARDWR 0x01 +static constexpr RegMask REG_0x06_SCANMOD = 0xe0; +static constexpr RegShift REG_0x06S_SCANMOD = 5; +static constexpr RegMask REG_0x06_PWRBIT = 0x10; +static constexpr RegMask REG_0x06_GAIN4 = 0x08; +static constexpr RegMask REG_0x06_OPTEST = 0x07; -#define REG_0x08_DECFLAG 0x40 -#define REG_0x08_GMMFFR 0x20 -#define REG_0x08_GMMFFG 0x10 -#define REG_0x08_GMMFFB 0x08 -#define REG_0x08_GMMZR 0x04 -#define REG_0x08_GMMZG 0x02 -#define REG_0x08_GMMZB 0x01 +static constexpr RegMask REG_0x07_SRAMSEL = 0x08; +static constexpr RegMask REG_0x07_FASTDMA = 0x04; +static constexpr RegMask REG_0x07_DMASEL = 0x02; +static constexpr RegMask REG_0x07_DMARDWR = 0x01; -#define REG_0x09_MCNTSET 0xc0 -#define REG_0x09_CLKSET 0x30 -#define REG_0x09_BACKSCAN 0x08 -#define REG_0x09_ENHANCE 0x04 -#define REG_0x09_SHORTTG 0x02 -#define REG_0x09_NWAIT 0x01 +static constexpr RegMask REG_0x08_DECFLAG = 0x40; +static constexpr RegMask REG_0x08_GMMFFR = 0x20; +static constexpr RegMask REG_0x08_GMMFFG = 0x10; +static constexpr RegMask REG_0x08_GMMFFB = 0x08; +static constexpr RegMask REG_0x08_GMMZR = 0x04; +static constexpr RegMask REG_0x08_GMMZG = 0x02; +static constexpr RegMask REG_0x08_GMMZB = 0x01; -#define REG_0x09S_MCNTSET 6 -#define REG_0x09S_CLKSET 4 +static constexpr RegMask REG_0x09_MCNTSET = 0xc0; +static constexpr RegMask REG_0x09_CLKSET = 0x30; +static constexpr RegMask REG_0x09_BACKSCAN = 0x08; +static constexpr RegMask REG_0x09_ENHANCE = 0x04; +static constexpr RegMask REG_0x09_SHORTTG = 0x02; +static constexpr RegMask REG_0x09_NWAIT = 0x01; + +static constexpr RegShift REG_0x09S_MCNTSET = 6; +static constexpr RegShift REG_0x09S_CLKSET = 4; -#define REG_0x0A_SRAMBUF 0x01 +static constexpr RegMask REG_0x0A_SRAMBUF = 0x01; -#define REG_0x0D 0x0d -#define REG_0x0D_CLRLNCNT 0x01 +static constexpr RegAddr REG_0x0D = 0x0d; +static constexpr RegMask REG_0x0D_CLRLNCNT = 0x01; -#define REG_0x16_CTRLHI 0x80 -#define REG_0x16_TOSHIBA 0x40 -#define REG_0x16_TGINV 0x20 -#define REG_0x16_CK1INV 0x10 -#define REG_0x16_CK2INV 0x08 -#define REG_0x16_CTRLINV 0x04 -#define REG_0x16_CKDIS 0x02 -#define REG_0x16_CTRLDIS 0x01 +static constexpr RegMask REG_0x16_CTRLHI = 0x80; +static constexpr RegMask REG_0x16_TOSHIBA = 0x40; +static constexpr RegMask REG_0x16_TGINV = 0x20; +static constexpr RegMask REG_0x16_CK1INV = 0x10; +static constexpr RegMask REG_0x16_CK2INV = 0x08; +static constexpr RegMask REG_0x16_CTRLINV = 0x04; +static constexpr RegMask REG_0x16_CKDIS = 0x02; +static constexpr RegMask REG_0x16_CTRLDIS = 0x01; -#define REG_0x17_TGMODE 0xc0 -#define REG_0x17_TGMODE_NO_DUMMY 0x00 -#define REG_0x17_TGMODE_REF 0x40 -#define REG_0x17_TGMODE_XPA 0x80 -#define REG_0x17_TGW 0x3f -#define REG_0x17S_TGW 0 +static constexpr RegMask REG_0x17_TGMODE = 0xc0; +static constexpr RegMask REG_0x17_TGMODE_NO_DUMMY = 0x00; +static constexpr RegMask REG_0x17_TGMODE_REF = 0x40; +static constexpr RegMask REG_0x17_TGMODE_XPA = 0x80; +static constexpr RegMask REG_0x17_TGW = 0x3f; +static constexpr RegShift REG_0x17S_TGW = 0; -#define REG_0x18_CNSET 0x80 -#define REG_0x18_DCKSEL 0x60 -#define REG_0x18_CKTOGGLE 0x10 -#define REG_0x18_CKDELAY 0x0c -#define REG_0x18_CKSEL 0x03 +static constexpr RegMask REG_0x18_CNSET = 0x80; +static constexpr RegMask REG_0x18_DCKSEL = 0x60; +static constexpr RegMask REG_0x18_CKTOGGLE = 0x10; +static constexpr RegMask REG_0x18_CKDELAY = 0x0c; +static constexpr RegMask REG_0x18_CKSEL = 0x03; -#define REG_0x1A_MANUAL3 0x02 -#define REG_0x1A_MANUAL1 0x01 -#define REG_0x1A_CK4INV 0x08 -#define REG_0x1A_CK3INV 0x04 -#define REG_0x1A_LINECLP 0x02 +static constexpr RegMask REG_0x1A_MANUAL3 = 0x02; +static constexpr RegMask REG_0x1A_MANUAL1 = 0x01; +static constexpr RegMask REG_0x1A_CK4INV = 0x08; +static constexpr RegMask REG_0x1A_CK3INV = 0x04; +static constexpr RegMask REG_0x1A_LINECLP = 0x02; -#define REG_0x1C_TGTIME 0x07 +static constexpr RegMask REG_0x1C_TGTIME = 0x07; -#define REG_0x1D_CK4LOW 0x80 -#define REG_0x1D_CK3LOW 0x40 -#define REG_0x1D_CK1LOW 0x20 -#define REG_0x1D_TGSHLD 0x1f -#define REG_0x1DS_TGSHLD 0 +static constexpr RegMask REG_0x1D_CK4LOW = 0x80; +static constexpr RegMask REG_0x1D_CK3LOW = 0x40; +static constexpr RegMask REG_0x1D_CK1LOW = 0x20; +static constexpr RegMask REG_0x1D_TGSHLD = 0x1f; +static constexpr RegShift REG_0x1DS_TGSHLD = 0; -#define REG_0x1E 0x1e -#define REG_0x1E_WDTIME 0xf0 -#define REG_0x1ES_WDTIME 4 -#define REG_0x1E_LINESEL 0x0f -#define REG_0x1ES_LINESEL 0 +static constexpr RegAddr REG_0x1E = 0x1e; +static constexpr RegMask REG_0x1E_WDTIME = 0xf0; +static constexpr RegShift REG_0x1ES_WDTIME = 4; +static constexpr RegMask REG_0x1E_LINESEL = 0x0f; +static constexpr RegShift REG_0x1ES_LINESEL = 0; -#define REG_EXPR 0x10 -#define REG_EXPG 0x12 -#define REG_EXPB 0x14 -#define REG_STEPNO 0x21 -#define REG_FWDSTEP 0x22 -#define REG_BWDSTEP 0x23 -#define REG_FASTNO 0x24 -#define REG_LINCNT 0x25 -#define REG_DPISET 0x2c -#define REG_STRPIXEL 0x30 -#define REG_ENDPIXEL 0x32 -#define REG_MAXWD 0x35 -#define REG_LPERIOD 0x38 +static constexpr RegAddr REG_EXPR = 0x10; +static constexpr RegAddr REG_EXPG = 0x12; +static constexpr RegAddr REG_EXPB = 0x14; +static constexpr RegAddr REG_STEPNO = 0x21; +static constexpr RegAddr REG_FWDSTEP = 0x22; +static constexpr RegAddr REG_BWDSTEP = 0x23; +static constexpr RegAddr REG_FASTNO = 0x24; +static constexpr RegAddr REG_LINCNT = 0x25; +static constexpr RegAddr REG_DPISET = 0x2c; +static constexpr RegAddr REG_STRPIXEL = 0x30; +static constexpr RegAddr REG_ENDPIXEL = 0x32; +static constexpr RegAddr REG_MAXWD = 0x35; +static constexpr RegAddr REG_LPERIOD = 0x38; -#define REG_0x40_HISPDFLG 0x04 -#define REG_0x40_MOTMFLG 0x02 -#define REG_0x40_DATAENB 0x01 +static constexpr RegMask REG_0x40_HISPDFLG = 0x04; +static constexpr RegMask REG_0x40_MOTMFLG = 0x02; +static constexpr RegMask REG_0x40_DATAENB = 0x01; -#define REG_0x41_PWRBIT 0x80 -#define REG_0x41_BUFEMPTY 0x40 -#define REG_0x41_FEEDFSH 0x20 -#define REG_0x41_SCANFSH 0x10 -#define REG_0x41_HOMESNR 0x08 -#define REG_0x41_LAMPSTS 0x04 -#define REG_0x41_FEBUSY 0x02 -#define REG_0x41_MOTORENB 0x01 +static constexpr RegMask REG_0x41_PWRBIT = 0x80; +static constexpr RegMask REG_0x41_BUFEMPTY = 0x40; +static constexpr RegMask REG_0x41_FEEDFSH = 0x20; +static constexpr RegMask REG_0x41_SCANFSH = 0x10; +static constexpr RegMask REG_0x41_HOMESNR = 0x08; +static constexpr RegMask REG_0x41_LAMPSTS = 0x04; +static constexpr RegMask REG_0x41_FEBUSY = 0x02; +static constexpr RegMask REG_0x41_MOTORENB = 0x01; -#define REG_0x58_VSMP 0xf8 -#define REG_0x58S_VSMP 3 -#define REG_0x58_VSMPW 0x07 -#define REG_0x58S_VSMPW 0 +static constexpr RegMask REG_0x58_VSMP = 0xf8; +static constexpr RegShift REG_0x58S_VSMP = 3; +static constexpr RegMask REG_0x58_VSMPW = 0x07; +static constexpr RegShift REG_0x58S_VSMPW = 0; -#define REG_0x59_BSMP 0xf8 -#define REG_0x59S_BSMP 3 -#define REG_0x59_BSMPW 0x07 -#define REG_0x59S_BSMPW 0 +static constexpr RegMask REG_0x59_BSMP = 0xf8; +static constexpr RegShift REG_0x59S_BSMP = 3; +static constexpr RegMask REG_0x59_BSMPW = 0x07; +static constexpr RegShift REG_0x59S_BSMPW = 0; -#define REG_0x5A_ADCLKINV 0x80 -#define REG_0x5A_RLCSEL 0x40 -#define REG_0x5A_CDSREF 0x30 -#define REG_0x5AS_CDSREF 4 -#define REG_0x5A_RLC 0x0f -#define REG_0x5AS_RLC 0 +static constexpr RegMask REG_0x5A_ADCLKINV = 0x80; +static constexpr RegMask REG_0x5A_RLCSEL = 0x40; +static constexpr RegMask REG_0x5A_CDSREF = 0x30; +static constexpr RegShift REG_0x5AS_CDSREF = 4; +static constexpr RegMask REG_0x5A_RLC = 0x0f; +static constexpr RegShift REG_0x5AS_RLC = 0; -#define REG_0x5E_DECSEL 0xe0 -#define REG_0x5ES_DECSEL 5 -#define REG_0x5E_STOPTIM 0x1f -#define REG_0x5ES_STOPTIM 0 +static constexpr RegMask REG_0x5E_DECSEL = 0xe0; +static constexpr RegShift REG_0x5ES_DECSEL = 5; +static constexpr RegMask REG_0x5E_STOPTIM = 0x1f; +static constexpr RegShift REG_0x5ES_STOPTIM = 0; -#define REG_0x60_ZIMOD 0x1f -#define REG_0x61_Z1MOD 0xff -#define REG_0x62_Z1MOD 0xff +static constexpr RegMask REG_0x60_ZIMOD = 0x1f; +static constexpr RegMask REG_0x61_Z1MOD = 0xff; +static constexpr RegMask REG_0x62_Z1MOD = 0xff; -#define REG_0x63_Z2MOD 0x1f -#define REG_0x64_Z2MOD 0xff -#define REG_0x65_Z2MOD 0xff +static constexpr RegMask REG_0x63_Z2MOD = 0x1f; +static constexpr RegMask REG_0x64_Z2MOD = 0xff; +static constexpr RegMask REG_0x65_Z2MOD = 0xff; -#define REG_0x67_STEPSEL 0xc0 -#define REG_0x67_FULLSTEP 0x00 -#define REG_0x67_HALFSTEP 0x40 -#define REG_0x67_QUATERSTEP 0x80 -#define REG_0x67_MTRPWM 0x3f +static constexpr RegMask REG_0x67_STEPSEL = 0xc0; +static constexpr RegMask REG_0x67_FULLSTEP = 0x00; +static constexpr RegMask REG_0x67_HALFSTEP = 0x40; +static constexpr RegMask REG_0x67_QUATERSTEP = 0x80; +static constexpr RegMask REG_0x67_MTRPWM = 0x3f; -#define REG_0x68_FSTPSEL 0xc0 -#define REG_0x68_FULLSTEP 0x00 -#define REG_0x68_HALFSTEP 0x40 -#define REG_0x68_QUATERSTEP 0x80 -#define REG_0x68_FASTPWM 0x3f +static constexpr RegMask REG_0x68_FSTPSEL = 0xc0; +static constexpr RegMask REG_0x68_FULLSTEP = 0x00; +static constexpr RegMask REG_0x68_HALFSTEP = 0x40; +static constexpr RegMask REG_0x68_QUATERSTEP = 0x80; +static constexpr RegMask REG_0x68_FASTPWM = 0x3f; -#define REG_0x6B_MULTFILM 0x80 -#define REG_0x6B_GPOM13 0x40 -#define REG_0x6B_GPOM12 0x20 -#define REG_0x6B_GPOM11 0x10 -#define REG_0x6B_GPO18 0x02 -#define REG_0x6B_GPO17 0x01 +static constexpr RegMask REG_0x6B_MULTFILM = 0x80; +static constexpr RegMask REG_0x6B_GPOM13 = 0x40; +static constexpr RegMask REG_0x6B_GPOM12 = 0x20; +static constexpr RegMask REG_0x6B_GPOM11 = 0x10; +static constexpr RegMask REG_0x6B_GPO18 = 0x02; +static constexpr RegMask REG_0x6B_GPO17 = 0x01; -#define REG_0x6B 0x6b +static constexpr RegAddr REG_0x6B = 0x6b; -#define REG_0x6C 0x6c -#define REG_0x6C_GPIOH 0xff -#define REG_0x6C_GPIOL 0xff +static constexpr RegAddr REG_0x6C = 0x6c; +static constexpr RegMask REG_0x6C_GPIOH = 0xff; +static constexpr RegMask REG_0x6C_GPIOL = 0xff; -#define REG_0x6D 0x6d -#define REG_0x6E 0x6e -#define REG_0x6F 0x6f +static constexpr RegAddr REG_0x6D = 0x6d; +static constexpr RegAddr REG_0x6E = 0x6e; +static constexpr RegAddr REG_0x6F = 0x6f; -#define REG_0x87_LEDADD 0x04 +static constexpr RegMask REG_0x87_LEDADD = 0x04; } // namespace gl841 } // namespace genesys diff --git a/backend/genesys/gl843_registers.h b/backend/genesys/gl843_registers.h index befe6a9ed..8ecb0fc04 100644 --- a/backend/genesys/gl843_registers.h +++ b/backend/genesys/gl843_registers.h @@ -44,332 +44,337 @@ #ifndef BACKEND_GENESYS_GL843_REGISTERS_H #define BACKEND_GENESYS_GL843_REGISTERS_H +#include + namespace genesys { namespace gl843 { -#define REG_0x01 0x01 -#define REG_0x01_CISSET 0x80 -#define REG_0x01_DOGENB 0x40 -#define REG_0x01_DVDSET 0x20 -#define REG_0x01_STAGGER 0x10 -#define REG_0x01_COMPENB 0x08 -#define REG_0x01_TRUEGRAY 0x04 -#define REG_0x01_SHDAREA 0x02 -#define REG_0x01_SCAN 0x01 +using RegAddr = std::uint16_t; +using RegMask = std::uint8_t; +using RegShift = unsigned; -#define REG_0x02 0x02 -#define REG_0x02_NOTHOME 0x80 -#define REG_0x02_ACDCDIS 0x40 -#define REG_0x02_AGOHOME 0x20 -#define REG_0x02_MTRPWR 0x10 -#define REG_0x02_FASTFED 0x08 -#define REG_0x02_MTRREV 0x04 -#define REG_0x02_HOMENEG 0x02 -#define REG_0x02_LONGCURV 0x01 +static constexpr RegAddr REG_0x01 = 0x01; +static constexpr RegMask REG_0x01_CISSET = 0x80; +static constexpr RegMask REG_0x01_DOGENB = 0x40; +static constexpr RegMask REG_0x01_DVDSET = 0x20; +static constexpr RegMask REG_0x01_STAGGER = 0x10; +static constexpr RegMask REG_0x01_COMPENB = 0x08; +static constexpr RegMask REG_0x01_TRUEGRAY = 0x04; +static constexpr RegMask REG_0x01_SHDAREA = 0x02; +static constexpr RegMask REG_0x01_SCAN = 0x01; -#define REG_0x03 0x03 -#define REG_0x03_LAMPDOG 0x80 -#define REG_0x03_AVEENB 0x40 -#define REG_0x03_XPASEL 0x20 -#define REG_0x03_LAMPPWR 0x10 -#define REG_0x03_LAMPTIM 0x0f +static constexpr RegAddr REG_0x02 = 0x02; +static constexpr RegMask REG_0x02_NOTHOME = 0x80; +static constexpr RegMask REG_0x02_ACDCDIS = 0x40; +static constexpr RegMask REG_0x02_AGOHOME = 0x20; +static constexpr RegMask REG_0x02_MTRPWR = 0x10; +static constexpr RegMask REG_0x02_FASTFED = 0x08; +static constexpr RegMask REG_0x02_MTRREV = 0x04; +static constexpr RegMask REG_0x02_HOMENEG = 0x02; +static constexpr RegMask REG_0x02_LONGCURV = 0x01; -#define REG_0x04 0x04 -#define REG_0x04_LINEART 0x80 -#define REG_0x04_BITSET 0x40 -#define REG_0x04_AFEMOD 0x30 -#define REG_0x04_FILTER 0x0c -#define REG_0x04_FESET 0x03 +static constexpr RegAddr REG_0x03 = 0x03; +static constexpr RegMask REG_0x03_LAMPDOG = 0x80; +static constexpr RegMask REG_0x03_AVEENB = 0x40; +static constexpr RegMask REG_0x03_XPASEL = 0x20; +static constexpr RegMask REG_0x03_LAMPPWR = 0x10; +static constexpr RegMask REG_0x03_LAMPTIM = 0x0f; -#define REG_0x04S_AFEMOD 4 +static constexpr RegAddr REG_0x04 = 0x04; +static constexpr RegMask REG_0x04_LINEART = 0x80; +static constexpr RegMask REG_0x04_BITSET = 0x40; +static constexpr RegMask REG_0x04_AFEMOD = 0x30; +static constexpr RegMask REG_0x04_FILTER = 0x0c; +static constexpr RegMask REG_0x04_FESET = 0x03; -#define REG_0x05 0x05 -#define REG_0x05_DPIHW 0xc0 -#define REG_0x05_DPIHW_600 0x00 -#define REG_0x05_DPIHW_1200 0x40 -#define REG_0x05_DPIHW_2400 0x80 -#define REG_0x05_DPIHW_4800 0xc0 -#define REG_0x05_MTLLAMP 0x30 -#define REG_0x05_GMMENB 0x08 -#define REG_0x05_MTLBASE 0x03 +static constexpr RegShift REG_0x04S_AFEMOD = 4; -#define REG_0x06 0x06 -#define REG_0x06_SCANMOD 0xe0 -#define REG_0x06S_SCANMOD 5 -#define REG_0x06_PWRBIT 0x10 -#define REG_0x06_GAIN4 0x08 -#define REG_0x06_OPTEST 0x07 +static constexpr RegAddr REG_0x05 = 0x05; +static constexpr RegMask REG_0x05_DPIHW = 0xc0; +static constexpr RegMask REG_0x05_DPIHW_600 = 0x00; +static constexpr RegMask REG_0x05_DPIHW_1200 = 0x40; +static constexpr RegMask REG_0x05_DPIHW_2400 = 0x80; +static constexpr RegMask REG_0x05_DPIHW_4800 = 0xc0; +static constexpr RegMask REG_0x05_MTLLAMP = 0x30; +static constexpr RegMask REG_0x05_GMMENB = 0x08; +static constexpr RegMask REG_0x05_MTLBASE = 0x03; -#define REG_0x07_LAMPSIM 0x80 +static constexpr RegAddr REG_0x06 = 0x06; +static constexpr RegMask REG_0x06_SCANMOD = 0xe0; +static constexpr RegShift REG_0x06S_SCANMOD = 5; +static constexpr RegMask REG_0x06_PWRBIT = 0x10; +static constexpr RegMask REG_0x06_GAIN4 = 0x08; +static constexpr RegMask REG_0x06_OPTEST = 0x07; -#define REG_0x08_DECFLAG 0x40 -#define REG_0x08_GMMFFR 0x20 -#define REG_0x08_GMMFFG 0x10 -#define REG_0x08_GMMFFB 0x08 -#define REG_0x08_GMMZR 0x04 -#define REG_0x08_GMMZG 0x02 -#define REG_0x08_GMMZB 0x01 +static constexpr RegMask REG_0x07_LAMPSIM = 0x80; -#define REG_0x09_MCNTSET 0xc0 -#define REG_0x09_EVEN1ST 0x20 -#define REG_0x09_BLINE1ST 0x10 -#define REG_0x09_BACKSCAN 0x08 -#define REG_0x09_ENHANCE 0x04 -#define REG_0x09_SHORTTG 0x02 -#define REG_0x09_NWAIT 0x01 +static constexpr RegMask REG_0x08_DECFLAG = 0x40; +static constexpr RegMask REG_0x08_GMMFFR = 0x20; +static constexpr RegMask REG_0x08_GMMFFG = 0x10; +static constexpr RegMask REG_0x08_GMMFFB = 0x08; +static constexpr RegMask REG_0x08_GMMZR = 0x04; +static constexpr RegMask REG_0x08_GMMZG = 0x02; +static constexpr RegMask REG_0x08_GMMZB = 0x01; -#define REG_0x09S_MCNTSET 6 -#define REG_0x09S_CLKSET 4 +static constexpr RegMask REG_0x09_MCNTSET = 0xc0; +static constexpr RegMask REG_0x09_EVEN1ST = 0x20; +static constexpr RegMask REG_0x09_BLINE1ST = 0x10; +static constexpr RegMask REG_0x09_BACKSCAN = 0x08; +static constexpr RegMask REG_0x09_ENHANCE = 0x04; +static constexpr RegMask REG_0x09_SHORTTG = 0x02; +static constexpr RegMask REG_0x09_NWAIT = 0x01; -#define REG_0x0B 0x0b -#define REG_0x0B_DRAMSEL 0x07 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_RFHDIS 0x10 -#define REG_0x0B_CLKSET 0xe0 -#define REG_0x0B_24MHZ 0x00 -#define REG_0x0B_30MHZ 0x20 -#define REG_0x0B_40MHZ 0x40 -#define REG_0x0B_48MHZ 0x60 -#define REG_0x0B_60MHZ 0x80 +static constexpr RegShift REG_0x09S_MCNTSET = 6; +static constexpr RegShift REG_0x09S_CLKSET = 4; -#define REG_0x0D 0x0d -#define REG_0x0D_JAMPCMD 0x80 -#define REG_0x0D_DOCCMD 0x40 -#define REG_0x0D_CCDCMD 0x20 -#define REG_0x0D_FULLSTP 0x10 -#define REG_0x0D_SEND 0x08 -#define REG_0x0D_CLRMCNT 0x04 -#define REG_0x0D_CLRDOCJM 0x02 -#define REG_0x0D_CLRLNCNT 0x01 +static constexpr RegAddr REG_0x0B = 0x0b; +static constexpr RegMask REG_0x0B_DRAMSEL = 0x07; +static constexpr RegMask REG_0x0B_ENBDRAM = 0x08; +static constexpr RegMask REG_0x0B_RFHDIS = 0x10; +static constexpr RegMask REG_0x0B_CLKSET = 0xe0; +static constexpr RegMask REG_0x0B_24MHZ = 0x00; +static constexpr RegMask REG_0x0B_30MHZ = 0x20; +static constexpr RegMask REG_0x0B_40MHZ = 0x40; +static constexpr RegMask REG_0x0B_48MHZ = 0x60; +static constexpr RegMask REG_0x0B_60MHZ = 0x80; -#define REG_0x0F 0x0f +static constexpr RegAddr REG_0x0D = 0x0d; +static constexpr RegMask REG_0x0D_JAMPCMD = 0x80; +static constexpr RegMask REG_0x0D_DOCCMD = 0x40; +static constexpr RegMask REG_0x0D_CCDCMD = 0x20; +static constexpr RegMask REG_0x0D_FULLSTP = 0x10; +static constexpr RegMask REG_0x0D_SEND = 0x08; +static constexpr RegMask REG_0x0D_CLRMCNT = 0x04; +static constexpr RegMask REG_0x0D_CLRDOCJM = 0x02; +static constexpr RegMask REG_0x0D_CLRLNCNT = 0x01; -#define REG_EXPR 0x10 -#define REG_EXPG 0x12 -#define REG_EXPB 0x14 +static constexpr RegAddr REG_0x0F = 0x0f; -#define REG_0x16_CTRLHI 0x80 -#define REG_0x16_TOSHIBA 0x40 -#define REG_0x16_TGINV 0x20 -#define REG_0x16_CK1INV 0x10 -#define REG_0x16_CK2INV 0x08 -#define REG_0x16_CTRLINV 0x04 -#define REG_0x16_CKDIS 0x02 -#define REG_0x16_CTRLDIS 0x01 +static constexpr RegAddr REG_EXPR = 0x10; +static constexpr RegAddr REG_EXPG = 0x12; +static constexpr RegAddr REG_EXPB = 0x14; -#define REG_0x17_TGMODE 0xc0 -#define REG_0x17_TGMODE_NO_DUMMY 0x00 -#define REG_0x17_TGMODE_REF 0x40 -#define REG_0x17_TGMODE_XPA 0x80 -#define REG_0x17_TGW 0x3f -#define REG_0x17S_TGW 0 +static constexpr RegMask REG_0x16_CTRLHI = 0x80; +static constexpr RegMask REG_0x16_TOSHIBA = 0x40; +static constexpr RegMask REG_0x16_TGINV = 0x20; +static constexpr RegMask REG_0x16_CK1INV = 0x10; +static constexpr RegMask REG_0x16_CK2INV = 0x08; +static constexpr RegMask REG_0x16_CTRLINV = 0x04; +static constexpr RegMask REG_0x16_CKDIS = 0x02; +static constexpr RegMask REG_0x16_CTRLDIS = 0x01; -#define REG_0x18 0x18 -#define REG_0x18_CNSET 0x80 -#define REG_0x18_DCKSEL 0x60 -#define REG_0x18_CKTOGGLE 0x10 -#define REG_0x18_CKDELAY 0x0c -#define REG_0x18_CKSEL 0x03 +static constexpr RegMask REG_0x17_TGMODE = 0xc0; +static constexpr RegMask REG_0x17_TGMODE_NO_DUMMY = 0x00; +static constexpr RegMask REG_0x17_TGMODE_REF = 0x40; +static constexpr RegMask REG_0x17_TGMODE_XPA = 0x80; +static constexpr RegMask REG_0x17_TGW = 0x3f; +static constexpr RegShift REG_0x17S_TGW = 0; -#define REG_EXPDMY 0x19 +static constexpr RegAddr REG_0x18 = 0x18; +static constexpr RegMask REG_0x18_CNSET = 0x80; +static constexpr RegMask REG_0x18_DCKSEL = 0x60; +static constexpr RegMask REG_0x18_CKTOGGLE = 0x10; +static constexpr RegMask REG_0x18_CKDELAY = 0x0c; +static constexpr RegMask REG_0x18_CKSEL = 0x03; -#define REG_0x1A_TGLSW2 0x80 -#define REG_0x1A_TGLSW1 0x40 -#define REG_0x1A_MANUAL3 0x02 -#define REG_0x1A_MANUAL1 0x01 -#define REG_0x1A_CK4INV 0x08 -#define REG_0x1A_CK3INV 0x04 -#define REG_0x1A_LINECLP 0x02 +static constexpr RegAddr REG_EXPDMY = 0x19; -#define REG_0x1C 0x1c -#define REG_0x1C_TGTIME 0x07 +static constexpr RegMask REG_0x1A_TGLSW2 = 0x80; +static constexpr RegMask REG_0x1A_TGLSW1 = 0x40; +static constexpr RegMask REG_0x1A_MANUAL3 = 0x02; +static constexpr RegMask REG_0x1A_MANUAL1 = 0x01; +static constexpr RegMask REG_0x1A_CK4INV = 0x08; +static constexpr RegMask REG_0x1A_CK3INV = 0x04; +static constexpr RegMask REG_0x1A_LINECLP = 0x02; -#define REG_0x1D_CK4LOW 0x80 -#define REG_0x1D_CK3LOW 0x40 -#define REG_0x1D_CK1LOW 0x20 -#define REG_0x1D_TGSHLD 0x1f -#define REG_0x1DS_TGSHLD 0 +static constexpr RegAddr REG_0x1C = 0x1c; +static constexpr RegMask REG_0x1C_TGTIME = 0x07; + +static constexpr RegMask REG_0x1D_CK4LOW = 0x80; +static constexpr RegMask REG_0x1D_CK3LOW = 0x40; +static constexpr RegMask REG_0x1D_CK1LOW = 0x20; +static constexpr RegMask REG_0x1D_TGSHLD = 0x1f; +static constexpr RegShift REG_0x1DS_TGSHLD = 0; -#define REG_0x1E 0x1e -#define REG_0x1E_WDTIME 0xf0 -#define REG_0x1ES_WDTIME 4 -#define REG_0x1E_LINESEL 0x0f -#define REG_0x1ES_LINESEL 0 +static constexpr RegAddr REG_0x1E = 0x1e; +static constexpr RegMask REG_0x1E_WDTIME = 0xf0; +static constexpr RegShift REG_0x1ES_WDTIME = 4; +static constexpr RegMask REG_0x1E_LINESEL = 0x0f; +static constexpr RegShift REG_0x1ES_LINESEL = 0; -#define REG_0x21 0x21 -#define REG_STEPNO 0x21 -#define REG_FWDSTEP 0x22 -#define REG_BWDSTEP 0x23 -#define REG_FASTNO 0x24 -#define REG_LINCNT 0x25 +static constexpr RegAddr REG_0x21 = 0x21; +static constexpr RegAddr REG_STEPNO = 0x21; +static constexpr RegAddr REG_FWDSTEP = 0x22; +static constexpr RegAddr REG_BWDSTEP = 0x23; +static constexpr RegAddr REG_FASTNO = 0x24; +static constexpr RegAddr REG_LINCNT = 0x25; -#define REG_0x29 0x29 -#define REG_0x2A 0x2a -#define REG_0x2B 0x2b -#define REG_DPISET 0x2c -#define REG_0x2E 0x2e -#define REG_0x2F 0x2f +static constexpr RegAddr REG_0x29 = 0x29; +static constexpr RegAddr REG_0x2A = 0x2a; +static constexpr RegAddr REG_0x2B = 0x2b; +static constexpr RegAddr REG_DPISET = 0x2c; +static constexpr RegAddr REG_0x2E = 0x2e; +static constexpr RegAddr REG_0x2F = 0x2f; -#define REG_STRPIXEL 0x30 -#define REG_ENDPIXEL 0x32 -#define REG_DUMMY 0x34 -#define REG_MAXWD 0x35 -#define REG_LPERIOD 0x38 -#define REG_FEEDL 0x3d +static constexpr RegAddr REG_STRPIXEL = 0x30; +static constexpr RegAddr REG_ENDPIXEL = 0x32; +static constexpr RegAddr REG_DUMMY = 0x34; +static constexpr RegAddr REG_MAXWD = 0x35; +static constexpr RegAddr REG_LPERIOD = 0x38; +static constexpr RegAddr REG_FEEDL = 0x3d; -#define REG_0x40 0x40 -#define REG_0x40_DOCSNR 0x80 -#define REG_0x40_ADFSNR 0x40 -#define REG_0x40_COVERSNR 0x20 -#define REG_0x40_CHKVER 0x10 -#define REG_0x40_DOCJAM 0x08 -#define REG_0x40_HISPDFLG 0x04 -#define REG_0x40_MOTMFLG 0x02 -#define REG_0x40_DATAENB 0x01 +static constexpr RegAddr REG_0x40 = 0x40; +static constexpr RegMask REG_0x40_DOCSNR = 0x80; +static constexpr RegMask REG_0x40_ADFSNR = 0x40; +static constexpr RegMask REG_0x40_COVERSNR = 0x20; +static constexpr RegMask REG_0x40_CHKVER = 0x10; +static constexpr RegMask REG_0x40_DOCJAM = 0x08; +static constexpr RegMask REG_0x40_HISPDFLG = 0x04; +static constexpr RegMask REG_0x40_MOTMFLG = 0x02; +static constexpr RegMask REG_0x40_DATAENB = 0x01; -#define REG_0x41_PWRBIT 0x80 -#define REG_0x41_BUFEMPTY 0x40 -#define REG_0x41_FEEDFSH 0x20 -#define REG_0x41_SCANFSH 0x10 -#define REG_0x41_HOMESNR 0x08 -#define REG_0x41_LAMPSTS 0x04 -#define REG_0x41_FEBUSY 0x02 -#define REG_0x41_MOTORENB 0x01 +static constexpr RegMask REG_0x41_PWRBIT = 0x80; +static constexpr RegMask REG_0x41_BUFEMPTY = 0x40; +static constexpr RegMask REG_0x41_FEEDFSH = 0x20; +static constexpr RegMask REG_0x41_SCANFSH = 0x10; +static constexpr RegMask REG_0x41_HOMESNR = 0x08; +static constexpr RegMask REG_0x41_LAMPSTS = 0x04; +static constexpr RegMask REG_0x41_FEBUSY = 0x02; +static constexpr RegMask REG_0x41_MOTORENB = 0x01; -#define REG_0x58_VSMP 0xf8 -#define REG_0x58S_VSMP 3 -#define REG_0x58_VSMPW 0x07 -#define REG_0x58S_VSMPW 0 +static constexpr RegMask REG_0x58_VSMP = 0xf8; +static constexpr RegShift REG_0x58S_VSMP = 3; +static constexpr RegMask REG_0x58_VSMPW = 0x07; +static constexpr RegShift REG_0x58S_VSMPW = 0; -#define REG_0x59_BSMP 0xf8 -#define REG_0x59S_BSMP 3 -#define REG_0x59_BSMPW 0x07 -#define REG_0x59S_BSMPW 0 +static constexpr RegMask REG_0x59_BSMP = 0xf8; +static constexpr RegShift REG_0x59S_BSMP = 3; +static constexpr RegMask REG_0x59_BSMPW = 0x07; +static constexpr RegShift REG_0x59S_BSMPW = 0; -#define REG_0x5A_ADCLKINV 0x80 -#define REG_0x5A_RLCSEL 0x40 -#define REG_0x5A_CDSREF 0x30 -#define REG_0x5AS_CDSREF 4 -#define REG_0x5A_RLC 0x0f -#define REG_0x5AS_RLC 0 +static constexpr RegMask REG_0x5A_ADCLKINV = 0x80; +static constexpr RegMask REG_0x5A_RLCSEL = 0x40; +static constexpr RegMask REG_0x5A_CDSREF = 0x30; +static constexpr RegShift REG_0x5AS_CDSREF = 4; +static constexpr RegMask REG_0x5A_RLC = 0x0f; +static constexpr RegShift REG_0x5AS_RLC = 0; -#define REG_0x5E 0x5e -#define REG_0x5E_DECSEL 0xe0 -#define REG_0x5ES_DECSEL 5 -#define REG_0x5E_STOPTIM 0x1f -#define REG_0x5ES_STOPTIM 0 +static constexpr RegAddr REG_0x5E = 0x5e; +static constexpr RegMask REG_0x5E_DECSEL = 0xe0; +static constexpr RegShift REG_0x5ES_DECSEL = 5; +static constexpr RegMask REG_0x5E_STOPTIM = 0x1f; +static constexpr RegShift REG_0x5ES_STOPTIM = 0; -#define REG_FMOVDEC 0x5f +static constexpr RegAddr REG_FMOVDEC = 0x5f; -#define REG_0x60 0x60 -#define REG_0x60_Z1MOD 0x1f -#define REG_0x61 0x61 -#define REG_0x61_Z1MOD 0xff -#define REG_0x62 0x62 -#define REG_0x62_Z1MOD 0xff +static constexpr RegAddr REG_0x60 = 0x60; +static constexpr RegMask REG_0x60_Z1MOD = 0x1f; +static constexpr RegAddr REG_0x61 = 0x61; +static constexpr RegMask REG_0x61_Z1MOD = 0xff; +static constexpr RegAddr REG_0x62 = 0x62; +static constexpr RegMask REG_0x62_Z1MOD = 0xff; -#define REG_0x63 0x63 -#define REG_0x63_Z2MOD 0x1f -#define REG_0x64 0x64 -#define REG_0x64_Z2MOD 0xff -#define REG_0x65 0x65 -#define REG_0x65_Z2MOD 0xff +static constexpr RegAddr REG_0x63 = 0x63; +static constexpr RegMask REG_0x63_Z2MOD = 0x1f; +static constexpr RegAddr REG_0x64 = 0x64; +static constexpr RegMask REG_0x64_Z2MOD = 0xff; +static constexpr RegAddr REG_0x65 = 0x65; +static constexpr RegMask REG_0x65_Z2MOD = 0xff; -#define REG_0x67 0x67 +static constexpr RegAddr REG_0x67 = 0x67; -#define REG_0x68 0x68 +static constexpr RegAddr REG_0x68 = 0x68; -#define REG_0x67S_STEPSEL 6 -#define REG_0x67_STEPSEL 0xc0 -#define REG_0x67_FULLSTEP 0x00 -#define REG_0x67_HALFSTEP 0x20 -#define REG_0x67_EIGHTHSTEP 0x60 -#define REG_0x67_16THSTEP 0x80 +static constexpr RegShift REG_0x67S_STEPSEL = 6; +static constexpr RegMask REG_0x67_STEPSEL = 0xc0; +static constexpr RegMask REG_0x67_FULLSTEP = 0x00; +static constexpr RegMask REG_0x67_HALFSTEP = 0x20; +static constexpr RegMask REG_0x67_EIGHTHSTEP = 0x60; +static constexpr RegMask REG_0x67_16THSTEP = 0x80; -#define REG_0x68S_FSTPSEL 6 -#define REG_0x68_FSTPSEL 0xc0 -#define REG_0x68_FULLSTEP 0x00 -#define REG_0x68_HALFSTEP 0x20 -#define REG_0x68_EIGHTHSTEP 0x60 -#define REG_0x68_16THSTEP 0x80 +static constexpr RegShift REG_0x68S_FSTPSEL = 6; +static constexpr RegMask REG_0x68_FSTPSEL = 0xc0; +static constexpr RegMask REG_0x68_FULLSTEP = 0x00; +static constexpr RegMask REG_0x68_HALFSTEP = 0x20; +static constexpr RegMask REG_0x68_EIGHTHSTEP = 0x60; +static constexpr RegMask REG_0x68_16THSTEP = 0x80; -#define REG_FSHDEC 0x69 -#define REG_FMOVNO 0x6a +static constexpr RegAddr REG_FSHDEC = 0x69; +static constexpr RegAddr REG_FMOVNO = 0x6a; -#define REG_0x6B 0x6b -#define REG_0x6B_MULTFILM 0x80 -#define REG_0x6B_GPOM13 0x40 -#define REG_0x6B_GPOM12 0x20 -#define REG_0x6B_GPOM11 0x10 -#define REG_0x6B_GPOCK4 0x08 -#define REG_0x6B_GPOCP 0x04 -#define REG_0x6B_GPOLEDB 0x02 -#define REG_0x6B_GPOADF 0x01 +static constexpr RegAddr REG_0x6B = 0x6b; +static constexpr RegMask REG_0x6B_MULTFILM = 0x80; +static constexpr RegMask REG_0x6B_GPOM13 = 0x40; +static constexpr RegMask REG_0x6B_GPOM12 = 0x20; +static constexpr RegMask REG_0x6B_GPOM11 = 0x10; +static constexpr RegMask REG_0x6B_GPOCK4 = 0x08; +static constexpr RegMask REG_0x6B_GPOCP = 0x04; +static constexpr RegMask REG_0x6B_GPOLEDB = 0x02; +static constexpr RegMask REG_0x6B_GPOADF = 0x01; -#define REG_0x6C 0x6c -#define REG_0x6C_GPIO16 0x80 -#define REG_0x6C_GPIO15 0x40 -#define REG_0x6C_GPIO14 0x20 -#define REG_0x6C_GPIO13 0x10 -#define REG_0x6C_GPIO12 0x08 -#define REG_0x6C_GPIO11 0x04 -#define REG_0x6C_GPIO10 0x02 -#define REG_0x6C_GPIO9 0x01 -#define REG_0x6C_GPIOH 0xff -#define REG_0x6C_GPIOL 0xff +static constexpr RegAddr REG_0x6C = 0x6c; +static constexpr RegMask REG_0x6C_GPIO16 = 0x80; +static constexpr RegMask REG_0x6C_GPIO15 = 0x40; +static constexpr RegMask REG_0x6C_GPIO14 = 0x20; +static constexpr RegMask REG_0x6C_GPIO13 = 0x10; +static constexpr RegMask REG_0x6C_GPIO12 = 0x08; +static constexpr RegMask REG_0x6C_GPIO11 = 0x04; +static constexpr RegMask REG_0x6C_GPIO10 = 0x02; +static constexpr RegMask REG_0x6C_GPIO9 = 0x01; +static constexpr RegMask REG_0x6C_GPIOH = 0xff; +static constexpr RegMask REG_0x6C_GPIOL = 0xff; -#define REG_Z1MOD 0x60 -#define REG_Z2MOD 0x63 +static constexpr RegAddr REG_Z1MOD = 0x60; +static constexpr RegAddr REG_Z2MOD = 0x63; -#define REG_0x6D 0x6d -#define REG_0x6E 0x6e -#define REG_0x6F 0x6f +static constexpr RegAddr REG_0x6D = 0x6d; +static constexpr RegAddr REG_0x6E = 0x6e; +static constexpr RegAddr REG_0x6F = 0x6f; -#define REG_CK1MAP 0x74 -#define REG_CK3MAP 0x77 -#define REG_CK4MAP 0x7a +static constexpr RegAddr REG_CK1MAP = 0x74; +static constexpr RegAddr REG_CK3MAP = 0x77; +static constexpr RegAddr REG_CK4MAP = 0x7a; -#define REG_0x7E 0x7e +static constexpr RegAddr REG_0x7E = 0x7e; -#define REG_0x9D 0x9d -#define REG_0x9DS_STEPTIM 2 +static constexpr RegAddr REG_0x9D = 0x9d; +static constexpr RegShift REG_0x9DS_STEPTIM = 2; -#define REG_0x87_LEDADD 0x04 +static constexpr RegMask REG_0x87_LEDADD = 0x04; -#define REG_0xA6 0xa6 -#define REG_0xA6_GPIO24 0x80 -#define REG_0xA6_GPIO23 0x40 -#define REG_0xA6_GPIO22 0x20 -#define REG_0xA6_GPIO21 0x10 -#define REG_0xA6_GPIO20 0x08 -#define REG_0xA6_GPIO19 0x04 -#define REG_0xA6_GPIO18 0x02 -#define REG_0xA6_GPIO17 0x01 -#define REG_0xA7 0xa7 -#define REG_0xA7_GPOE24 0x80 -#define REG_0xA7_GPOE23 0x40 -#define REG_0xA7_GPOE22 0x20 -#define REG_0xA7_GPOE21 0x10 -#define REG_0xA7_GPOE20 0x08 -#define REG_0xA7_GPOE19 0x04 -#define REG_0xA7_GPOE18 0x02 -#define REG_0xA7_GPOE17 0x01 -#define REG_0xA8 0xa8 -#define REG_0xA8_GPOE27 0x20 -#define REG_0xA8_GPOE26 0x10 -#define REG_0xA8_GPOE25 0x08 -#define REG_0xA8_GPO27 0x04 -#define REG_0xA8_GPO26 0x02 -#define REG_0xA8_GPO25 0x01 -#define REG_0xA9 0xa9 -#define REG_0xA9_GPO33 0x20 -#define REG_0xA9_GPO32 0x10 -#define REG_0xA9_GPO31 0x08 -#define REG_0xA9_GPO30 0x04 -#define REG_0xA9_GPO29 0x02 -#define REG_0xA9_GPO28 0x01 +static constexpr RegAddr REG_0xA6 = 0xa6; +static constexpr RegMask REG_0xA6_GPIO24 = 0x80; +static constexpr RegMask REG_0xA6_GPIO23 = 0x40; +static constexpr RegMask REG_0xA6_GPIO22 = 0x20; +static constexpr RegMask REG_0xA6_GPIO21 = 0x10; +static constexpr RegMask REG_0xA6_GPIO20 = 0x08; +static constexpr RegMask REG_0xA6_GPIO19 = 0x04; +static constexpr RegMask REG_0xA6_GPIO18 = 0x02; +static constexpr RegMask REG_0xA6_GPIO17 = 0x01; +static constexpr RegAddr REG_0xA7 = 0xa7; +static constexpr RegMask REG_0xA7_GPOE24 = 0x80; +static constexpr RegMask REG_0xA7_GPOE23 = 0x40; +static constexpr RegMask REG_0xA7_GPOE22 = 0x20; +static constexpr RegMask REG_0xA7_GPOE21 = 0x10; +static constexpr RegMask REG_0xA7_GPOE20 = 0x08; +static constexpr RegMask REG_0xA7_GPOE19 = 0x04; +static constexpr RegMask REG_0xA7_GPOE18 = 0x02; +static constexpr RegMask REG_0xA7_GPOE17 = 0x01; +static constexpr RegAddr REG_0xA8 = 0xa8; +static constexpr RegMask REG_0xA8_GPOE27 = 0x20; +static constexpr RegMask REG_0xA8_GPOE26 = 0x10; +static constexpr RegMask REG_0xA8_GPOE25 = 0x08; +static constexpr RegMask REG_0xA8_GPO27 = 0x04; +static constexpr RegMask REG_0xA8_GPO26 = 0x02; +static constexpr RegMask REG_0xA8_GPO25 = 0x01; +static constexpr RegAddr REG_0xA9 = 0xa9; +static constexpr RegMask REG_0xA9_GPO33 = 0x20; +static constexpr RegMask REG_0xA9_GPO32 = 0x10; +static constexpr RegMask REG_0xA9_GPO31 = 0x08; +static constexpr RegMask REG_0xA9_GPO30 = 0x04; +static constexpr RegMask REG_0xA9_GPO29 = 0x02; +static constexpr RegMask REG_0xA9_GPO28 = 0x01; } // namespace gl843 } // namespace genesys diff --git a/backend/genesys/gl846_registers.h b/backend/genesys/gl846_registers.h index cd98cab9a..29efdeeeb 100644 --- a/backend/genesys/gl846_registers.h +++ b/backend/genesys/gl846_registers.h @@ -44,300 +44,305 @@ #ifndef BACKEND_GENESYS_GL846_REGISTERS_H #define BACKEND_GENESYS_GL846_REGISTERS_H +#include + namespace genesys { namespace gl846 { -#define REG_0x01 0x01 -#define REG_0x01_CISSET 0x80 -#define REG_0x01_DOGENB 0x40 -#define REG_0x01_DVDSET 0x20 -#define REG_0x01_STAGGER 0x10 -#define REG_0x01_COMPENB 0x08 -#define REG_0x01_TRUEGRAY 0x04 -#define REG_0x01_SHDAREA 0x02 -#define REG_0x01_SCAN 0x01 +using RegAddr = std::uint16_t; +using RegMask = std::uint8_t; +using RegShift = unsigned; -#define REG_0x02 0x02 -#define REG_0x02_NOTHOME 0x80 -#define REG_0x02_ACDCDIS 0x40 -#define REG_0x02_AGOHOME 0x20 -#define REG_0x02_MTRPWR 0x10 -#define REG_0x02_FASTFED 0x08 -#define REG_0x02_MTRREV 0x04 -#define REG_0x02_HOMENEG 0x02 -#define REG_0x02_LONGCURV 0x01 +static constexpr RegAddr REG_0x01 = 0x01; +static constexpr RegMask REG_0x01_CISSET = 0x80; +static constexpr RegMask REG_0x01_DOGENB = 0x40; +static constexpr RegMask REG_0x01_DVDSET = 0x20; +static constexpr RegMask REG_0x01_STAGGER = 0x10; +static constexpr RegMask REG_0x01_COMPENB = 0x08; +static constexpr RegMask REG_0x01_TRUEGRAY = 0x04; +static constexpr RegMask REG_0x01_SHDAREA = 0x02; +static constexpr RegMask REG_0x01_SCAN = 0x01; -#define REG_0x03 0x03 -#define REG_0x03_LAMPDOG 0x80 -#define REG_0x03_AVEENB 0x40 -#define REG_0x03_XPASEL 0x20 -#define REG_0x03_LAMPPWR 0x10 -#define REG_0x03_LAMPTIM 0x0f +static constexpr RegAddr REG_0x02 = 0x02; +static constexpr RegMask REG_0x02_NOTHOME = 0x80; +static constexpr RegMask REG_0x02_ACDCDIS = 0x40; +static constexpr RegMask REG_0x02_AGOHOME = 0x20; +static constexpr RegMask REG_0x02_MTRPWR = 0x10; +static constexpr RegMask REG_0x02_FASTFED = 0x08; +static constexpr RegMask REG_0x02_MTRREV = 0x04; +static constexpr RegMask REG_0x02_HOMENEG = 0x02; +static constexpr RegMask REG_0x02_LONGCURV = 0x01; -#define REG_0x04 0x04 -#define REG_0x04_LINEART 0x80 -#define REG_0x04_BITSET 0x40 -#define REG_0x04_AFEMOD 0x30 -#define REG_0x04_FILTER 0x0c -#define REG_0x04_FESET 0x03 +static constexpr RegAddr REG_0x03 = 0x03; +static constexpr RegMask REG_0x03_LAMPDOG = 0x80; +static constexpr RegMask REG_0x03_AVEENB = 0x40; +static constexpr RegMask REG_0x03_XPASEL = 0x20; +static constexpr RegMask REG_0x03_LAMPPWR = 0x10; +static constexpr RegMask REG_0x03_LAMPTIM = 0x0f; -#define REG_0x04S_AFEMOD 4 +static constexpr RegAddr REG_0x04 = 0x04; +static constexpr RegMask REG_0x04_LINEART = 0x80; +static constexpr RegMask REG_0x04_BITSET = 0x40; +static constexpr RegMask REG_0x04_AFEMOD = 0x30; +static constexpr RegMask REG_0x04_FILTER = 0x0c; +static constexpr RegMask REG_0x04_FESET = 0x03; -#define REG_0x05 0x05 -#define REG_0x05_DPIHW 0xc0 -#define REG_0x05_DPIHW_600 0x00 -#define REG_0x05_DPIHW_1200 0x40 -#define REG_0x05_DPIHW_2400 0x80 -#define REG_0x05_DPIHW_4800 0xc0 -#define REG_0x05_MTLLAMP 0x30 -#define REG_0x05_GMMENB 0x08 -#define REG_0x05_MTLBASE 0x03 +static constexpr RegShift REG_0x04S_AFEMOD = 4; -#define REG_0x06_SCANMOD 0xe0 -#define REG_0x06S_SCANMOD 5 -#define REG_0x06_PWRBIT 0x10 -#define REG_0x06_GAIN4 0x08 -#define REG_0x06_OPTEST 0x07 +static constexpr RegAddr REG_0x05 = 0x05; +static constexpr RegMask REG_0x05_DPIHW = 0xc0; +static constexpr RegMask REG_0x05_DPIHW_600 = 0x00; +static constexpr RegMask REG_0x05_DPIHW_1200 = 0x40; +static constexpr RegMask REG_0x05_DPIHW_2400 = 0x80; +static constexpr RegMask REG_0x05_DPIHW_4800 = 0xc0; +static constexpr RegMask REG_0x05_MTLLAMP = 0x30; +static constexpr RegMask REG_0x05_GMMENB = 0x08; +static constexpr RegMask REG_0x05_MTLBASE = 0x03; -#define REG_0x07_LAMPSIM 0x80 +static constexpr RegMask REG_0x06_SCANMOD = 0xe0; +static constexpr RegShift REG_0x06S_SCANMOD = 5; +static constexpr RegMask REG_0x06_PWRBIT = 0x10; +static constexpr RegMask REG_0x06_GAIN4 = 0x08; +static constexpr RegMask REG_0x06_OPTEST = 0x07; -#define REG_0x08_DRAM2X 0x80 -#define REG_0x08_MPENB 0x20 -#define REG_0x08_CIS_LINE 0x10 -#define REG_0x08_IR1ENB 0x08 -#define REG_0x08_IR2ENB 0x04 -#define REG_0x08_ENB24M 0x01 +static constexpr RegMask REG_0x07_LAMPSIM = 0x80; -#define REG_0x09_MCNTSET 0xc0 -#define REG_0x09_EVEN1ST 0x20 -#define REG_0x09_BLINE1ST 0x10 -#define REG_0x09_BACKSCAN 0x08 -#define REG_0x09_ENHANCE 0x04 -#define REG_0x09_SHORTTG 0x02 -#define REG_0x09_NWAIT 0x01 +static constexpr RegMask REG_0x08_DRAM2X = 0x80; +static constexpr RegMask REG_0x08_MPENB = 0x20; +static constexpr RegMask REG_0x08_CIS_LINE = 0x10; +static constexpr RegMask REG_0x08_IR1ENB = 0x08; +static constexpr RegMask REG_0x08_IR2ENB = 0x04; +static constexpr RegMask REG_0x08_ENB24M = 0x01; -#define REG_0x09S_MCNTSET 6 -#define REG_0x09S_CLKSET 4 +static constexpr RegMask REG_0x09_MCNTSET = 0xc0; +static constexpr RegMask REG_0x09_EVEN1ST = 0x20; +static constexpr RegMask REG_0x09_BLINE1ST = 0x10; +static constexpr RegMask REG_0x09_BACKSCAN = 0x08; +static constexpr RegMask REG_0x09_ENHANCE = 0x04; +static constexpr RegMask REG_0x09_SHORTTG = 0x02; +static constexpr RegMask REG_0x09_NWAIT = 0x01; + +static constexpr RegShift REG_0x09S_MCNTSET = 6; +static constexpr RegShift REG_0x09S_CLKSET = 4; -#define REG_0x0A_LPWMEN 0x10 +static constexpr RegAddr REG_0x0A_LPWMEN = 0x10; -#define REG_0x0B 0x0b -#define REG_0x0B_DRAMSEL 0x07 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_RFHDIS 0x10 -#define REG_0x0B_CLKSET 0xe0 -#define REG_0x0B_24MHZ 0x00 -#define REG_0x0B_30MHZ 0x20 -#define REG_0x0B_40MHZ 0x40 -#define REG_0x0B_48MHZ 0x60 -#define REG_0x0B_60MHZ 0x80 +static constexpr RegAddr REG_0x0B = 0x0b; +static constexpr RegMask REG_0x0B_DRAMSEL = 0x07; +static constexpr RegMask REG_0x0B_ENBDRAM = 0x08; +static constexpr RegMask REG_0x0B_RFHDIS = 0x10; +static constexpr RegMask REG_0x0B_CLKSET = 0xe0; +static constexpr RegMask REG_0x0B_24MHZ = 0x00; +static constexpr RegMask REG_0x0B_30MHZ = 0x20; +static constexpr RegMask REG_0x0B_40MHZ = 0x40; +static constexpr RegMask REG_0x0B_48MHZ = 0x60; +static constexpr RegMask REG_0x0B_60MHZ = 0x80; -#define REG_0x0C 0x0c -#define REG_0x0C_CCDLMT 0x0f +static constexpr RegAddr REG_0x0C = 0x0c; +static constexpr RegMask REG_0x0C_CCDLMT = 0x0f; -#define REG_0x0D 0x0d -#define REG_0x0D_SCSYNC 0x40 -#define REG_0x0D_CLRERR 0x20 -#define REG_0x0D_FULLSTP 0x10 -#define REG_0x0D_SEND 0x80 -#define REG_0x0D_CLRMCNT 0x04 -#define REG_0x0D_CLRDOCJM 0x02 -#define REG_0x0D_CLRLNCNT 0x01 +static constexpr RegAddr REG_0x0D = 0x0d; +static constexpr RegMask REG_0x0D_SCSYNC = 0x40; +static constexpr RegMask REG_0x0D_CLRERR = 0x20; +static constexpr RegMask REG_0x0D_FULLSTP = 0x10; +static constexpr RegMask REG_0x0D_SEND = 0x80; +static constexpr RegMask REG_0x0D_CLRMCNT = 0x04; +static constexpr RegMask REG_0x0D_CLRDOCJM = 0x02; +static constexpr RegMask REG_0x0D_CLRLNCNT = 0x01; -#define REG_0x0F 0x0f +static constexpr RegAddr REG_0x0F = 0x0f; -#define REG_0x16_CTRLHI 0x80 -#define REG_0x16_TOSHIBA 0x40 -#define REG_0x16_TGINV 0x20 -#define REG_0x16_CK1INV 0x10 -#define REG_0x16_CK2INV 0x08 -#define REG_0x16_CTRLINV 0x04 -#define REG_0x16_CKDIS 0x02 -#define REG_0x16_CTRLDIS 0x01 +static constexpr RegMask REG_0x16_CTRLHI = 0x80; +static constexpr RegMask REG_0x16_TOSHIBA = 0x40; +static constexpr RegMask REG_0x16_TGINV = 0x20; +static constexpr RegMask REG_0x16_CK1INV = 0x10; +static constexpr RegMask REG_0x16_CK2INV = 0x08; +static constexpr RegMask REG_0x16_CTRLINV = 0x04; +static constexpr RegMask REG_0x16_CKDIS = 0x02; +static constexpr RegMask REG_0x16_CTRLDIS = 0x01; -#define REG_0x17_TGMODE 0xc0 -#define REG_0x17_TGMODE_NO_DUMMY 0x00 -#define REG_0x17_TGMODE_REF 0x40 -#define REG_0x17_TGMODE_XPA 0x80 -#define REG_0x17_TGW 0x3f -#define REG_0x17S_TGW 0 +static constexpr RegMask REG_0x17_TGMODE = 0xc0; +static constexpr RegMask REG_0x17_TGMODE_NO_DUMMY = 0x00; +static constexpr RegMask REG_0x17_TGMODE_REF = 0x40; +static constexpr RegMask REG_0x17_TGMODE_XPA = 0x80; +static constexpr RegMask REG_0x17_TGW = 0x3f; +static constexpr RegAddr REG_0x17S_TGW = 0; -#define REG_0x18 0x18 -#define REG_0x18_CNSET 0x80 -#define REG_0x18_DCKSEL 0x60 -#define REG_0x18_CKTOGGLE 0x10 -#define REG_0x18_CKDELAY 0x0c -#define REG_0x18_CKSEL 0x03 +static constexpr RegAddr REG_0x18 = 0x18; +static constexpr RegMask REG_0x18_CNSET = 0x80; +static constexpr RegMask REG_0x18_DCKSEL = 0x60; +static constexpr RegMask REG_0x18_CKTOGGLE = 0x10; +static constexpr RegMask REG_0x18_CKDELAY = 0x0c; +static constexpr RegMask REG_0x18_CKSEL = 0x03; -#define REG_0x1A_SW2SET 0x80 -#define REG_0x1A_SW1SET 0x40 -#define REG_0x1A_MANUAL3 0x02 -#define REG_0x1A_MANUAL1 0x01 -#define REG_0x1A_CK4INV 0x08 -#define REG_0x1A_CK3INV 0x04 -#define REG_0x1A_LINECLP 0x02 +static constexpr RegMask REG_0x1A_SW2SET = 0x80; +static constexpr RegMask REG_0x1A_SW1SET = 0x40; +static constexpr RegMask REG_0x1A_MANUAL3 = 0x02; +static constexpr RegMask REG_0x1A_MANUAL1 = 0x01; +static constexpr RegMask REG_0x1A_CK4INV = 0x08; +static constexpr RegMask REG_0x1A_CK3INV = 0x04; +static constexpr RegMask REG_0x1A_LINECLP = 0x02; -#define REG_0x1C 0x1c -#define REG_0x1C_TGTIME 0x07 +static constexpr RegAddr REG_0x1C = 0x1c; +static constexpr RegMask REG_0x1C_TGTIME = 0x07; -#define REG_0x1D_CK4LOW 0x80 -#define REG_0x1D_CK3LOW 0x40 -#define REG_0x1D_CK1LOW 0x20 -#define REG_0x1D_TGSHLD 0x1f -#define REG_0x1DS_TGSHLD 0 +static constexpr RegMask REG_0x1D_CK4LOW = 0x80; +static constexpr RegMask REG_0x1D_CK3LOW = 0x40; +static constexpr RegMask REG_0x1D_CK1LOW = 0x20; +static constexpr RegMask REG_0x1D_TGSHLD = 0x1f; +static constexpr RegShift REG_0x1DS_TGSHLD = 0; -#define REG_0x1E_WDTIME 0xf0 -#define REG_0x1ES_WDTIME 4 -#define REG_0x1E_LINESEL 0x0f -#define REG_0x1ES_LINESEL 0 +static constexpr RegMask REG_0x1E_WDTIME = 0xf0; +static constexpr RegShift REG_0x1ES_WDTIME = 4; +static constexpr RegMask REG_0x1E_LINESEL = 0x0f; +static constexpr RegShift REG_0x1ES_LINESEL = 0; -#define REG_FEDCNT 0x1f +static constexpr RegAddr REG_FEDCNT = 0x1f; -#define REG_0x24 0x1c -#define REG_0x40 0x40 -#define REG_0x40_DOCSNR 0x80 -#define REG_0x40_ADFSNR 0x40 -#define REG_0x40_COVERSNR 0x20 -#define REG_0x40_CHKVER 0x10 -#define REG_0x40_DOCJAM 0x08 -#define REG_0x40_HISPDFLG 0x04 -#define REG_0x40_MOTMFLG 0x02 -#define REG_0x40_DATAENB 0x01 +static constexpr RegAddr REG_0x24 = 0x1c; +static constexpr RegAddr REG_0x40 = 0x40; +static constexpr RegMask REG_0x40_DOCSNR = 0x80; +static constexpr RegMask REG_0x40_ADFSNR = 0x40; +static constexpr RegMask REG_0x40_COVERSNR = 0x20; +static constexpr RegMask REG_0x40_CHKVER = 0x10; +static constexpr RegMask REG_0x40_DOCJAM = 0x08; +static constexpr RegMask REG_0x40_HISPDFLG = 0x04; +static constexpr RegMask REG_0x40_MOTMFLG = 0x02; +static constexpr RegMask REG_0x40_DATAENB = 0x01; -#define REG_0x41_PWRBIT 0x80 -#define REG_0x41_BUFEMPTY 0x40 -#define REG_0x41_FEEDFSH 0x20 -#define REG_0x41_SCANFSH 0x10 -#define REG_0x41_HOMESNR 0x08 -#define REG_0x41_LAMPSTS 0x04 -#define REG_0x41_FEBUSY 0x02 -#define REG_0x41_MOTORENB 0x01 +static constexpr RegMask REG_0x41_PWRBIT = 0x80; +static constexpr RegMask REG_0x41_BUFEMPTY = 0x40; +static constexpr RegMask REG_0x41_FEEDFSH = 0x20; +static constexpr RegMask REG_0x41_SCANFSH = 0x10; +static constexpr RegMask REG_0x41_HOMESNR = 0x08; +static constexpr RegMask REG_0x41_LAMPSTS = 0x04; +static constexpr RegMask REG_0x41_FEBUSY = 0x02; +static constexpr RegMask REG_0x41_MOTORENB = 0x01; -#define REG_0x58_VSMP 0xf8 -#define REG_0x58S_VSMP 3 -#define REG_0x58_VSMPW 0x07 -#define REG_0x58S_VSMPW 0 +static constexpr RegMask REG_0x58_VSMP = 0xf8; +static constexpr RegShift REG_0x58S_VSMP = 3; +static constexpr RegMask REG_0x58_VSMPW = 0x07; +static constexpr RegAddr REG_0x58S_VSMPW = 0; -#define REG_0x59_BSMP 0xf8 -#define REG_0x59S_BSMP 3 -#define REG_0x59_BSMPW 0x07 -#define REG_0x59S_BSMPW 0 +static constexpr RegMask REG_0x59_BSMP = 0xf8; +static constexpr RegAddr REG_0x59S_BSMP = 3; +static constexpr RegMask REG_0x59_BSMPW = 0x07; +static constexpr RegShift REG_0x59S_BSMPW = 0; -#define REG_0x5A_ADCLKINV 0x80 -#define REG_0x5A_RLCSEL 0x40 -#define REG_0x5A_CDSREF 0x30 -#define REG_0x5AS_CDSREF 4 -#define REG_0x5A_RLC 0x0f -#define REG_0x5AS_RLC 0 +static constexpr RegMask REG_0x5A_ADCLKINV = 0x80; +static constexpr RegMask REG_0x5A_RLCSEL = 0x40; +static constexpr RegMask REG_0x5A_CDSREF = 0x30; +static constexpr RegShift REG_0x5AS_CDSREF = 4; +static constexpr RegMask REG_0x5A_RLC = 0x0f; +static constexpr RegShift REG_0x5AS_RLC = 0; -#define REG_0x5E_DECSEL 0xe0 -#define REG_0x5ES_DECSEL 5 -#define REG_0x5E_STOPTIM 0x1f -#define REG_0x5ES_STOPTIM 0 +static constexpr RegMask REG_0x5E_DECSEL = 0xe0; +static constexpr RegShift REG_0x5ES_DECSEL = 5; +static constexpr RegMask REG_0x5E_STOPTIM = 0x1f; +static constexpr RegShift REG_0x5ES_STOPTIM = 0; -#define REG_0x60 0x60 -#define REG_0x60_Z1MOD 0x1f -#define REG_0x61 0x61 -#define REG_0x61_Z1MOD 0xff -#define REG_0x62 0x62 -#define REG_0x62_Z1MOD 0xff +static constexpr RegAddr REG_0x60 = 0x60; +static constexpr RegMask REG_0x60_Z1MOD = 0x1f; +static constexpr RegAddr REG_0x61 = 0x61; +static constexpr RegMask REG_0x61_Z1MOD = 0xff; +static constexpr RegAddr REG_0x62 = 0x62; +static constexpr RegMask REG_0x62_Z1MOD = 0xff; -#define REG_0x63 0x63 -#define REG_0x63_Z2MOD 0x1f -#define REG_0x64 0x64 -#define REG_0x64_Z2MOD 0xff -#define REG_0x65 0x65 -#define REG_0x65_Z2MOD 0xff +static constexpr RegAddr REG_0x63 = 0x63; +static constexpr RegMask REG_0x63_Z2MOD = 0x1f; +static constexpr RegAddr REG_0x64 = 0x64; +static constexpr RegMask REG_0x64_Z2MOD = 0xff; +static constexpr RegAddr REG_0x65 = 0x65; +static constexpr RegMask REG_0x65_Z2MOD = 0xff; -#define REG_0x60S_STEPSEL 5 -#define REG_0x60_STEPSEL 0xe0 -#define REG_0x60_FULLSTEP 0x00 -#define REG_0x60_HALFSTEP 0x20 -#define REG_0x60_EIGHTHSTEP 0x60 -#define REG_0x60_16THSTEP 0x80 +static constexpr RegShift REG_0x60S_STEPSEL = 5; +static constexpr RegMask REG_0x60_STEPSEL = 0xe0; +static constexpr RegMask REG_0x60_FULLSTEP = 0x00; +static constexpr RegMask REG_0x60_HALFSTEP = 0x20; +static constexpr RegMask REG_0x60_EIGHTHSTEP = 0x60; +static constexpr RegMask REG_0x60_16THSTEP = 0x80; -#define REG_0x63S_FSTPSEL 5 -#define REG_0x63_FSTPSEL 0xe0 -#define REG_0x63_FULLSTEP 0x00 -#define REG_0x63_HALFSTEP 0x20 -#define REG_0x63_EIGHTHSTEP 0x60 -#define REG_0x63_16THSTEP 0x80 +static constexpr RegShift REG_0x63S_FSTPSEL = 5; +static constexpr RegMask REG_0x63_FSTPSEL = 0xe0; +static constexpr RegMask REG_0x63_FULLSTEP = 0x00; +static constexpr RegMask REG_0x63_HALFSTEP = 0x20; +static constexpr RegMask REG_0x63_EIGHTHSTEP = 0x60; +static constexpr RegMask REG_0x63_16THSTEP = 0x80; -#define REG_0x67 0x67 -#define REG_0x67_MTRPWM 0x80 +static constexpr RegAddr REG_0x67 = 0x67; +static constexpr RegMask REG_0x67_MTRPWM = 0x80; -#define REG_0x68 0x68 -#define REG_0x68_FASTPWM 0x80 +static constexpr RegAddr REG_0x68 = 0x68; +static constexpr RegMask REG_0x68_FASTPWM = 0x80; -#define REG_0x6B 0x6b -#define REG_0x6B_MULTFILM 0x80 -#define REG_0x6B_GPOM13 0x40 -#define REG_0x6B_GPOM12 0x20 -#define REG_0x6B_GPOM11 0x10 -#define REG_0x6B_GPO18 0x02 -#define REG_0x6B_GPO17 0x01 +static constexpr RegAddr REG_0x6B = 0x6b; +static constexpr RegMask REG_0x6B_MULTFILM = 0x80; +static constexpr RegMask REG_0x6B_GPOM13 = 0x40; +static constexpr RegMask REG_0x6B_GPOM12 = 0x20; +static constexpr RegMask REG_0x6B_GPOM11 = 0x10; +static constexpr RegMask REG_0x6B_GPO18 = 0x02; +static constexpr RegMask REG_0x6B_GPO17 = 0x01; -#define REG_0x6C 0x6c -#define REG_0x6C_GPIO16 0x80 -#define REG_0x6C_GPIO15 0x40 -#define REG_0x6C_GPIO14 0x20 -#define REG_0x6C_GPIO13 0x10 -#define REG_0x6C_GPIO12 0x08 -#define REG_0x6C_GPIO11 0x04 -#define REG_0x6C_GPIO10 0x02 -#define REG_0x6C_GPIO9 0x01 -#define REG_0x6C_GPIOH 0xff -#define REG_0x6C_GPIOL 0xff +static constexpr RegAddr REG_0x6C = 0x6c; +static constexpr RegMask REG_0x6C_GPIO16 = 0x80; +static constexpr RegMask REG_0x6C_GPIO15 = 0x40; +static constexpr RegMask REG_0x6C_GPIO14 = 0x20; +static constexpr RegMask REG_0x6C_GPIO13 = 0x10; +static constexpr RegMask REG_0x6C_GPIO12 = 0x08; +static constexpr RegMask REG_0x6C_GPIO11 = 0x04; +static constexpr RegMask REG_0x6C_GPIO10 = 0x02; +static constexpr RegMask REG_0x6C_GPIO9 = 0x01; +static constexpr RegMask REG_0x6C_GPIOH = 0xff; +static constexpr RegMask REG_0x6C_GPIOL = 0xff; -#define REG_0x6D 0x6d -#define REG_0x6E 0x6e -#define REG_0x6F 0x6f -#define REG_0x7E 0x7e +static constexpr RegAddr REG_0x6D = 0x6d; +static constexpr RegAddr REG_0x6E = 0x6e; +static constexpr RegAddr REG_0x6F = 0x6f; +static constexpr RegAddr REG_0x7E = 0x7e; -#define REG_0x87_ACYCNRLC 0x10 -#define REG_0x87_ENOFFSET 0x08 -#define REG_0x87_LEDADD 0x04 -#define REG_0x87_CK4ADC 0x02 -#define REG_0x87_AUTOCONF 0x01 +static constexpr RegMask REG_0x87_ACYCNRLC = 0x10; +static constexpr RegMask REG_0x87_ENOFFSET = 0x08; +static constexpr RegMask REG_0x87_LEDADD = 0x04; +static constexpr RegMask REG_0x87_CK4ADC = 0x02; +static constexpr RegMask REG_0x87_AUTOCONF = 0x01; -#define REG_0x9E 0x9e -#define REG_0x9F 0x9f +static constexpr RegAddr REG_0x9E = 0x9e; +static constexpr RegAddr REG_0x9F = 0x9f; -#define REG_0xA6 0xa6 -#define REG_0xA7 0xa7 -#define REG_0xA8 0xa8 -#define REG_0xA9 0xa9 -#define REG_0xAB 0xab +static constexpr RegAddr REG_0xA6 = 0xa6; +static constexpr RegAddr REG_0xA7 = 0xa7; +static constexpr RegAddr REG_0xA8 = 0xa8; +static constexpr RegAddr REG_0xA9 = 0xa9; +static constexpr RegAddr REG_0xAB = 0xab; -#define REG_EXPR 0x10 -#define REG_EXPG 0x12 -#define REG_EXPB 0x14 -#define REG_EXPDMY 0x19 -#define REG_STEPNO 0x21 -#define REG_FWDSTEP 0x22 -#define REG_BWDSTEP 0x23 -#define REG_FASTNO 0x24 -#define REG_DPISET 0x2c -#define REG_STRPIXEL 0x30 -#define REG_ENDPIXEL 0x32 -#define REG_LINCNT 0x25 -#define REG_MAXWD 0x35 -#define REG_LPERIOD 0x38 -#define REG_FEEDL 0x3d -#define REG_FMOVDEC 0x5f -#define REG_FSHDEC 0x69 -#define REG_FMOVNO 0x6a -#define REG_CK1MAP 0x74 -#define REG_CK3MAP 0x77 -#define REG_CK4MAP 0x7a +static constexpr RegAddr REG_EXPR = 0x10; +static constexpr RegAddr REG_EXPG = 0x12; +static constexpr RegAddr REG_EXPB = 0x14; +static constexpr RegAddr REG_EXPDMY = 0x19; +static constexpr RegAddr REG_STEPNO = 0x21; +static constexpr RegAddr REG_FWDSTEP = 0x22; +static constexpr RegAddr REG_BWDSTEP = 0x23; +static constexpr RegAddr REG_FASTNO = 0x24; +static constexpr RegAddr REG_DPISET = 0x2c; +static constexpr RegAddr REG_STRPIXEL = 0x30; +static constexpr RegAddr REG_ENDPIXEL = 0x32; +static constexpr RegAddr REG_LINCNT = 0x25; +static constexpr RegAddr REG_MAXWD = 0x35; +static constexpr RegAddr REG_LPERIOD = 0x38; +static constexpr RegAddr REG_FEEDL = 0x3d; +static constexpr RegAddr REG_FMOVDEC = 0x5f; +static constexpr RegAddr REG_FSHDEC = 0x69; +static constexpr RegAddr REG_FMOVNO = 0x6a; +static constexpr RegAddr REG_CK1MAP = 0x74; +static constexpr RegAddr REG_CK3MAP = 0x77; +static constexpr RegAddr REG_CK4MAP = 0x7a; -#define REG_0xF8 0xf8 -#define REG_0xF8_MAXSEL 0xf0 -#define REG_0xF8_SMAXSEL 4 -#define REG_0xF8_MINSEL 0x0f +static constexpr RegAddr REG_0xF8 = 0xf8; +static constexpr RegMask REG_0xF8_MAXSEL = 0xf0; +static constexpr RegShift REG_0xF8_SMAXSEL = 4; +static constexpr RegMask REG_0xF8_MINSEL = 0x0f; #define SETREG(adr,val) { dev->reg.init_reg(adr, val); } diff --git a/backend/genesys/gl847_registers.h b/backend/genesys/gl847_registers.h index 6b02efb34..19e0199e5 100644 --- a/backend/genesys/gl847_registers.h +++ b/backend/genesys/gl847_registers.h @@ -44,285 +44,287 @@ #ifndef BACKEND_GENESYS_GL847_REGISTERS_H #define BACKEND_GENESYS_GL847_REGISTERS_H +#include + namespace genesys { namespace gl847 { -#define REG_0x01 0x01 -#define REG_0x01_CISSET 0x80 -#define REG_0x01_DOGENB 0x40 -#define REG_0x01_DVDSET 0x20 -#define REG_0x01_STAGGER 0x10 -#define REG_0x01_COMPENB 0x08 -#define REG_0x01_TRUEGRAY 0x04 -#define REG_0x01_SHDAREA 0x02 -#define REG_0x01_SCAN 0x01 +using RegAddr = std::uint16_t; +using RegMask = std::uint8_t; +using RegShift = unsigned; -#define REG_0x02 0x02 -#define REG_0x02_NOTHOME 0x80 -#define REG_0x02_ACDCDIS 0x40 -#define REG_0x02_AGOHOME 0x20 -#define REG_0x02_MTRPWR 0x10 -#define REG_0x02_FASTFED 0x08 -#define REG_0x02_MTRREV 0x04 -#define REG_0x02_HOMENEG 0x02 -#define REG_0x02_LONGCURV 0x01 +static constexpr RegAddr REG_0x01 = 0x01; +static constexpr RegMask REG_0x01_CISSET = 0x80; +static constexpr RegMask REG_0x01_DOGENB = 0x40; +static constexpr RegMask REG_0x01_DVDSET = 0x20; +static constexpr RegMask REG_0x01_STAGGER = 0x10; +static constexpr RegMask REG_0x01_COMPENB = 0x08; +static constexpr RegMask REG_0x01_TRUEGRAY = 0x04; +static constexpr RegMask REG_0x01_SHDAREA = 0x02; +static constexpr RegMask REG_0x01_SCAN = 0x01; -#define REG_0x03 0x03 -#define REG_0x03_LAMPDOG 0x80 -#define REG_0x03_AVEENB 0x40 -#define REG_0x03_XPASEL 0x20 -#define REG_0x03_LAMPPWR 0x10 -#define REG_0x03_LAMPTIM 0x0f +static constexpr RegAddr REG_0x02 = 0x02; +static constexpr RegMask REG_0x02_NOTHOME = 0x80; +static constexpr RegMask REG_0x02_ACDCDIS = 0x40; +static constexpr RegMask REG_0x02_AGOHOME = 0x20; +static constexpr RegMask REG_0x02_MTRPWR = 0x10; +static constexpr RegMask REG_0x02_FASTFED = 0x08; +static constexpr RegMask REG_0x02_MTRREV = 0x04; +static constexpr RegMask REG_0x02_HOMENEG = 0x02; +static constexpr RegMask REG_0x02_LONGCURV = 0x01; -#define REG_0x04 0x04 -#define REG_0x04_LINEART 0x80 -#define REG_0x04_BITSET 0x40 -#define REG_0x04_AFEMOD 0x30 -#define REG_0x04_FILTER 0x0c -#define REG_0x04_FESET 0x03 +static constexpr RegAddr REG_0x03 = 0x03; +static constexpr RegMask REG_0x03_LAMPDOG = 0x80; +static constexpr RegMask REG_0x03_AVEENB = 0x40; +static constexpr RegMask REG_0x03_XPASEL = 0x20; +static constexpr RegMask REG_0x03_LAMPPWR = 0x10; +static constexpr RegMask REG_0x03_LAMPTIM = 0x0f; -#define REG_0x04S_AFEMOD 4 +static constexpr RegAddr REG_0x04 = 0x04; +static constexpr RegMask REG_0x04_LINEART = 0x80; +static constexpr RegMask REG_0x04_BITSET = 0x40; +static constexpr RegMask REG_0x04_AFEMOD = 0x30; +static constexpr RegMask REG_0x04_FILTER = 0x0c; +static constexpr RegMask REG_0x04_FESET = 0x03; +static constexpr RegShift REG_0x04S_AFEMOD = 4; -#define REG_0x05 0x05 -#define REG_0x05_DPIHW 0xc0 -#define REG_0x05_DPIHW_600 0x00 -#define REG_0x05_DPIHW_1200 0x40 -#define REG_0x05_DPIHW_2400 0x80 -#define REG_0x05_DPIHW_4800 0xc0 -#define REG_0x05_MTLLAMP 0x30 -#define REG_0x05_GMMENB 0x08 -#define REG_0x05_MTLBASE 0x03 +static constexpr RegAddr REG_0x05 = 0x05; +static constexpr RegMask REG_0x05_DPIHW = 0xc0; +static constexpr RegMask REG_0x05_DPIHW_600 = 0x00; +static constexpr RegMask REG_0x05_DPIHW_1200 = 0x40; +static constexpr RegMask REG_0x05_DPIHW_2400 = 0x80; +static constexpr RegMask REG_0x05_DPIHW_4800 = 0xc0; +static constexpr RegMask REG_0x05_MTLLAMP = 0x30; +static constexpr RegMask REG_0x05_GMMENB = 0x08; +static constexpr RegMask REG_0x05_MTLBASE = 0x03; -#define REG_0x06_SCANMOD 0xe0 -#define REG_0x06S_SCANMOD 5 -#define REG_0x06_PWRBIT 0x10 -#define REG_0x06_GAIN4 0x08 -#define REG_0x06_OPTEST 0x07 +static constexpr RegMask REG_0x06_SCANMOD = 0xe0; +static constexpr RegMask REG_0x06S_SCANMOD = 5; +static constexpr RegMask REG_0x06_PWRBIT = 0x10; +static constexpr RegMask REG_0x06_GAIN4 = 0x08; +static constexpr RegMask REG_0x06_OPTEST = 0x07; -#define REG_0x07_LAMPSIM 0x80 +static constexpr RegMask REG_0x07_LAMPSIM = 0x80; -#define REG_0x08_DRAM2X 0x80 -#define REG_0x08_MPENB 0x20 -#define REG_0x08_CIS_LINE 0x10 -#define REG_0x08_IR1ENB 0x08 -#define REG_0x08_IR2ENB 0x04 -#define REG_0x08_ENB24M 0x01 +static constexpr RegMask REG_0x08_DRAM2X = 0x80; +static constexpr RegMask REG_0x08_MPENB = 0x20; +static constexpr RegMask REG_0x08_CIS_LINE = 0x10; +static constexpr RegMask REG_0x08_IR1ENB = 0x08; +static constexpr RegMask REG_0x08_IR2ENB = 0x04; +static constexpr RegMask REG_0x08_ENB24M = 0x01; -#define REG_0x09_MCNTSET 0xc0 -#define REG_0x09_EVEN1ST 0x20 -#define REG_0x09_BLINE1ST 0x10 -#define REG_0x09_BACKSCAN 0x08 -#define REG_0x09_ENHANCE 0x04 -#define REG_0x09_SHORTTG 0x02 -#define REG_0x09_NWAIT 0x01 +static constexpr RegMask REG_0x09_MCNTSET = 0xc0; +static constexpr RegMask REG_0x09_EVEN1ST = 0x20; +static constexpr RegMask REG_0x09_BLINE1ST = 0x10; +static constexpr RegMask REG_0x09_BACKSCAN = 0x08; +static constexpr RegMask REG_0x09_ENHANCE = 0x04; +static constexpr RegMask REG_0x09_SHORTTG = 0x02; +static constexpr RegMask REG_0x09_NWAIT = 0x01; -#define REG_0x09S_MCNTSET 6 -#define REG_0x09S_CLKSET 4 +static constexpr RegShift REG_0x09S_MCNTSET = 6; +static constexpr RegShift REG_0x09S_CLKSET = 4; +static constexpr RegMask REG_0x0A_LPWMEN = 0x10; -#define REG_0x0A_LPWMEN 0x10 +static constexpr RegAddr REG_0x0B = 0x0b; +static constexpr RegMask REG_0x0B_DRAMSEL = 0x07; +static constexpr RegMask REG_0x0B_ENBDRAM = 0x08; +static constexpr RegMask REG_0x0B_RFHDIS = 0x10; +static constexpr RegMask REG_0x0B_CLKSET = 0xe0; +static constexpr RegMask REG_0x0B_24MHZ = 0x00; +static constexpr RegMask REG_0x0B_30MHZ = 0x20; +static constexpr RegMask REG_0x0B_40MHZ = 0x40; +static constexpr RegMask REG_0x0B_48MHZ = 0x60; +static constexpr RegMask REG_0x0B_60MHZ = 0x80; -#define REG_0x0B 0x0b -#define REG_0x0B_DRAMSEL 0x07 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_ENBDRAM 0x08 -#define REG_0x0B_RFHDIS 0x10 -#define REG_0x0B_CLKSET 0xe0 -#define REG_0x0B_24MHZ 0x00 -#define REG_0x0B_30MHZ 0x20 -#define REG_0x0B_40MHZ 0x40 -#define REG_0x0B_48MHZ 0x60 -#define REG_0x0B_60MHZ 0x80 +static constexpr RegAddr REG_0x0C = 0x0c; +static constexpr RegMask REG_0x0C_CCDLMT = 0x0f; -#define REG_0x0C 0x0c -#define REG_0x0C_CCDLMT 0x0f +static constexpr RegAddr REG_0x0D = 0x0d; +static constexpr RegMask REG_0x0D_FULLSTP = 0x10; +static constexpr RegMask REG_0x0D_SEND = 0x80; +static constexpr RegMask REG_0x0D_CLRMCNT = 0x04; +static constexpr RegMask REG_0x0D_CLRDOCJM = 0x02; +static constexpr RegMask REG_0x0D_CLRLNCNT = 0x01; -#define REG_0x0D 0x0d -#define REG_0x0D_FULLSTP 0x10 -#define REG_0x0D_SEND 0x80 -#define REG_0x0D_CLRMCNT 0x04 -#define REG_0x0D_CLRDOCJM 0x02 -#define REG_0x0D_CLRLNCNT 0x01 +static constexpr RegAddr REG_0x0F = 0x0f; -#define REG_0x0F 0x0f +static constexpr RegMask REG_0x16_CTRLHI = 0x80; +static constexpr RegMask REG_0x16_TOSHIBA = 0x40; +static constexpr RegMask REG_0x16_TGINV = 0x20; +static constexpr RegMask REG_0x16_CK1INV = 0x10; +static constexpr RegMask REG_0x16_CK2INV = 0x08; +static constexpr RegMask REG_0x16_CTRLINV = 0x04; +static constexpr RegMask REG_0x16_CKDIS = 0x02; +static constexpr RegMask REG_0x16_CTRLDIS = 0x01; -#define REG_0x16_CTRLHI 0x80 -#define REG_0x16_TOSHIBA 0x40 -#define REG_0x16_TGINV 0x20 -#define REG_0x16_CK1INV 0x10 -#define REG_0x16_CK2INV 0x08 -#define REG_0x16_CTRLINV 0x04 -#define REG_0x16_CKDIS 0x02 -#define REG_0x16_CTRLDIS 0x01 +static constexpr RegMask REG_0x17_TGMODE = 0xc0; +static constexpr RegMask REG_0x17_TGMODE_NO_DUMMY = 0x00; +static constexpr RegMask REG_0x17_TGMODE_REF = 0x40; +static constexpr RegMask REG_0x17_TGMODE_XPA = 0x80; +static constexpr RegMask REG_0x17_TGW = 0x3f; +static constexpr RegMask REG_0x17S_TGW = 0; -#define REG_0x17_TGMODE 0xc0 -#define REG_0x17_TGMODE_NO_DUMMY 0x00 -#define REG_0x17_TGMODE_REF 0x40 -#define REG_0x17_TGMODE_XPA 0x80 -#define REG_0x17_TGW 0x3f -#define REG_0x17S_TGW 0 +static constexpr RegAddr REG_0x18 = 0x18; +static constexpr RegMask REG_0x18_CNSET = 0x80; +static constexpr RegMask REG_0x18_DCKSEL = 0x60; +static constexpr RegMask REG_0x18_CKTOGGLE = 0x10; +static constexpr RegMask REG_0x18_CKDELAY = 0x0c; +static constexpr RegMask REG_0x18_CKSEL = 0x03; -#define REG_0x18 0x18 -#define REG_0x18_CNSET 0x80 -#define REG_0x18_DCKSEL 0x60 -#define REG_0x18_CKTOGGLE 0x10 -#define REG_0x18_CKDELAY 0x0c -#define REG_0x18_CKSEL 0x03 +static constexpr RegMask REG_0x1A_SW2SET = 0x80; +static constexpr RegMask REG_0x1A_SW1SET = 0x40; +static constexpr RegMask REG_0x1A_MANUAL3 = 0x02; +static constexpr RegMask REG_0x1A_MANUAL1 = 0x01; +static constexpr RegMask REG_0x1A_CK4INV = 0x08; +static constexpr RegMask REG_0x1A_CK3INV = 0x04; +static constexpr RegMask REG_0x1A_LINECLP = 0x02; -#define REG_0x1A_SW2SET 0x80 -#define REG_0x1A_SW1SET 0x40 -#define REG_0x1A_MANUAL3 0x02 -#define REG_0x1A_MANUAL1 0x01 -#define REG_0x1A_CK4INV 0x08 -#define REG_0x1A_CK3INV 0x04 -#define REG_0x1A_LINECLP 0x02 +static constexpr RegAddr REG_0x1C = 0x1c; +static constexpr RegMask REG_0x1C_TGTIME = 0x07; -#define REG_0x1C 0x1c -#define REG_0x1C_TGTIME 0x07 +static constexpr RegMask REG_0x1D_CK4LOW = 0x80; +static constexpr RegMask REG_0x1D_CK3LOW = 0x40; +static constexpr RegMask REG_0x1D_CK1LOW = 0x20; +static constexpr RegMask REG_0x1D_TGSHLD = 0x1f; +static constexpr RegMask REG_0x1DS_TGSHLD = 0; -#define REG_0x1D_CK4LOW 0x80 -#define REG_0x1D_CK3LOW 0x40 -#define REG_0x1D_CK1LOW 0x20 -#define REG_0x1D_TGSHLD 0x1f -#define REG_0x1DS_TGSHLD 0 +static constexpr RegMask REG_0x1E_WDTIME = 0xf0; +static constexpr RegMask REG_0x1ES_WDTIME = 4; +static constexpr RegMask REG_0x1E_LINESEL = 0x0f; +static constexpr RegMask REG_0x1ES_LINESEL = 0; +static constexpr RegAddr REG_FEDCNT = 0x1f; -#define REG_0x1E_WDTIME 0xf0 -#define REG_0x1ES_WDTIME 4 -#define REG_0x1E_LINESEL 0x0f -#define REG_0x1ES_LINESEL 0 +static constexpr RegAddr REG_0x24 = 0x1c; +static constexpr RegAddr REG_0x40 = 0x40; +static constexpr RegMask REG_0x40_CHKVER = 0x10; +static constexpr RegMask REG_0x40_HISPDFLG = 0x04; +static constexpr RegMask REG_0x40_MOTMFLG = 0x02; +static constexpr RegMask REG_0x40_DATAENB = 0x01; -#define REG_FEDCNT 0x1f +static constexpr RegMask REG_0x41_PWRBIT = 0x80; +static constexpr RegMask REG_0x41_BUFEMPTY = 0x40; +static constexpr RegMask REG_0x41_FEEDFSH = 0x20; +static constexpr RegMask REG_0x41_SCANFSH = 0x10; +static constexpr RegMask REG_0x41_HOMESNR = 0x08; +static constexpr RegMask REG_0x41_LAMPSTS = 0x04; +static constexpr RegMask REG_0x41_FEBUSY = 0x02; +static constexpr RegMask REG_0x41_MOTORENB = 0x01; -#define REG_0x24 0x1c -#define REG_0x40 0x40 -#define REG_0x40_CHKVER 0x10 -#define REG_0x40_HISPDFLG 0x04 -#define REG_0x40_MOTMFLG 0x02 -#define REG_0x40_DATAENB 0x01 +static constexpr RegMask REG_0x58_VSMP = 0xf8; +static constexpr RegShift REG_0x58S_VSMP = 3; +static constexpr RegMask REG_0x58_VSMPW = 0x07; +static constexpr RegShift REG_0x58S_VSMPW = 0; -#define REG_0x41_PWRBIT 0x80 -#define REG_0x41_BUFEMPTY 0x40 -#define REG_0x41_FEEDFSH 0x20 -#define REG_0x41_SCANFSH 0x10 -#define REG_0x41_HOMESNR 0x08 -#define REG_0x41_LAMPSTS 0x04 -#define REG_0x41_FEBUSY 0x02 -#define REG_0x41_MOTORENB 0x01 +static constexpr RegMask REG_0x59_BSMP = 0xf8; +static constexpr RegShift REG_0x59S_BSMP = 3; +static constexpr RegMask REG_0x59_BSMPW = 0x07; +static constexpr RegShift REG_0x59S_BSMPW = 0; -#define REG_0x58_VSMP 0xf8 -#define REG_0x58S_VSMP 3 -#define REG_0x58_VSMPW 0x07 -#define REG_0x58S_VSMPW 0 +static constexpr RegMask REG_0x5A_ADCLKINV = 0x80; +static constexpr RegMask REG_0x5A_RLCSEL = 0x40; +static constexpr RegMask REG_0x5A_CDSREF = 0x30; +static constexpr RegShift REG_0x5AS_CDSREF = 4; +static constexpr RegMask REG_0x5A_RLC = 0x0f; +static constexpr RegShift REG_0x5AS_RLC = 0; -#define REG_0x59_BSMP 0xf8 -#define REG_0x59S_BSMP 3 -#define REG_0x59_BSMPW 0x07 -#define REG_0x59S_BSMPW 0 +static constexpr RegMask REG_0x5E_DECSEL = 0xe0; +static constexpr RegShift REG_0x5ES_DECSEL = 5; +static constexpr RegMask REG_0x5E_STOPTIM = 0x1f; +static constexpr RegShift REG_0x5ES_STOPTIM = 0; -#define REG_0x5A_ADCLKINV 0x80 -#define REG_0x5A_RLCSEL 0x40 -#define REG_0x5A_CDSREF 0x30 -#define REG_0x5AS_CDSREF 4 -#define REG_0x5A_RLC 0x0f -#define REG_0x5AS_RLC 0 +static constexpr RegAddr REG_0x60 = 0x60; +static constexpr RegMask REG_0x60_Z1MOD = 0x1f; +static constexpr RegAddr REG_0x61 = 0x61; +static constexpr RegMask REG_0x61_Z1MOD = 0xff; +static constexpr RegAddr REG_0x62 = 0x62; +static constexpr RegMask REG_0x62_Z1MOD = 0xff; -#define REG_0x5E_DECSEL 0xe0 -#define REG_0x5ES_DECSEL 5 -#define REG_0x5E_STOPTIM 0x1f -#define REG_0x5ES_STOPTIM 0 +static constexpr RegAddr REG_0x63 = 0x63; +static constexpr RegMask REG_0x63_Z2MOD = 0x1f; +static constexpr RegAddr REG_0x64 = 0x64; +static constexpr RegMask REG_0x64_Z2MOD = 0xff; +static constexpr RegAddr REG_0x65 = 0x65; +static constexpr RegMask REG_0x65_Z2MOD = 0xff; -#define REG_0x60 0x60 -#define REG_0x60_Z1MOD 0x1f -#define REG_0x61 0x61 -#define REG_0x61_Z1MOD 0xff -#define REG_0x62 0x62 -#define REG_0x62_Z1MOD 0xff +static constexpr RegShift REG_0x60S_STEPSEL = 5; +static constexpr RegMask REG_0x60_STEPSEL = 0xe0; +static constexpr RegMask REG_0x60_FULLSTEP = 0x00; +static constexpr RegMask REG_0x60_HALFSTEP = 0x20; +static constexpr RegMask REG_0x60_EIGHTHSTEP = 0x60; +static constexpr RegMask REG_0x60_16THSTEP = 0x80; -#define REG_0x63 0x63 -#define REG_0x63_Z2MOD 0x1f -#define REG_0x64 0x64 -#define REG_0x64_Z2MOD 0xff -#define REG_0x65 0x65 -#define REG_0x65_Z2MOD 0xff +static constexpr RegShift REG_0x63S_FSTPSEL = 5; +static constexpr RegMask REG_0x63_FSTPSEL = 0xe0; +static constexpr RegMask REG_0x63_FULLSTEP = 0x00; +static constexpr RegMask REG_0x63_HALFSTEP = 0x20; +static constexpr RegMask REG_0x63_EIGHTHSTEP = 0x60; +static constexpr RegMask REG_0x63_16THSTEP = 0x80; -#define REG_0x60S_STEPSEL 5 -#define REG_0x60_STEPSEL 0xe0 -#define REG_0x60_FULLSTEP 0x00 -#define REG_0x60_HALFSTEP 0x20 -#define REG_0x60_EIGHTHSTEP 0x60 -#define REG_0x60_16THSTEP 0x80 +static constexpr RegAddr REG_0x67 = 0x67; +static constexpr RegMask REG_0x67_MTRPWM = 0x80; -#define REG_0x63S_FSTPSEL 5 -#define REG_0x63_FSTPSEL 0xe0 -#define REG_0x63_FULLSTEP 0x00 -#define REG_0x63_HALFSTEP 0x20 -#define REG_0x63_EIGHTHSTEP 0x60 -#define REG_0x63_16THSTEP 0x80 +static constexpr RegAddr REG_0x68 = 0x68; +static constexpr RegMask REG_0x68_FASTPWM = 0x80; -#define REG_0x67 0x67 -#define REG_0x67_MTRPWM 0x80 +static constexpr RegAddr REG_0x6B = 0x6b; +static constexpr RegMask REG_0x6B_MULTFILM = 0x80; +static constexpr RegMask REG_0x6B_GPOM13 = 0x40; +static constexpr RegMask REG_0x6B_GPOM12 = 0x20; +static constexpr RegMask REG_0x6B_GPOM11 = 0x10; +static constexpr RegMask REG_0x6B_GPO18 = 0x02; +static constexpr RegMask REG_0x6B_GPO17 = 0x01; -#define REG_0x68 0x68 -#define REG_0x68_FASTPWM 0x80 +static constexpr RegShift REG_0x6C = 0x6c; +static constexpr RegMask REG_0x6C_GPIO16 = 0x80; +static constexpr RegMask REG_0x6C_GPIO15 = 0x40; +static constexpr RegMask REG_0x6C_GPIO14 = 0x20; +static constexpr RegMask REG_0x6C_GPIO13 = 0x10; +static constexpr RegMask REG_0x6C_GPIO12 = 0x08; +static constexpr RegMask REG_0x6C_GPIO11 = 0x04; +static constexpr RegMask REG_0x6C_GPIO10 = 0x02; +static constexpr RegMask REG_0x6C_GPIO9 = 0x01; +static constexpr RegMask REG_0x6C_GPIOH = 0xff; +static constexpr RegMask REG_0x6C_GPIOL = 0xff; -#define REG_0x6B 0x6b -#define REG_0x6B_MULTFILM 0x80 -#define REG_0x6B_GPOM13 0x40 -#define REG_0x6B_GPOM12 0x20 -#define REG_0x6B_GPOM11 0x10 -#define REG_0x6B_GPO18 0x02 -#define REG_0x6B_GPO17 0x01 +static constexpr RegAddr REG_0x6D = 0x6d; +static constexpr RegAddr REG_0x6E = 0x6e; +static constexpr RegAddr REG_0x6F = 0x6f; +static constexpr RegAddr REG_0x7E = 0x7e; -#define REG_0x6C 0x6c -#define REG_0x6C_GPIO16 0x80 -#define REG_0x6C_GPIO15 0x40 -#define REG_0x6C_GPIO14 0x20 -#define REG_0x6C_GPIO13 0x10 -#define REG_0x6C_GPIO12 0x08 -#define REG_0x6C_GPIO11 0x04 -#define REG_0x6C_GPIO10 0x02 -#define REG_0x6C_GPIO9 0x01 -#define REG_0x6C_GPIOH 0xff -#define REG_0x6C_GPIOL 0xff +static constexpr RegMask REG_0x87_LEDADD = 0x04; -#define REG_0x6D 0x6d -#define REG_0x6E 0x6e -#define REG_0x6F 0x6f -#define REG_0x7E 0x7e +static constexpr RegAddr REG_0x9E = 0x9e; +static constexpr RegAddr REG_0x9F = 0x9f; -#define REG_0x87_LEDADD 0x04 +static constexpr RegAddr REG_0xA6 = 0xa6; +static constexpr RegAddr REG_0xA7 = 0xa7; +static constexpr RegAddr REG_0xA8 = 0xa8; +static constexpr RegAddr REG_0xA9 = 0xa9; +static constexpr RegAddr REG_0xAB = 0xab; -#define REG_0x9E 0x9e -#define REG_0x9F 0x9f - -#define REG_0xA6 0xa6 -#define REG_0xA7 0xa7 -#define REG_0xA8 0xa8 -#define REG_0xA9 0xa9 -#define REG_0xAB 0xab - -#define REG_EXPR 0x10 -#define REG_EXPG 0x12 -#define REG_EXPB 0x14 -#define REG_EXPDMY 0x19 -#define REG_STEPNO 0x21 -#define REG_FWDSTEP 0x22 -#define REG_BWDSTEP 0x23 -#define REG_FASTNO 0x24 -#define REG_DPISET 0x2c -#define REG_STRPIXEL 0x30 -#define REG_ENDPIXEL 0x32 -#define REG_LINCNT 0x25 -#define REG_MAXWD 0x35 -#define REG_LPERIOD 0x38 -#define REG_FEEDL 0x3d -#define REG_FMOVDEC 0x5f -#define REG_FSHDEC 0x69 -#define REG_FMOVNO 0x6a -#define REG_CK1MAP 0x74 -#define REG_CK3MAP 0x77 -#define REG_CK4MAP 0x7a +static constexpr RegAddr REG_EXPR = 0x10; +static constexpr RegAddr REG_EXPG = 0x12; +static constexpr RegAddr REG_EXPB = 0x14; +static constexpr RegAddr REG_EXPDMY = 0x19; +static constexpr RegAddr REG_STEPNO = 0x21; +static constexpr RegAddr REG_FWDSTEP = 0x22; +static constexpr RegAddr REG_BWDSTEP = 0x23; +static constexpr RegAddr REG_FASTNO = 0x24; +static constexpr RegAddr REG_DPISET = 0x2c; +static constexpr RegAddr REG_STRPIXEL = 0x30; +static constexpr RegAddr REG_ENDPIXEL = 0x32; +static constexpr RegAddr REG_LINCNT = 0x25; +static constexpr RegAddr REG_MAXWD = 0x35; +static constexpr RegAddr REG_LPERIOD = 0x38; +static constexpr RegAddr REG_FEEDL = 0x3d; +static constexpr RegAddr REG_FMOVDEC = 0x5f; +static constexpr RegAddr REG_FSHDEC = 0x69; +static constexpr RegAddr REG_FMOVNO = 0x6a; +static constexpr RegAddr REG_CK1MAP = 0x74; +static constexpr RegAddr REG_CK3MAP = 0x77; +static constexpr RegAddr REG_CK4MAP = 0x7a; #define SETREG(adr,val) { dev->reg.init_reg(adr, val); }