2011-11-02 07:40:04 +00:00
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/* sane - Scanner Access Now Easy.
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2012-03-17 09:36:30 +00:00
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Copyright (C) 2011-2012 St<EFBFBD>phane Voltz <stef.dev@free.fr>
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2011-11-02 07:40:04 +00:00
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This file is part of the SANE package.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA.
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As a special exception, the authors of SANE give permission for
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additional uses of the libraries contained in this release of SANE.
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The exception is that, if you link a SANE library with other files
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to produce an executable, this does not by itself cause the
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resulting executable to be covered by the GNU General Public
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License. Your use of that executable is in no way restricted on
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account of linking the SANE library code into it.
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This exception does not, however, invalidate any other reasons why
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the executable file might be covered by the GNU General Public
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License.
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If you submit changes to SANE to the maintainers to be included in
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a subsequent release, you agree by submitting the changes that
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those changes may be distributed with this exception intact.
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If you write modifications of your own for SANE, it is your choice
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whether to permit this exception to apply to your modifications.
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If you do not wish that, delete this exception notice.
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*/
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#include "genesys.h"
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/* Individual bits */
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#define REG01_CISSET 0x80
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#define REG01_DOGENB 0x40
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#define REG01_DVDSET 0x20
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#define REG01_M16DRAM 0x08
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#define REG01_DRAMSEL 0x04
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#define REG01_SHDAREA 0x02
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#define REG01_SCAN 0x01
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#define REG02_NOTHOME 0x80
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#define REG02_ACDCDIS 0x40
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#define REG02_AGOHOME 0x20
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#define REG02_MTRPWR 0x10
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#define REG02_FASTFED 0x08
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#define REG02_MTRREV 0x04
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#define REG02_HOMENEG 0x02
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#define REG02_LONGCURV 0x01
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#define REG03_LAMPDOG 0x80
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#define REG03_AVEENB 0x40
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#define REG03_XPASEL 0x20
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#define REG03_LAMPPWR 0x10
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#define REG03_LAMPTIM 0x0f
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#define REG04_LINEART 0x80
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#define REG04_BITSET 0x40
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#define REG04_AFEMOD 0x30
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#define REG04_FILTER 0x0c
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#define REG04_FESET 0x03
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#define REG04S_AFEMOD 4
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#define REG05_DPIHW 0xc0
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#define REG05_DPIHW_600 0x00
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#define REG05_DPIHW_1200 0x40
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#define REG05_DPIHW_2400 0x80
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#define REG05_MTLLAMP 0x30
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#define REG05_GMMENB 0x08
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#define REG05_MTLBASE 0x03
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#define REG06_SCANMOD 0xe0
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#define REG06S_SCANMOD 5
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#define REG06_PWRBIT 0x10
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#define REG06_GAIN4 0x08
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#define REG06_OPTEST 0x07
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#define REG07_SRAMSEL 0x08
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#define REG07_FASTDMA 0x04
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#define REG07_DMASEL 0x02
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#define REG07_DMARDWR 0x01
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#define REG08_DECFLAG 0x40
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#define REG08_GMMFFR 0x20
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#define REG08_GMMFFG 0x10
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#define REG08_GMMFFB 0x08
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#define REG08_GMMZR 0x04
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#define REG08_GMMZG 0x02
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#define REG08_GMMZB 0x01
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#define REG09_MCNTSET 0xc0
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#define REG09_CLKSET 0x30
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#define REG09_BACKSCAN 0x08
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#define REG09_ENHANCE 0x04
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#define REG09_SHORTTG 0x02
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#define REG09_NWAIT 0x01
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#define REG09S_MCNTSET 6
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#define REG09S_CLKSET 4
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#define REG0A_SRAMBUF 0x01
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#define REG0D_CLRLNCNT 0x01
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#define REG16_CTRLHI 0x80
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#define REG16_TOSHIBA 0x40
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#define REG16_TGINV 0x20
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#define REG16_CK1INV 0x10
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#define REG16_CK2INV 0x08
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#define REG16_CTRLINV 0x04
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#define REG16_CKDIS 0x02
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#define REG16_CTRLDIS 0x01
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#define REG17_TGMODE 0xc0
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#define REG17_TGMODE_NO_DUMMY 0x00
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#define REG17_TGMODE_REF 0x40
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#define REG17_TGMODE_XPA 0x80
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#define REG17_TGW 0x3f
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#define REG17S_TGW 0
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#define REG18_CNSET 0x80
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#define REG18_DCKSEL 0x60
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#define REG18_CKTOGGLE 0x10
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#define REG18_CKDELAY 0x0c
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#define REG18_CKSEL 0x03
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#define REG1A_MANUAL3 0x02
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#define REG1A_MANUAL1 0x01
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#define REG1A_CK4INV 0x08
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#define REG1A_CK3INV 0x04
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#define REG1A_LINECLP 0x02
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#define REG1C_TGTIME 0x07
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#define REG1D_CK4LOW 0x80
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#define REG1D_CK3LOW 0x40
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#define REG1D_CK1LOW 0x20
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#define REG1D_TGSHLD 0x1f
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#define REG1DS_TGSHLD 0
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#define REG1E_WDTIME 0xf0
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#define REG1ES_WDTIME 4
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#define REG1E_LINESEL 0x0f
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#define REG1ES_LINESEL 0
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#define REG40_HISPDFLG 0x04
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#define REG40_MOTMFLG 0x02
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#define REG40_DATAENB 0x01
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#define REG41_PWRBIT 0x80
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#define REG41_BUFEMPTY 0x40
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#define REG41_FEEDFSH 0x20
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#define REG41_SCANFSH 0x10
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#define REG41_HOMESNR 0x08
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#define REG41_LAMPSTS 0x04
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#define REG41_FEBUSY 0x02
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#define REG41_MOTORENB 0x01
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#define REG58_VSMP 0xf8
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#define REG58S_VSMP 3
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#define REG58_VSMPW 0x07
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#define REG58S_VSMPW 0
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#define REG59_BSMP 0xf8
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#define REG59S_BSMP 3
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#define REG59_BSMPW 0x07
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#define REG59S_BSMPW 0
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#define REG5A_ADCLKINV 0x80
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#define REG5A_RLCSEL 0x40
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#define REG5A_CDSREF 0x30
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#define REG5AS_CDSREF 4
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#define REG5A_RLC 0x0f
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#define REG5AS_RLC 0
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#define REG5E_DECSEL 0xe0
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#define REG5ES_DECSEL 5
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#define REG5E_STOPTIM 0x1f
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#define REG5ES_STOPTIM 0
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#define REG60_ZIMOD 0x1f
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#define REG61_Z1MOD 0xff
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#define REG62_Z1MOD 0xff
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#define REG63_Z2MOD 0x1f
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#define REG64_Z2MOD 0xff
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#define REG65_Z2MOD 0xff
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#define REG67_STEPSEL 0xc0
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#define REG67_FULLSTEP 0x00
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#define REG67_HALFSTEP 0x40
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#define REG67_QUATERSTEP 0x80
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#define REG67_MTRPWM 0x3f
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#define REG68_FSTPSEL 0xc0
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#define REG68_FULLSTEP 0x00
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#define REG68_HALFSTEP 0x40
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#define REG68_QUATERSTEP 0x80
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#define REG68_FASTPWM 0x3f
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#define REG6B_MULTFILM 0x80
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#define REG6B_GPOM13 0x40
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#define REG6B_GPOM12 0x20
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#define REG6B_GPOM11 0x10
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#define REG6B_GPO18 0x02
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#define REG6B_GPO17 0x01
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#define REG6C_GPIOH 0xff
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#define REG6C_GPIOL 0xff
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#define REG87_LEDADD 0x04
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enum
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{
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reg_0x01 = 0,
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reg_0x02,
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reg_0x03,
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reg_0x04,
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reg_0x05,
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reg_0x06,
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reg_0x07,
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reg_0x08,
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reg_0x09,
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reg_0x0a,
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reg_0x10,
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reg_0x11,
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reg_0x12,
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reg_0x13,
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reg_0x14,
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reg_0x15,
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reg_0x16,
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reg_0x17,
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reg_0x18,
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reg_0x19,
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reg_0x1a,
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reg_0x1b,
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reg_0x1c,
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reg_0x1d,
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reg_0x1e,
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reg_0x1f,
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reg_0x20,
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reg_0x21,
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reg_0x22,
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reg_0x23,
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reg_0x24,
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reg_0x25,
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reg_0x26,
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reg_0x27,
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reg_0x29,
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reg_0x2c,
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reg_0x2d,
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reg_0x2e,
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reg_0x2f,
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reg_0x30,
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reg_0x31,
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reg_0x32,
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reg_0x33,
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reg_0x34,
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reg_0x35,
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reg_0x36,
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reg_0x37,
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reg_0x38,
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reg_0x39,
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reg_0x3d,
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reg_0x3e,
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reg_0x3f,
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reg_0x52,
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reg_0x53,
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reg_0x54,
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reg_0x55,
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reg_0x56,
|
|
|
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|
|
reg_0x57,
|
|
|
|
|
|
reg_0x58,
|
|
|
|
|
|
reg_0x59,
|
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|
|
|
|
reg_0x5a,
|
|
|
|
|
|
|
|
|
|
|
|
reg_0x5d,
|
|
|
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|
|
reg_0x5e,
|
|
|
|
|
|
reg_0x5f,
|
|
|
|
|
|
reg_0x60,
|
|
|
|
|
|
reg_0x61,
|
|
|
|
|
|
reg_0x62,
|
|
|
|
|
|
reg_0x63,
|
|
|
|
|
|
reg_0x64,
|
|
|
|
|
|
reg_0x65,
|
|
|
|
|
|
reg_0x66,
|
|
|
|
|
|
reg_0x67,
|
|
|
|
|
|
reg_0x68,
|
|
|
|
|
|
reg_0x69,
|
|
|
|
|
|
reg_0x6a,
|
|
|
|
|
|
reg_0x6b,
|
|
|
|
|
|
reg_0x6c,
|
|
|
|
|
|
reg_0x6d,
|
|
|
|
|
|
reg_0x6e,
|
|
|
|
|
|
reg_0x6f,
|
|
|
|
|
|
reg_0x70,
|
|
|
|
|
|
reg_0x71,
|
|
|
|
|
|
reg_0x72,
|
|
|
|
|
|
reg_0x73,
|
|
|
|
|
|
reg_0x74,
|
|
|
|
|
|
reg_0x75,
|
|
|
|
|
|
reg_0x76,
|
|
|
|
|
|
reg_0x77,
|
|
|
|
|
|
reg_0x78,
|
|
|
|
|
|
reg_0x79,
|
|
|
|
|
|
reg_0x7a,
|
|
|
|
|
|
reg_0x7b,
|
|
|
|
|
|
reg_0x7c,
|
|
|
|
|
|
reg_0x7d,
|
|
|
|
|
|
reg_0x7e,
|
|
|
|
|
|
reg_0x7f,
|
|
|
|
|
|
reg_0x80,
|
|
|
|
|
|
reg_0x81,
|
|
|
|
|
|
reg_0x82,
|
|
|
|
|
|
reg_0x83,
|
|
|
|
|
|
reg_0x84,
|
|
|
|
|
|
reg_0x85,
|
|
|
|
|
|
reg_0x86,
|
|
|
|
|
|
reg_0x87,
|
|
|
|
|
|
GENESYS_GL841_MAX_REGS
|
|
|
|
|
|
};
|
