kopia lustrzana https://github.com/piotr022/rf96
new modifications
Piotr
rodzic
5bd2310df5
commit
4da1addbbe
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@ -27,6 +27,9 @@ void clockInit();
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**
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**===========================================================================
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*/
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uint8_t rssi_u8 = 0;
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rf96_config conf;
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int main(void)
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{
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clockInit();
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@ -40,13 +43,12 @@ SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PB; //przypisanie szyny B do EXTI0
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EXTI->IMR |= EXTI_IMR_MR0;
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EXTI->FTSR |= EXTI_FTSR_TR0;
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/////////////////////////////////////for intterupt enf
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conf.freqency_u32 = 433000000UL;
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rf_set_params(&conf);
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//spiWrite(0x06,0x64);
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//spiWrite(0x07,0xC0);
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//spiWrite(0x08,0x11);
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uint32_t freq_u32 =0;
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uint8_t rssi_u8 = 0;
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spiWrite(0x06,0x64);
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spiWrite(0x07,0xC0);
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spiWrite(0x08,0x11);
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freq_u32 = (spiRead(0x08) |
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(spiRead(0x07) << 8) |
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(spiRead(0x06) << 16) ) * (float)61.035;
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@ -62,15 +64,22 @@ spiWrite(RegPreambleLsb, 40);
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spiWrite(RegPaRamp, (0x9 | (0b01 << 5)));
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spiWrite(RegDioMapping1, (0b01 << 6)); //enabling preamble detect pn DIO0
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spiWrite(RegDioMapping2, 0b1); //setting to preamble detect
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//spiWrite(RegFifoThresh, 0x80);
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//spiWrite(RegSyncConfig, (spiRead(RegSyncConfig) & 0b00111111));
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//while(!(spiRead(RegOpMode) & FSK_SBY_MODE)){};
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spiWrite(RegRxConfig, 0b00011110); //setting rxtrigger to preable detect
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//and enabling agc
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spiWrite(RegPacketConfig1,0b10000000);
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spiWrite(RegSyncConfig,0b00001000);
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spiWrite(RegOpMode, FSK_SBY_MODE);
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//spiWrite(LR_RegFifoAddrPtr, spiRead(LR_RegFifoTxBaseAddr) ); //0x80
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spiWrite(RegSeqConfig1,0b10000110);
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spiWrite(RegSeqConfig2,0b01010010);
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spiWrite(RegOpMode,FSK_RX_MODE);
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int iii;//spiWrite(LR_RegFifoAddrPtr, spiRead(LR_RegFifoTxBaseAddr) ); //0x80
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//spiWrite(RegOpMode,FSK_RX_MODE);
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//SysTick_Config(8000000);
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NVIC_EnableIRQ(EXTI0_IRQn);
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while (1)
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@ -183,6 +192,9 @@ __attribute__ ((interrupt)) void EXTI0_IRQHandler(void)
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{
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if(EXTI->PR & EXTI_PR_PR0){
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EXTI->PR = EXTI_PR_PR0;
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uint8_t test[16];
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for(int j=0; j <16; j++)
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test[j]=spiRead(RegFIFO);
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printMsg("RSSI: %i, IRQ1 %x, IRQ2 %x\n",(-1*spiRead(0x11)/2),spiRead(RegIrqFlags1),spiRead(RegIrqFlags2));
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}
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}
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@ -14,7 +14,13 @@
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void rf_set_params(rf96_config * _conf)
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{
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uint32_t val = (_conf->freqency_u32) / F_STEP;
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spiWrite(RegFreqLsb, val & 0xFF);
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spiWrite(RegFreqMid, (val >> 8) & 0xFF);
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spiWrite(RegFreqMsb, (val >> 16) & 0xFF);
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}
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@ -12,7 +12,7 @@
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#define SX1278_MAX_PACKET 256
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#define SX1278_DEFAULT_TIMEOUT 3000
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#define F_STEP 61.035F
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/********************LoRa mode***************************/
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#define LR_RegFifo 0x00
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// Common settings
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@ -70,10 +70,6 @@
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/********************FSK/ook mode***************************/
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#define FSK_SBY_MODE 0b00001001
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#define FSK_TX_MODE 0b00001011
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#define FSK_RX_MODE 0b00001101
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#define FSK_SLEEP_MODE 0b00001000
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//registers
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@ -145,75 +141,18 @@
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#define RegPaDac 0x4d
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#define RegBitRateFrac 0x5d
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//values for OpMode register
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#define FSK_SBY_MODE 0b00001001
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#define FSK_TX_MODE 0b00001011
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#define FSK_RX_MODE 0b00001101
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#define FSK_SLEEP_MODE 0b00001000
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typedef struct{
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uint32_t freqency_u32;
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//
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//#define FSK_SLEEP_MODE 0x00
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//#define FSK_STANDBY_MODE 0x01
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//#define FSK_TX_MODE 0x03
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//#define FSK_RX_MODE 0x05
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//
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//
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}rf96_config;
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/**********************************************************
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**Parameter table define
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**********************************************************/
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#define SX1278_433MHZ 0
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static const uint8_t SX1278_Frequency[1][3] = { { 0x6C, 0x80, 0x00 }, //434MHz
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};
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#define SX1278_POWER_20DBM 0
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#define SX1278_POWER_17DBM 1
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#define SX1278_POWER_14DBM 2
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#define SX1278_POWER_11DBM 3
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static const uint8_t SX1278_Power[4] = { 0xFF, //20dbm
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0xFC, //17dbm
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0xF9, //14dbm
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0xF6, //11dbm
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};
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#define SX1278_LORA_SF_6 0
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#define SX1278_LORA_SF_7 1
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#define SX1278_LORA_SF_8 2
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#define SX1278_LORA_SF_9 3
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#define SX1278_LORA_SF_10 4
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#define SX1278_LORA_SF_11 5
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#define SX1278_LORA_SF_12 6
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static const uint8_t SX1278_SpreadFactor[7] = { 6, 7, 8, 9, 10, 11, 12 };
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#define SX1278_LORA_BW_7_8KHZ 0
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#define SX1278_LORA_BW_10_4KHZ 1
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#define SX1278_LORA_BW_15_6KHZ 2
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#define SX1278_LORA_BW_20_8KHZ 3
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#define SX1278_LORA_BW_31_2KHZ 4
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#define SX1278_LORA_BW_41_7KHZ 5
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#define SX1278_LORA_BW_62_5KHZ 6
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#define SX1278_LORA_BW_125KHZ 7
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#define SX1278_LORA_BW_250KHZ 8
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#define SX1278_LORA_BW_500KHZ 9
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static const uint8_t SX1278_LoRaBandwidth[10] = { 0, // 7.8KHz,
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1, // 10.4KHz,
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2, // 15.6KHz,
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3, // 20.8KHz,
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4, // 31.2KHz,
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5, // 41.7KHz,
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6, // 62.5KHz,
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7, // 125.0KHz,
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8, // 250.0KHz,
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9 // 500.0KHz
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};
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void rf_set_params(rf96_config * _conf);
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#endif /* RF96_H_ */
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