kopia lustrzana https://github.com/dl9rdz/rdz_ttgo_sonde
281 wiersze
8.7 KiB
C++
281 wiersze
8.7 KiB
C++
/*
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* Functions for using SX127x in FSK mode (mainly receive)
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* Copyright (C) 2019 Hansi Reiser, dl9rdz
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*
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* Partially based on the SX1278 libraray for managing Semtech modules
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* Copyright (C) 2015 Wireless Open Source
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* http://wirelessopensource.com
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*
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* SPDX-License-Identifier: LGPL-2.1+
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*/
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#ifndef SX1278FSK_h
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#define SX1278FSK_h
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/******************************************************************************
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* Includes
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******************************************************************************/
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#include <stdlib.h>
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#include <stdint.h>
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#include <Arduino.h>
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#include <SPI.h>
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#ifndef inttypes_h
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#include <inttypes.h>
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#endif
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/******************************************************************************
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* Definitions & Declarations
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*****************************************************************************/
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#define SX127X_CRYSTAL_FREQ 32000000
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#define SX127X_FSTEP (SX127X_CRYSTAL_FREQ*1.0/(1<<19))
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#define SX1278FSK_debug_mode 0
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//! MACROS //
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#define bitRead(value, bit) (((value) >> (bit)) & 0x01) // read a bit
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#define bitSet(value, bit) ((value) |= (1UL << (bit))) // set bit to '1'
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#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) // set bit to '0'
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//! REGISTERS //
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// FSK Commun LORA
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#define REG_FIFO 0x00
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#define REG_OP_MODE 0x01
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#define REG_BITRATE_MSB 0x02
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#define REG_BITRATE_LSB 0x03
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#define REG_FDEV_MSB 0x04
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#define REG_FDEV_LSB 0x05
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define REG_PA_CONFIG 0x09
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#define REG_PA_RAMP 0x0A
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#define REG_OCP 0x0B
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#define REG_LNA 0x0C
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#define REG_RX_CONFIG 0x0D
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#define REG_FIFO_ADDR_PTR 0x0D
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#define REG_RSSI_CONFIG 0x0E
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#define REG_FIFO_TX_BASE_ADDR 0x0E
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#define REG_RSSI_COLLISION 0x0F
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#define REG_FIFO_RX_BASE_ADDR 0x0F
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#define REG_RSSI_THRESH 0x10
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#define REG_FIFO_RX_CURRENT_ADDR 0x10
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#define REG_RSSI_VALUE_FSK 0x11
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#define REG_IRQ_FLAGS_MASK 0x11
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#define REG_RX_BW 0x12
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#define REG_IRQ_FLAGS 0x12
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#define REG_AFC_BW 0x13
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#define REG_RX_NB_BYTES 0x13
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#define REG_OOK_PEAK 0x14
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#define REG_RX_HEADER_CNT_VALUE_MSB 0x14
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#define REG_OOK_FIX 0x15
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#define REG_RX_HEADER_CNT_VALUE_LSB 0x15
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#define REG_OOK_AVG 0x16
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#define REG_RX_PACKET_CNT_VALUE_MSB 0x16
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#define REG_RX_PACKET_CNT_VALUE_LSB 0x17
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#define REG_MODEM_STAT 0x18
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#define REG_PKT_SNR_VALUE 0x19
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#define REG_AFC_FEI 0x1A
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#define REG_PKT_RSSI_VALUE 0x1A
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#define REG_AFC_MSB 0x1B
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#define REG_RSSI_VALUE_LORA 0x1B
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#define REG_AFC_LSB 0x1C
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#define REG_HOP_CHANNEL 0x1C
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#define REG_FEI_MSB 0x1D
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#define REG_MODEM_CONFIG1 0x1D
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#define REG_FEI_LSB 0x1E
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#define REG_MODEM_CONFIG2 0x1E
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#define REG_PREAMBLE_DETECT 0x1F
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#define REG_SYMB_TIMEOUT_LSB 0x1F
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#define REG_RX_TIMEOUT1 0x20
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#define REG_PREAMBLE_MSB_LORA 0x20
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#define REG_RX_TIMEOUT2 0x21
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#define REG_PREAMBLE_LSB_LORA 0x21
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#define REG_RX_TIMEOUT3 0x22
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#define REG_PAYLOAD_LENGTH_LORA 0x22
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#define REG_RX_DELAY 0x23
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#define REG_MAX_PAYLOAD_LENGTH 0x23
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#define REG_OSC 0x24
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#define REG_HOP_PERIOD 0x24
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#define REG_PREAMBLE_MSB_FSK 0x25
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#define REG_FIFO_RX_BYTE_ADDR 0x25
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#define REG_PREAMBLE_LSB_FSK 0x26
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#define REG_MODEM_CONFIG3 0x26
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#define REG_SYNC_CONFIG 0x27
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#define REG_SYNC_VALUE1 0x28
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#define REG_LORA_FEI_MSB 0x28
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#define REG_SYNC_VALUE2 0x29
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#define REG_LORA_FEI_MID 0x29
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#define REG_SYNC_VALUE3 0x2A
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#define REG_LORA_FEI_LSB 0x2A
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#define REG_SYNC_VALUE4 0x2B
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#define REG_SYNC_VALUE5 0x2C
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#define REG_RSSI_WIDEBAND 0x2C
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#define REG_SYNC_VALUE6 0x2D
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#define REG_SYNC_VALUE7 0x2E
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#define REG_SYNC_VALUE8 0x2F
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#define REG_PACKET_CONFIG1 0x30
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#define REG_PACKET_CONFIG2 0x31
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#define REG_DETECT_OPTIMIZE 0x31
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#define REG_PAYLOAD_LENGTH_FSK 0x32
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#define REG_NODE_ADRS 0x33
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#define REG_INVERT_IQ 0x33
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#define REG_BROADCAST_ADRS 0x34
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#define REG_FIFO_THRESH 0x35
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#define REG_SEQ_CONFIG1 0x36
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#define REG_SEQ_CONFIG2 0x37
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#define REG_DETECTION_THRESHOLD 0x37
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#define REG_TIMER_RESOL 0x38
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#define REG_TIMER1_COEF 0x39
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#define REG_SYNC_WORD 0x39
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#define REG_TIMER2_COEF 0x3A
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#define REG_IMAGE_CAL 0x3B
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#define REG_TEMP 0x3C
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#define REG_LOW_BAT 0x3D
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#define REG_IRQ_FLAGS1 0x3E
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#define REG_IRQ_FLAGS2 0x3F
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#define REG_DIO_MAPPING1 0x40
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#define REG_DIO_MAPPING2 0x41
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#define REG_VERSION 0x42
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#define REG_PLL_HOP 0x44
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#define REG_TCXO 0x4B
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#define REG_PA_DAC 0x4D
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#define REG_FORMER_TEMP 0x5B
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#define REG_BIT_RATE_FRAC 0x5D
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#define REG_AGC_REF 0x61
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#define REG_AGC_THRESH1 0x62
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#define REG_AGC_THRESH2 0x63
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#define REG_AGC_THRESH3 0x64
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#define REG_PLL 0x70
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//FSK MODES:
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const uint8_t FSK_SLEEP_MODE = 0x00;
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const uint8_t FSK_STANDBY_MODE = 0x01;
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const uint8_t FSK_TX_MODE = 0x03;
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const uint8_t FSK_RX_MODE = 0x05;
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/******************************************************************************
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* SX1278FSK Class
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* Functions and variables for managing SX127x transceiver chips in FSK mode,
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* mainly for receiving radiosonde transmissions
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******************************************************************************/
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class SX1278FSK
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{
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public:
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// class constructor
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SX1278FSK();
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void setup(xSemaphoreHandle lock);
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// Turn on SX1278 module (return 0 on sucess, 1 otherwise)
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uint8_t ON();
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// Turn off SX1278 module
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void OFF();
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// Read internal register
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byte readRegister(byte address);
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// Write internal register
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void writeRegister(byte address, byte data);
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// Clear IRQ flags
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void clearIRQFlags();
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// Activate FSK mode (return 0 on success, 1 otherwise)
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uint8_t setFSK();
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// Configures bitrate register (closest approximation to requested bitrate)
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uint8_t setBitrate(float bps);
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float getBitrate();
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// Configures RX bandwidth (next largest supported bandwith if exact value not possible)
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uint8_t setRxBandwidth(float bps);
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float getRxBandwidth();
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// Configures AFC bandwidth (next largest supported bandwith if exact value not possible)
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uint8_t setAFCBandwidth(float bps);
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float getAFCBandwidth();
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// Configures RX frequency (closest approximation to requested frequency)
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uint8_t setFrequency(float freq);
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float getFrequency();
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int getLNAGain();
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uint8_t setLNAGain(int gain);
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uint8_t getRxConf();
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uint8_t setRxConf(uint8_t conf);
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uint8_t setSyncConf(uint8_t conf, int len, const uint8_t *syncpattern);
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uint8_t getSyncConf();
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uint8_t setPreambleDetect(uint8_t conf);
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uint8_t getPreambleDetect();
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uint8_t setPacketConfig(uint8_t conf1, uint8_t conf2);
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uint16_t getPacketConfig();
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// Get configured preamble length (used for TX only?)
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uint16_t getPreambleLength();
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// Sets the preamble length.
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uint8_t setPreambleLength(uint16_t l);
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// Gets the payload length (expected length for receive)
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int getPayloadLength();
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uint8_t setPayloadLength(int len);
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// Get current RSSI value
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int16_t getRSSI();
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// Get current FEI (frequency error indication) value
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int32_t getFEI();
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// Get current AFC value
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int32_t getAFC();
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uint16_t getRawAFC();
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void setRawAFC(uint16_t afc);
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// Get the maximum current supply by the module.
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int getMaxCurrent();
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// Set the maximum current supply by the module.
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int8_t setMaxCurrent(uint8_t rate);
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// Put the module in reception mode.
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//return '0' on success, '1' otherwise
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uint8_t receive();
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// Receive a packet
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uint8_t receivePacketTimeout(uint32_t wait, byte *data);
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xSemaphoreHandle _lock = NULL;
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#if 0
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//! It gets the internal temperature of the module.
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/*!
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It stores in global '_temp' variable the module temperature.
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\return '0' on success, '1' otherwise
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*/
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uint8_t getTemp();
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//! It prints the registers related to RX via USB
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/*!
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* \return void
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*/
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void showRxRegisters();
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#endif
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};
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extern SX1278FSK sx1278;
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#endif
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