kopia lustrzana https://github.com/r-burg/rbfilter
145 wiersze
2.8 KiB
Plaintext
145 wiersze
2.8 KiB
Plaintext
v 20130925 2
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C 40400 47800 1 0 0 resistor-2.sym
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{
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T 40800 48150 5 10 0 0 0 0 1
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device=RESISTOR
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T 40600 48100 5 10 1 1 0 0 1
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refdes=R1
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T 40600 47800 5 10 0 1 0 0 1
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value=12.5k
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}
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C 44300 48700 1 0 0 resistor-2.sym
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{
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T 44700 49050 5 10 0 0 0 0 1
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device=RESISTOR
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T 44500 49000 5 10 1 1 0 0 1
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refdes=R3
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T 44500 48700 5 10 0 1 0 0 1
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value=38.5k
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}
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C 43800 46200 1 90 0 resistor-2.sym
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{
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T 43450 46600 5 10 0 0 90 0 1
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device=RESISTOR
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T 43500 46400 5 10 1 1 90 0 1
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refdes=R2
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T 43800 46200 5 10 1 1 0 0 1
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value=12.5k
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}
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C 42600 47700 1 0 0 capacitor-1.sym
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{
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T 42800 48400 5 10 0 0 0 0 1
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device=CAPACITOR
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T 42800 48200 5 10 1 1 0 0 1
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refdes=C2
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T 42800 48600 5 10 0 0 0 0 1
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symversion=0.1
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T 42600 47500 5 10 0 1 0 0 1
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value=0.083117uF
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}
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C 42100 46300 1 90 0 capacitor-1.sym
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{
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T 41400 46500 5 10 0 0 90 0 1
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device=CAPACITOR
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T 41600 46500 5 10 1 1 90 0 1
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refdes=C1
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T 41200 46500 5 10 0 0 90 0 1
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symversion=0.1
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T 42000 46500 5 10 0 1 0 0 1
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value=0.05uF
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}
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N 41300 47900 42600 47900 4
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N 43500 47900 45400 47900 4
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N 40300 45400 49000 45400 4
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N 41900 47200 41900 47900 4
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N 43700 47100 43700 47900 4
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N 41900 46300 41900 45400 4
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N 43700 46200 43700 45400 4
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N 44300 48800 42200 48800 4
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N 42200 48800 42200 47900 4
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N 46400 47700 49000 47700 4
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{
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T 48500 47800 5 10 1 1 0 0 1
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netname=Vout
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}
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N 45200 48800 47000 48800 4
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N 47000 48800 47000 47700 4
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C 47500 46600 1 90 0 resistor-2.sym
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{
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T 47150 47000 5 10 0 0 90 0 1
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device=RESISTOR
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T 47200 46800 5 10 1 1 90 0 1
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refdes=Rb
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T 47500 46600 5 10 1 1 0 0 1
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value=4k
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}
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C 46300 45500 1 90 0 resistor-2.sym
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{
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T 45950 45900 5 10 0 0 90 0 1
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device=RESISTOR
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T 46000 45700 5 10 1 1 90 0 1
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refdes=Ra
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T 46300 45500 5 10 1 1 0 0 1
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value=1k
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}
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N 47400 47500 47400 47700 4
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N 45400 47500 45300 47500 4
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N 45300 47500 45300 46500 4
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N 45300 46500 47400 46500 4
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N 46200 46400 46200 46500 4
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N 46200 45500 46200 45400 4
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C 45400 47300 1 0 0 aop-spice-1.sym
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{
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T 46450 47450 5 8 0 0 0 0 1
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device=AOP-Standard
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T 46100 48100 5 10 1 1 0 0 1
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refdes=U1
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}
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N 47400 46500 47400 46600 4
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C 40100 46000 1 0 0 vpulse-1.sym
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{
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T 40800 46650 5 10 1 1 0 0 1
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refdes=V1
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T 40800 46850 5 10 0 0 0 0 1
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device=vpulse
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T 40800 47050 5 10 0 0 0 0 1
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footprint=none
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T 40100 45750 5 10 0 1 0 0 1
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value=pulse 0 1 10n 10n 100n 1u 2u
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}
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C 44300 45900 1 0 0 vdc-1.sym
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{
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T 45000 46550 5 10 1 1 0 0 1
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refdes=V2
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T 45000 46750 5 10 0 0 0 0 1
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device=VOLTAGE_SOURCE
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T 45000 46950 5 10 0 0 0 0 1
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footprint=none
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T 45000 46350 5 10 1 1 0 0 1
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value=DC 12V
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}
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C 47900 45900 1 0 0 vdc-1.sym
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{
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T 48600 46550 5 10 1 1 0 0 1
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refdes=V3
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T 48600 46750 5 10 0 0 0 0 1
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device=VOLTAGE_SOURCE
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T 48600 46950 5 10 0 0 0 0 1
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footprint=none
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T 48600 46350 5 10 1 1 0 0 1
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value=DC -12V
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}
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N 44600 45900 44600 45400 4
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N 44600 47100 45900 47100 4
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N 45900 47100 45900 47300 4
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N 48200 47100 48200 48400 4
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N 48200 48400 45900 48400 4
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N 45900 48400 45900 48100 4
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N 48200 45900 48200 45400 4
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N 40400 47900 40400 47200 4
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{
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T 40400 47400 5 10 1 1 0 0 1
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netname=Vin
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}
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N 40400 46000 40400 45400 4
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