v 20130925 2
C 42300 47800 1 0 0 resistor-2.sym
{
T 42700 48150 5 10 0 0 0 0 1
device=RESISTOR
T 42500 48100 5 10 1 1 0 0 1
refdes=R1
}
C 44300 48700 1 0 0 resistor-2.sym
{
T 44700 49050 5 10 0 0 0 0 1
device=RESISTOR
T 44500 49000 5 10 1 1 0 0 1
refdes=R3
}
C 44900 46200 1 90 0 resistor-2.sym
{
T 44550 46600 5 10 0 0 90 0 1
device=RESISTOR
T 44600 46400 5 10 1 1 90 0 1
refdes=R2
}
C 43800 47700 1 0 0 capacitor-1.sym
{
T 44000 48400 5 10 0 0 0 0 1
device=CAPACITOR
T 44000 48200 5 10 1 1 0 0 1
refdes=C2
T 44000 48600 5 10 0 0 0 0 1
symversion=0.1
}
C 43600 46300 1 90 0 capacitor-1.sym
{
T 42900 46500 5 10 0 0 90 0 1
device=CAPACITOR
T 43700 47000 5 10 1 1 180 0 1
refdes=C1
T 42700 46500 5 10 0 0 90 0 1
symversion=0.1
}
N 43200 47900 43800 47900 4
N 44700 47900 45400 47900 4
N 42000 45400 49000 45400 4
{
T 42100 45400 5 10 1 1 0 0 1
netname=Ground
}
N 43400 47200 43400 47900 4
N 44800 47100 44800 47900 4
N 43400 46300 43400 45400 4
N 44800 46200 44800 45400 4
N 44300 48800 43800 48800 4
N 43800 48800 43800 47900 4
N 46400 47700 49000 47700 4
{
T 48500 47800 5 10 1 1 0 0 1
netname=Vout
}
N 45200 48800 47000 48800 4
N 47000 48800 47000 47700 4
C 47500 46600 1 90 0 resistor-2.sym
{
T 47150 47000 5 10 0 0 90 0 1
device=RESISTOR
T 47200 46800 5 10 1 1 90 0 1
refdes=Rb
}
C 47300 45500 1 90 0 resistor-2.sym
{
T 46950 45900 5 10 0 0 90 0 1
device=RESISTOR
T 47000 45700 5 10 1 1 90 0 1
refdes=Ra
}
N 47400 47500 47400 47700 4
N 45400 47500 45300 47500 4
N 45300 47500 45300 46600 4
N 45300 46600 47400 46600 4
N 47200 46400 47200 46600 4
N 47200 45500 47200 45400 4
C 45400 47300 1 0 0 aop-spice-1.sym
{
T 46450 47450 5 8 0 0 0 0 1
device=AOP-Standard
T 46100 48100 5 10 1 1 0 0 1
refdes=U1
}
C 41700 46000 1 0 0 vpulse-1.sym
{
T 42400 46650 5 10 1 1 0 0 1
refdes=V1
T 42400 46850 5 10 0 0 0 0 1
device=vpulse
T 42400 47050 5 10 0 0 0 0 1
footprint=none
}
C 45600 45500 1 0 0 vdc-1.sym
{
T 46300 46150 5 10 1 1 0 0 1
refdes=V2
T 46300 46350 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 46300 46550 5 10 0 0 0 0 1
footprint=none
T 46300 45950 5 10 1 1 0 0 1
value=DC 12V
}
C 47900 45900 1 0 0 vdc-1.sym
{
T 48600 46550 5 10 1 1 0 0 1
refdes=V3
T 48600 46750 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 48600 46950 5 10 0 0 0 0 1
footprint=none
T 48600 46350 5 10 1 1 0 0 1
value=DC -12V
}
N 45900 45500 45900 45400 4
N 45900 46700 45900 47300 4
N 48200 47100 48200 48400 4
N 48200 48400 45900 48400 4
N 45900 48400 45900 48100 4
N 48200 45900 48200 45400 4
N 42300 47900 42000 47900 4
{
T 42000 47400 5 10 1 1 0 0 1
netname=Vin
}
N 42000 46000 42000 45400 4
N 42000 47900 42000 47200 4