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diff --git a/Circuit_diagrams/Cct.png b/Circuit_diagrams/Cct.png
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Binary files /dev/null and b/Circuit_diagrams/Cct.png differ
diff --git a/Circuit_diagrams/Clean b/Circuit_diagrams/Clean
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--- /dev/null
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diff --git a/Circuit_diagrams/DirectForm1.dxf b/Circuit_diagrams/DirectForm1.dxf
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+N 47400 47500 47400 47700 4
+N 45400 47500 45300 47500 4
+N 45300 47500 45300 46500 4
+N 45300 46500 47400 46500 4
+N 46200 46400 46200 46500 4
+N 46200 45500 46200 45400 4
+C 45400 47300 1 0 0 aop-spice-1.sym
+{
+T 46450 47450 5 8 0 0 0 0 1
+device=AOP-Standard
+T 46100 48100 5 10 1 1 0 0 1
+refdes=U1
+}
+N 47400 46500 47400 46600 4
+C 40100 46000 1 0 0 vpulse-1.sym
+{
+T 40800 46650 5 10 1 1 0 0 1
+refdes=V1
+T 40800 46850 5 10 0 0 0 0 1
+device=vpulse
+T 40800 47050 5 10 0 0 0 0 1
+footprint=none
+T 40100 45750 5 10 0 1 0 0 1
+value=pulse 0 1 10n 10n 100n 1u 2u
+}
+C 44300 45900 1 0 0 vdc-1.sym
+{
+T 45000 46550 5 10 1 1 0 0 1
+refdes=V2
+T 45000 46750 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 45000 46950 5 10 0 0 0 0 1
+footprint=none
+T 45000 46350 5 10 1 1 0 0 1
+value=DC 12V
+}
+C 47900 45900 1 0 0 vdc-1.sym
+{
+T 48600 46550 5 10 1 1 0 0 1
+refdes=V3
+T 48600 46750 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 48600 46950 5 10 0 0 0 0 1
+footprint=none
+T 48600 46350 5 10 1 1 0 0 1
+value=DC -12V
+}
+N 44600 45900 44600 45400 4
+N 44600 47100 45900 47100 4
+N 45900 47100 45900 47300 4
+N 48200 47100 48200 48400 4
+N 48200 48400 45900 48400 4
+N 45900 48400 45900 48100 4
+N 48200 45900 48200 45400 4
+N 40400 47900 40400 47200 4
+{
+T 40400 47400 5 10 1 1 0 0 1
+netname=Vin
+}
+N 40400 46000 40400 45400 4
diff --git a/Circuit_diagrams/band_pass_MF.png b/Circuit_diagrams/band_pass_MF.png
new file mode 100644
index 0000000..42f48b2
Binary files /dev/null and b/Circuit_diagrams/band_pass_MF.png differ
diff --git a/Circuit_diagrams/band_pass_MF.sch b/Circuit_diagrams/band_pass_MF.sch
new file mode 100644
index 0000000..5eb478b
--- /dev/null
+++ b/Circuit_diagrams/band_pass_MF.sch
@@ -0,0 +1,75 @@
+v 20200319 2
+C 40000 40000 0 0 0 title-B.sym
+C 44700 45900 1 0 0 resistor-2.sym
+{
+T 45100 46250 5 10 0 0 0 0 1
+device=RESISTOR
+T 44900 46200 5 10 1 1 0 0 1
+refdes=R1
+}
+C 46300 45800 1 0 0 capacitor-1.sym
+{
+T 46500 46500 5 10 0 0 0 0 1
+device=CAPACITOR
+T 46500 46300 5 10 1 1 0 0 1
+refdes=C2
+T 46500 46700 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 48000 45800 1 0 0 aop-std-1.sym
+{
+T 49050 45950 5 10 0 0 0 0 1
+device=AOP-Standard
+T 48700 45900 5 10 1 1 0 0 1
+refdes=U1
+T 49050 46550 5 10 0 0 0 0 1
+footprint=DIP8
+T 49050 46150 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 46300 46400 1 90 0 capacitor-1.sym
+{
+T 45600 46600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 45800 46600 5 10 1 1 90 0 1
+refdes=C1
+T 45400 46600 5 10 0 0 90 0 1
+symversion=0.1
+}
+C 47500 46400 1 90 0 resistor-2.sym
+{
+T 47150 46800 5 10 0 0 90 0 1
+device=RESISTOR
+T 47200 46600 5 10 1 1 90 0 1
+refdes=R2
+}
+C 43900 44700 1 0 0 vac-1.sym
+{
+T 44600 45350 5 10 1 1 0 0 1
+refdes=V1
+T 44600 45550 5 10 0 0 0 0 1
+device=vac
+T 44600 45750 5 10 0 0 0 0 1
+footprint=none
+T 44600 45150 5 10 1 1 0 0 1
+value=dc 0 ac 1
+}
+N 44200 44700 44200 44500 4
+N 43000 44500 50000 44500 4
+N 44200 45900 44200 46000 4
+N 44200 46000 44700 46000 4
+N 45600 46000 46300 46000 4
+N 47200 46000 48000 46000 4
+N 46100 46400 46100 46000 4
+N 46100 47300 46100 47700 4
+N 46100 47700 49500 47700 4
+N 49000 46200 50000 46200 4
+N 49500 47700 49500 46200 4
+N 47400 47300 47400 47700 4
+N 47400 46400 47400 46000 4
+N 48000 46400 47800 46400 4
+N 47800 46400 47800 44500 4
+C 48700 45500 1 180 0 12V-minus-1.sym
+C 48300 46900 1 0 0 12V-plus-1.sym
+N 48500 46900 48500 46600 4
+N 48500 45800 48500 45500 4
diff --git a/Circuit_diagrams/band_pass_SK.png b/Circuit_diagrams/band_pass_SK.png
new file mode 100644
index 0000000..bc5d06b
Binary files /dev/null and b/Circuit_diagrams/band_pass_SK.png differ
diff --git a/Circuit_diagrams/band_pass_SK.sch b/Circuit_diagrams/band_pass_SK.sch
new file mode 100644
index 0000000..7a9b1c5
--- /dev/null
+++ b/Circuit_diagrams/band_pass_SK.sch
@@ -0,0 +1,131 @@
+v 20130925 2
+C 42300 47800 1 0 0 resistor-2.sym
+{
+T 42700 48150 5 10 0 0 0 0 1
+device=RESISTOR
+T 42500 48100 5 10 1 1 0 0 1
+refdes=R1
+}
+C 44300 48700 1 0 0 resistor-2.sym
+{
+T 44700 49050 5 10 0 0 0 0 1
+device=RESISTOR
+T 44500 49000 5 10 1 1 0 0 1
+refdes=R3
+}
+C 44900 46200 1 90 0 resistor-2.sym
+{
+T 44550 46600 5 10 0 0 90 0 1
+device=RESISTOR
+T 44600 46400 5 10 1 1 90 0 1
+refdes=R2
+}
+C 43800 47700 1 0 0 capacitor-1.sym
+{
+T 44000 48400 5 10 0 0 0 0 1
+device=CAPACITOR
+T 44000 48200 5 10 1 1 0 0 1
+refdes=C2
+T 44000 48600 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 43600 46300 1 90 0 capacitor-1.sym
+{
+T 42900 46500 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43700 47000 5 10 1 1 180 0 1
+refdes=C1
+T 42700 46500 5 10 0 0 90 0 1
+symversion=0.1
+}
+N 43200 47900 43800 47900 4
+N 44700 47900 45400 47900 4
+N 42000 45400 49000 45400 4
+{
+T 42100 45400 5 10 1 1 0 0 1
+netname=Ground
+}
+N 43400 47200 43400 47900 4
+N 44800 47100 44800 47900 4
+N 43400 46300 43400 45400 4
+N 44800 46200 44800 45400 4
+N 44300 48800 43800 48800 4
+N 43800 48800 43800 47900 4
+N 46400 47700 49000 47700 4
+{
+T 48500 47800 5 10 1 1 0 0 1
+netname=Vout
+}
+N 45200 48800 47000 48800 4
+N 47000 48800 47000 47700 4
+C 47500 46600 1 90 0 resistor-2.sym
+{
+T 47150 47000 5 10 0 0 90 0 1
+device=RESISTOR
+T 47200 46800 5 10 1 1 90 0 1
+refdes=Rb
+}
+C 47300 45500 1 90 0 resistor-2.sym
+{
+T 46950 45900 5 10 0 0 90 0 1
+device=RESISTOR
+T 47000 45700 5 10 1 1 90 0 1
+refdes=Ra
+}
+N 47400 47500 47400 47700 4
+N 45400 47500 45300 47500 4
+N 45300 47500 45300 46600 4
+N 45300 46600 47400 46600 4
+N 47200 46400 47200 46600 4
+N 47200 45500 47200 45400 4
+C 45400 47300 1 0 0 aop-spice-1.sym
+{
+T 46450 47450 5 8 0 0 0 0 1
+device=AOP-Standard
+T 46100 48100 5 10 1 1 0 0 1
+refdes=U1
+}
+C 41700 46000 1 0 0 vpulse-1.sym
+{
+T 42400 46650 5 10 1 1 0 0 1
+refdes=V1
+T 42400 46850 5 10 0 0 0 0 1
+device=vpulse
+T 42400 47050 5 10 0 0 0 0 1
+footprint=none
+}
+C 45600 45500 1 0 0 vdc-1.sym
+{
+T 46300 46150 5 10 1 1 0 0 1
+refdes=V2
+T 46300 46350 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 46300 46550 5 10 0 0 0 0 1
+footprint=none
+T 46300 45950 5 10 1 1 0 0 1
+value=DC 12V
+}
+C 47900 45900 1 0 0 vdc-1.sym
+{
+T 48600 46550 5 10 1 1 0 0 1
+refdes=V3
+T 48600 46750 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 48600 46950 5 10 0 0 0 0 1
+footprint=none
+T 48600 46350 5 10 1 1 0 0 1
+value=DC -12V
+}
+N 45900 45500 45900 45400 4
+N 45900 46700 45900 47300 4
+N 48200 47100 48200 48400 4
+N 48200 48400 45900 48400 4
+N 45900 48400 45900 48100 4
+N 48200 45900 48200 45400 4
+N 42300 47900 42000 47900 4
+{
+T 42000 47400 5 10 1 1 0 0 1
+netname=Vin
+}
+N 42000 46000 42000 45400 4
+N 42000 47900 42000 47200 4
diff --git a/Circuit_diagrams/high_pass.sch b/Circuit_diagrams/high_pass.sch
new file mode 100644
index 0000000..69df146
--- /dev/null
+++ b/Circuit_diagrams/high_pass.sch
@@ -0,0 +1,128 @@
+v 20130925 2
+C 44300 48700 1 0 0 resistor-2.sym
+{
+T 44700 49050 5 10 0 0 0 0 1
+device=RESISTOR
+T 44500 49000 5 10 1 1 0 0 1
+refdes=R2
+}
+C 43800 46200 1 90 0 resistor-2.sym
+{
+T 43450 46600 5 10 0 0 90 0 1
+device=RESISTOR
+T 43500 46400 5 10 1 1 90 0 1
+refdes=R1
+}
+N 42000 47800 42600 47800 4
+N 43500 47800 45500 47800 4
+N 40300 45100 47900 45100 4
+{
+T 40300 45100 5 10 1 1 0 0 1
+netname=Gnd
+}
+N 43700 47100 43700 47800 4
+N 43700 46200 43700 45100 4
+N 44300 48800 42200 48800 4
+N 42200 48800 42200 47800 4
+N 46500 47600 47900 47600 4
+{
+T 47100 47700 5 10 1 1 0 0 1
+netname=Vout
+}
+N 45200 48800 47000 48800 4
+N 47000 48800 47000 47600 4
+C 47500 46500 1 90 0 resistor-2.sym
+{
+T 47150 46900 5 10 0 0 90 0 1
+device=RESISTOR
+T 47200 46700 5 10 1 1 90 0 1
+refdes=Ra
+}
+N 47400 47400 47400 47600 4
+N 45500 47400 45100 47400 4
+N 45100 47400 45100 46500 4
+N 45100 46500 47400 46500 4
+C 42000 48000 1 180 0 capacitor-1.sym
+{
+T 41800 47300 5 10 0 0 180 0 1
+device=CAPACITOR
+T 41800 47600 5 10 1 1 180 0 1
+refdes=C1
+T 41800 47100 5 10 0 0 180 0 1
+symversion=0.1
+}
+N 41100 47800 40300 47800 4
+{
+T 40500 47800 5 10 1 1 0 0 1
+netname=Vin
+}
+N 40300 47300 40300 47800 4
+N 40300 46100 40300 45100 4
+C 44100 45700 1 0 0 vdc-1.sym
+{
+T 44800 46350 5 10 1 1 0 0 1
+refdes=Vcc
+T 44800 46550 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 44800 46750 5 10 0 0 0 0 1
+footprint=none
+T 44800 46150 5 10 1 1 0 0 1
+value=DC 12V
+}
+N 44400 45700 44400 45100 4
+N 44400 46900 44400 48400 4
+N 44400 48400 46000 48400 4
+N 46000 48000 46000 48400 4
+C 45700 45200 1 0 0 vdc-1.sym
+{
+T 46400 45850 5 10 1 1 0 0 1
+refdes=Vss
+T 46400 46050 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 46400 46250 5 10 0 0 0 0 1
+footprint=none
+T 46400 45650 5 10 1 1 0 0 1
+value=DC -12V
+}
+C 40000 46100 1 0 0 vpulse-1.sym
+{
+T 40700 46750 5 10 1 1 0 0 1
+refdes=V1
+T 40700 46950 5 10 0 0 0 0 1
+device=vpulse
+T 40700 47150 5 10 0 0 0 0 1
+footprint=none
+}
+C 45500 47200 1 0 0 lm358-1.sym
+{
+T 46175 47800 5 10 0 0 0 0 1
+device=LM358/NS
+T 46200 48550 5 10 0 0 0 0 1
+footprint=DIP8
+T 45700 48100 5 10 1 1 0 0 1
+refdes=U1
+T 45500 47200 5 10 0 1 0 0 1
+value=LM358/NS
+}
+N 46000 47200 46000 46400 4
+C 47500 45300 1 90 0 resistor-2.sym
+{
+T 47150 45700 5 10 0 0 90 0 1
+device=RESISTOR
+T 47200 45500 5 10 1 1 90 0 1
+refdes=Rb
+}
+N 47400 46500 47400 46200 4
+N 47400 45300 47400 45100 4
+N 46000 45200 46000 45100 4
+T 46500 44600 9 10 1 0 0 0 1
+k = Rb/(Ra+Rb)
+C 43500 48000 1 180 0 capacitor-1.sym
+{
+T 43300 47300 5 10 0 0 180 0 1
+device=CAPACITOR
+T 43300 47600 5 10 1 1 180 0 1
+refdes=C2
+T 43300 47100 5 10 0 0 180 0 1
+symversion=0.1
+}
diff --git a/Circuit_diagrams/high_pass_MF.png b/Circuit_diagrams/high_pass_MF.png
new file mode 100644
index 0000000..b694a08
Binary files /dev/null and b/Circuit_diagrams/high_pass_MF.png differ
diff --git a/Circuit_diagrams/high_pass_SK.png b/Circuit_diagrams/high_pass_SK.png
new file mode 100644
index 0000000..0fbbb4a
Binary files /dev/null and b/Circuit_diagrams/high_pass_SK.png differ
diff --git a/Circuit_diagrams/low_pass.sch b/Circuit_diagrams/low_pass.sch
new file mode 100644
index 0000000..56b6534
--- /dev/null
+++ b/Circuit_diagrams/low_pass.sch
@@ -0,0 +1,85 @@
+v 20200319 2
+C 40000 40000 0 0 0 title-B.sym
+C 44700 46900 1 0 0 resistor-2.sym
+{
+T 45100 47250 5 10 0 0 0 0 1
+device=RESISTOR
+T 44900 47200 5 10 1 1 0 0 1
+refdes=R1
+}
+C 46400 46900 1 0 0 resistor-2.sym
+{
+T 46800 47250 5 10 0 0 0 0 1
+device=RESISTOR
+T 46600 47200 5 10 1 1 0 0 1
+refdes=R2
+}
+C 49100 45600 1 0 0 resistor-2.sym
+{
+T 49500 45950 5 10 0 0 0 0 1
+device=RESISTOR
+T 49300 45900 5 10 1 1 0 0 1
+refdes=R3
+}
+C 48300 46400 1 0 0 opamp-1.sym
+{
+T 49000 47200 5 10 0 0 0 0 1
+device=OPAMP
+T 49000 47000 5 10 1 1 0 0 1
+refdes=U1
+T 49000 47800 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 47800 45400 1 90 0 capacitor-1.sym
+{
+T 47100 45600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 47400 45700 5 10 1 1 180 0 1
+refdes=C1
+T 46900 45600 5 10 0 0 90 0 1
+symversion=0.1
+}
+C 47600 47800 1 0 0 capacitor-1.sym
+{
+T 47800 48500 5 10 0 0 0 0 1
+device=CAPACITOR
+T 47800 48300 5 10 1 1 0 0 1
+refdes=C2
+T 47800 48700 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 44500 45700 1 90 0 voltage-2.sym
+{
+T 43950 45800 5 10 0 0 90 0 1
+device=VOLTAGE_SOURCE
+T 44100 46100 5 10 1 1 180 0 1
+refdes=Vin
+}
+N 45600 47000 46400 47000 4
+N 47300 47000 48300 47000 4
+N 49300 46800 51200 46800 4
+N 47600 48000 46000 48000 4
+N 46000 48000 46000 47000 4
+N 48500 48000 50000 48000 4
+N 50000 48000 50000 46800 4
+N 47600 46300 47600 47000 4
+N 44300 45700 44300 45000 4
+N 44300 45000 51200 45000 4
+N 47600 45400 47600 45000 4
+N 48300 46600 48200 46600 4
+N 48200 46600 48200 45700 4
+N 48200 45700 49100 45700 4
+N 50000 45700 50300 45700 4
+N 50300 45700 50300 46800 4
+N 44300 46600 44300 47000 4
+N 44300 47000 44700 47000 4
+N 48500 47600 49100 47600 4
+N 48500 46000 49100 46000 4
+N 48800 47200 48800 47600 4
+N 48800 46400 48800 46000 4
+T 48600 47700 9 10 1 0 0 0 1
++Vs
+T 48900 46100 9 10 1 0 0 0 1
+-Vs
+T 48900 45300 9 10 1 0 0 0 1
+Let R3 = R1 + R2
diff --git a/Circuit_diagrams/low_pass_MF.png b/Circuit_diagrams/low_pass_MF.png
new file mode 100644
index 0000000..2f6a523
Binary files /dev/null and b/Circuit_diagrams/low_pass_MF.png differ
diff --git a/Circuit_diagrams/low_pass_SK.png b/Circuit_diagrams/low_pass_SK.png
new file mode 100644
index 0000000..d9e31cb
Binary files /dev/null and b/Circuit_diagrams/low_pass_SK.png differ