kopia lustrzana https://github.com/bristol-seds/pico-tracker
566 wiersze
21 KiB
C
566 wiersze
21 KiB
C
/**
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* SAM D20/D21/R21 TC - Timer Counter Driver
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*
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* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef TC_H_INCLUDED
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#define TC_H_INCLUDED
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/**
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* SAM D20/D21/R21 Timer/Counter Driver (TC)
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*
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* Module Overview
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*
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* The Timer/Counter (TC) module provides a set of timing and counting related
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* functionality, such as the generation of periodic waveforms, the capturing
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* of a periodic waveform's frequency/duty cycle, and software timekeeping for
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* periodic operations. TC modules can be configured to use an 8-, 16-, or
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* 32-bit counter size.
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*
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* This TC module for the SAM D20/D21/R21 is capable of the following functions:
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*
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* - Generation of PWM signals
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* - Generation of timestamps for events
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* - General time counting
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* - Waveform period capture
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* - Waveform frequency capture
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*
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* Functional Description
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*
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* Independent of the configured counter size, each TC module can be set up
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* in one of two different modes; capture and compare.
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*
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* In capture mode, the counter value is stored when a configurable event
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* occurs. This mode can be used to generate timestamps used in event capture,
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* or it can be used for the measurement of a periodic input signal's
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* frequency/duty cycle.
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*
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* In compare mode, the counter value is compared against one or more of the
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* configured channel compare values. When the counter value coincides with a
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* compare value an action can be taken automatically by the module, such as
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* generating an output event or toggling a pin when used for frequency or PWM
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* signal generation.
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*
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* Note: The connection of events between modules requires the use of
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* the SAM D20/D21/R21 Event System Driver (EVENTS) to route
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* output event of one module to the the input event of another.
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* For more information on event routing, refer to the event
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* driver documentation.
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*
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* Timer/Counter Size
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* Each timer module can be configured in one of three different counter
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* sizes; 8-, 16-, and 32-bits. The size of the counter determines the maximum
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* value it can count to before an overflow occurs and the count is reset back
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* to zero.
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*
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* When using the counter in 16- or 32-bit count mode, Compare Capture
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* register 0 (CC0) is used to store the period value when running in PWM
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* generation match mode.
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*
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* When using 32-bit counter size, two 16-bit counters are chained together
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* in a cascade formation. Even numbered TC modules (e.g. TC0, TC2) can be
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* configured as 32-bit counters. The odd numbered counters will act as slaves
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* to the even numbered masters, and will not be reconfigurable until the
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* master timer is disabled.
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*
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* Clock Settings
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*
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* Clock Selection
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* Each TC peripheral is clocked asynchronously to the
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* system clock by a GCLK (Generic Clock) channel. The GCLK channel
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* connects to any of the GCLK generators. The GCLK generators are
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* configured to use one of the available clock sources on the system
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* such as internal oscillator, external crystals etc.
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*
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* Prescaler
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* Each TC module in the SAM D20/D21/R21 has its own
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* individual clock prescaler, which can be used to divide the input
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* clock frequency used in the counter. This prescaler only scales the
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* clock used to provide clock pulses for the counter to count, and
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* does not affect the digital register interface portion of the
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* module, thus the timer registers will synchronized to the raw GCLK
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* frequency input to the module.
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*
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* As a result of this, when selecting a GCLK frequency and timer prescaler
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* value the user application should consider both the timer resolution
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* required and the synchronization frequency, to avoid lengthy
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* synchronization times of the module if a very slow GCLK frequency is fed
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* into the TC module. It is preferable to use a higher module GCLK frequency
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* as the input to the timer and prescale this down as much as possible to
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* obtain a suitable counter frequency in latency-sensitive applications.
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*
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* Reloading
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* Timer modules also contain a configurable reload action, used when a
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* re-trigger event occurs. Examples of a re-trigger event are the counter
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* reaching the max value when counting up, or when an event from the event
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* system tells the counter to re-trigger. The reload action determines if the
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* prescaler should be reset, and when this should happen. The counter will
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* always be reloaded with the value it is set to start counting from.
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*
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* <table>
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* <caption>TC module reload actions</caption>
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* <tr>
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* <th>Reload Action</th>
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* <th>Description</th>
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* </tr>
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* <tr>
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* <td>\ref TC_RELOAD_ACTION_GCLK </td>
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* <td>Reload TC counter value on next GCLK cycle. Leave prescaler
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* as-is.</td>
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* </tr>
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* <tr>
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* <td>\ref TC_RELOAD_ACTION_PRESC </td>
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* <td>Reloads TC counter value on next prescaler clock. Leave prescaler
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* as-is.</td>
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* </tr>
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* <tr>
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* <td> \ref TC_RELOAD_ACTION_RESYNC </td>
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* <td>Reload TC counter value on next GCLK cycle. Clear prescaler to
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* zero.</td>
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* </tr>
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* </table>
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*
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* The reload action to use will depend on the specific application being
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* implemented. One example is when an external trigger for a reload occurs; if
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* the TC uses the prescaler, the counter in the prescaler should not have a
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* value between zero and the division factor. The TC counter and the counter
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* in the prescaler should both start at zero. When the counter is set to
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* re-trigger when it reaches the max value on the other hand, this is not the
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* right option to use. In such a case it would be better if the prescaler is
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* left unaltered when the re-trigger happens, letting the counter reset on the
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* next GCLK cycle.
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*
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* Compare Match Operations
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* In compare match operation, Compare/Capture registers are used in comparison
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* with the counter value. When the timer's count value matches the value of a
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* compare channel, a user defined action can be taken.
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*
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* Basic Timer
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*
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* A Basic Timer is a simple application where compare match operations is used
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* to determine when a specific period has elapsed. In Basic Timer operations,
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* one or more values in the module's Compare/Capture registers are used to
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* specify the time (as a number of prescaled GCLK cycles) when an action should
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* be taken by the microcontroller. This can be an Interrupt Service Routine
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* (ISR), event generator via the event system, or a software flag that is
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* polled via the user application.
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*
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* Waveform Generation
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*
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* Waveform generation enables the TC module to generate square waves, or if
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* combined with an external passive low-pass filter, analog waveforms.
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*
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* Waveform Generation - PWM
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*
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* Pulse width modulation is a form of waveform generation and a signalling
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* technique that can be useful in many situations. When PWM mode is used,
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* a digital pulse train with a configurable frequency and duty cycle can be
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* generated by the TC module and output to a GPIO pin of the device.
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*
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* Often PWM is used to communicate a control or information parameter to an
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* external circuit or component. Differing impedances of the source generator
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* and sink receiver circuits is less of an issue when using PWM compared to
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* using an analog voltage value, as noise will not generally affect the
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* signal's integrity to a meaningful extent.
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*
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* Frequency Generation mode is in many ways identical to PWM
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* generation. However, in Frequency Generation a toggle only occurs
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* on the output when a match on a capture channels occurs. When the
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* match is made, the timer value is reset, resulting in a variable
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* frequency square wave with a fixed 50% duty cycle.
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*
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* Capture Operations
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*
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* In capture operations, any event from the event system or a pin change can
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* trigger a capture of the counter value. This captured counter value can be
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* used as a timestamp for the event, or it can be used in frequency and pulse
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* width capture.
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*
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* Capture Operations - Event
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*
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* Event capture is a simple use of the capture functionality,
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* designed to create timestamps for specific events. When the TC
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* module's input capture pin is externally toggled, the current timer
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* count value is copied into a buffered register which can then be
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* read out by the user application.
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*
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* Note that when performing any capture operation, there is a risk that the
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* counter reaches its top value (MAX) when counting up, or the bottom value
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* (zero) when counting down, before the capture event occurs. This can distort
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* the result, making event timestamps to appear shorter than reality; the
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* user application should check for timer overflow when reading a capture
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* result in order to detect this situation and perform an appropriate
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* adjustment.
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*
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* Before checking for a new capture, TC_STATUS_COUNT_OVERFLOW should
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* be checked. The response to an overflow error is left to the user
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* application, however it may be necessary to clear both the capture
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* overflow flag and the capture flag upon each capture reading.
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*
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* Capture Operations - Pulse Width
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*
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* Pulse Width Capture mode makes it possible to measure the pulse width and
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* period of PWM signals. This mode uses two capture channels of the counter.
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* This means that the counter module used for Pulse Width Capture can not be
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* used for any other purpose. There are two modes for pulse width capture;
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* Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture
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* channel 0 is used for storing the pulse width and capture channel 1 stores
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* the observed period. While in PPW mode, the roles of the two capture channels
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* is reversed.
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*
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* As in the above example it is necessary to poll on interrupt flags to see
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* if a new capture has happened and check that a capture overflow error has
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* not occurred.
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*
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* One-shot Mode
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*
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* TC modules can be configured into a one-shot mode. When configured in this
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* manner, starting the timer will cause it to count until the next overflow
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* or underflow condition before automatically halting, waiting to be manually
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* triggered by the user application software or an event signal from the event
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* system.
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*
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* Wave Generation Output Inversion
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*
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* The output of the wave generation can be inverted by hardware if desired,
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* resulting in the logically inverted value being output to the configured
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* device GPIO pin.
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*
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*
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* Special Considerations
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*
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* The number of capture compare registers in each TC module is dependent on
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* the specific SAM D20/D21/R21 device being used, and in some cases the counter size.
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*
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* The maximum amount of capture compare registers available in any SAM D20/D21/R21
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* device is two when running in 32-bit mode and four in 8-, and 16-bit modes.
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*/
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#include "samd20.h"
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#include "tc.h"
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#include <stdbool.h>
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/* Same number for 8-, 16- and 32-bit TC and all TC instances */
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#define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC8_NUM
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/**
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* TC status type
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*/
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enum tc_status_t {
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TC_STATUS_OK = 0,
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TC_STATUS_BUSY,
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TC_STATUS_DENIED
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};
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/**
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* TC error type
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*/
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enum tc_error_t {
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TC_ERROR_INVALID_ARG = 1,
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TC_ERROR_INVALID_STATE,
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TC_ERROR_INVALID_DEVICE,
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TC_ERROR_NO_32BIT_SLAVE_EXISTS
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};
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/**
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* Module status flags
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*/
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/** Timer channel 0 has matched against its compare value, or has captured a
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* new value.
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*/
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#define TC_STATUS_CHANNEL_0_MATCH (1UL << 0)
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/** Timer channel 1 has matched against its compare value, or has captured a
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* new value.
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*/
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#define TC_STATUS_CHANNEL_1_MATCH (1UL << 1)
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/** Timer register synchronization has completed, and the synchronized count
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* value may be read.
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*/
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#define TC_STATUS_SYNC_READY (1UL << 2)
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/** A new value was captured before the previous value was read, resulting in
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* lost data.
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*/
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#define TC_STATUS_CAPTURE_OVERFLOW (1UL << 3)
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/** The timer count value has overflowed from its maximum value to its minimum
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* when counting upward, or from its minimum value to its maximum when
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* counting downward.
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*/
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#define TC_STATUS_COUNT_OVERFLOW (1UL << 4)
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/**
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* Index of the compare capture channels
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*
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* This enum is used to specify which capture/compare channel to do
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* operations on.
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*/
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enum tc_compare_capture_channel {
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/** Index of compare capture channel 0 */
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TC_COMPARE_CAPTURE_CHANNEL_0,
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/** Index of compare capture channel 1 */
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TC_COMPARE_CAPTURE_CHANNEL_1,
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};
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/**
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* TC wave generation mode enum
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*
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* This enum is used to select which mode to run the wave
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* generation in.
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*/
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enum tc_wave_generation {
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/** Top is max, except in 8-bit counter size where it is the PER
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* register
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*/
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TC_WAVE_GENERATION_NORMAL_FREQ = TC_CTRLA_WAVEGEN_NFRQ,
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/** Top is CC0, except in 8-bit counter size where it is the PER
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* register
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*/
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TC_WAVE_GENERATION_MATCH_FREQ = TC_CTRLA_WAVEGEN_MFRQ,
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/** Top is max, except in 8-bit counter size where it is the PER
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* register
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*/
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TC_WAVE_GENERATION_NORMAL_PWM = TC_CTRLA_WAVEGEN_NPWM,
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/** Top is CC0, except in 8-bit counter size where it is the PER
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* register
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*/
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TC_WAVE_GENERATION_MATCH_PWM = TC_CTRLA_WAVEGEN_MPWM,
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};
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/**
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* Specifies if the counter is 8-, 16-, or 32-bits.
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*
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* This enum specifies the maximum value it is possible to count to.
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*/
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enum tc_counter_size {
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/** The counter's max value is 0xFF, the period register is
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* available to be used as top value.
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*/
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TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8,
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/** The counter's max value is 0xFFFF. There is no separate
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* period register, to modify top one of the capture compare
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* registers has to be used. This limits the amount of
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* available channels.
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*/
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TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16,
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/** The counter's max value is 0xFFFFFFFF. There is no separate
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* period register, to modify top one of the capture compare
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* registers has to be used. This limits the amount of
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* available channels.
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*/
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TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32,
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};
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/**
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* TC Counter reload action enum
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*
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* This enum specify how the counter and prescaler should reload.
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*/
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enum tc_reload_action {
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/** The counter is reloaded/reset on the next GCLK and starts
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* counting on the prescaler clock.
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*/
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TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK,
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/** The counter is reloaded/reset on the next prescaler clock
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*/
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TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC,
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/** The counter is reloaded/reset on the next GCLK, and the
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* prescaler is restarted as well.
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*/
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TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC,
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};
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/**
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* TC clock prescaler values
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*/
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enum tc_clock_prescaler {
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/** Divide clock by 1 */
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TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0),
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/** Divide clock by 2 */
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TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1),
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/** Divide clock by 4 */
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TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2),
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/** Divide clock by 8 */
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TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3),
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/** Divide clock by 16 */
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TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4),
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/** Divide clock by 64 */
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TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5),
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/** Divide clock by 256 */
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TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6),
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/** Divide clock by 1024 */
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TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7),
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};
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/**
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* TC module count direction.
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*/
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enum tc_count_direction {
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/** Timer should count upward from zero to MAX. */
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TC_COUNT_DIRECTION_UP,
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/** Timer should count downward to zero from MAX. */
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TC_COUNT_DIRECTION_DOWN,
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};
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/**
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* Waveform inversion mode.
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*/
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enum tc_waveform_invert_output {
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/** No inversion of the waveform output. */
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TC_WAVEFORM_INVERT_OUTPUT_NONE = 0,
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/** Invert output from compare channel 0. */
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TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_CTRLC_INVEN(1),
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/** Invert output from compare channel 1. */
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TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_CTRLC_INVEN(2),
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};
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/**
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* Action to perform when the TC module is triggered by an event.
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*/
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enum tc_event_action {
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/** No event action. */
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TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF,
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/** Re-trigger on event. */
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TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER,
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/** Increment counter on event. */
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TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT,
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/** Start counter on event. */
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TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START,
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/** Store period in capture register 0, pulse width in capture
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* register 1.
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|
*/
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|
TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW,
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|
|
|
/** Store pulse width in capture register 0, period in capture
|
|
* register 1.
|
|
*/
|
|
TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP,
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|
};
|
|
|
|
/**
|
|
* TC event enable/disable structure.
|
|
*/
|
|
struct tc_events {
|
|
/** Generate an output event on a compare channel match. */
|
|
bool generate_event_on_compare_channel
|
|
[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
|
|
/** Generate an output event on counter overflow. */
|
|
bool generate_event_on_overflow;
|
|
/** Perform the configured event action when an incoming event is signalled. */
|
|
bool on_event_perform_action;
|
|
/** Specifies if the input event source is inverted, when used in PWP or
|
|
* PPW event action modes.
|
|
*/
|
|
bool invert_event_input;
|
|
/** Specifies which event to trigger if an event is triggered. */
|
|
enum tc_event_action event_action;
|
|
};
|
|
|
|
|
|
/**
|
|
* \brief Configuration struct for TC module in 32-bit size counter mode.
|
|
*/
|
|
struct tc_pwm_channel {
|
|
/** When \c true, PWM output for the given channel is enabled. */
|
|
bool enabled;
|
|
/** Specifies pin output for each channel. */
|
|
uint32_t pin_out;
|
|
/** Specifies MUX setting for each output channel pin. */
|
|
uint32_t pin_mux;
|
|
};
|
|
|
|
|
|
void tc_enable(Tc* const hw);
|
|
void tc_disable(Tc* const hw);
|
|
|
|
void tc_start_counter(Tc* const hw);
|
|
void tc_stop_counter(Tc* const hw);
|
|
|
|
uint32_t tc_get_status(Tc* const hw);
|
|
void tc_clear_status(Tc* const hw,
|
|
const uint32_t status_flags);
|
|
|
|
void tc_set_count_value(Tc* const hw, const uint32_t count);
|
|
uint32_t tc_get_count_value(Tc* const hw);
|
|
|
|
uint32_t tc_get_capture_value(Tc* const hw,
|
|
const enum tc_compare_capture_channel channel_index);
|
|
void tc_set_compare_value(Tc* const hw,
|
|
const enum tc_compare_capture_channel channel_index,
|
|
const uint32_t compare);
|
|
|
|
const Tc* tc_get_slave_instance(Tc* const hw);
|
|
void tc_reset(Tc* const hw);
|
|
void tc_set_top_value (Tc* const hw,
|
|
const uint32_t top_value);
|
|
|
|
void tc_enable_events(Tc* const hw,
|
|
struct tc_events *const events);
|
|
void tc_disable_events(Tc* const hw,
|
|
struct tc_events *const events);
|
|
|
|
enum tc_status_t tc_init(Tc* const hw,
|
|
enum gclk_generator source_clock,
|
|
enum tc_counter_size counter_size, /* 8, 16 or 32bit */
|
|
enum tc_clock_prescaler clock_prescaler,
|
|
enum tc_wave_generation wave_generation,
|
|
enum tc_reload_action reload_action,
|
|
enum tc_count_direction count_direction,
|
|
uint8_t waveform_invert_output,
|
|
bool oneshot,
|
|
bool run_in_standby,
|
|
uint32_t value,
|
|
uint32_t top_value,
|
|
bool* enable_capture_channels,
|
|
uint32_t* compare_channel_values);
|
|
|
|
#endif /* TC_H_INCLUDED */
|