kopia lustrzana https://github.com/bristol-seds/pico-tracker
222 wiersze
7.3 KiB
C
222 wiersze
7.3 KiB
C
/*
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* si4060 software library
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*
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* Stefan Biereigel
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*
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*/
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#ifndef SI4060_H_
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#define SI4060_H_
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#include <inttypes.h>
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#include "samd20.h"
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#include "system/port.h"
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#include "hw_config.h"
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/**
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* Chip Select. Active Low (High = Inactive, Low = Active)
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*/
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#define _si406x_cs_enable() \
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port_pin_set_output_level(SI406X_SEL_PIN, 0)
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#define _si406x_cs_disable() \
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port_pin_set_output_level(SI406X_SEL_PIN, 1)
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#define spi_select _si406x_cs_enable
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#define spi_deselect _si406x_cs_disable
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#define spi_write spi_bitbang_transfer
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#define spi_read() spi_bitbang_transfer(0xff)
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#define __delay_cycles(n) do { \
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for (int cyc = 0; cyc < n; cyc++) { __NOP(); } \
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} while(0)
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void si4060_shutdown(void);
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#define XO_FREQ 16000000UL
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#define RF_FREQ_HZ 434600000.0f
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#define RF_DEV_HZ 100.0f
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#define F_INT (2 * XO_FREQ / 8)
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#define FDIV_INTE ( (RF_FREQ_HZ / F_INT) - 1)
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#define FDIV_FRAC ( (RF_FREQ_HZ - F_INT*(int)FDIV_INTE) * ((uint32_t)1 << 19) ) / F_INT
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#define FDEV ( ( ( (uint32_t)1 << 19) * 8 * RF_DEV_HZ)/ (2*XO_FREQ))
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/* function prototypes */
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void si4060_shutdown (void);
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void si4060_wakeup (void);
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void si4060_reset (void);
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void si4060_power_up (void);
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void si4060_nop (void);
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uint8_t si4060_get_state(void);
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void si4060_get_freq(void);
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void si4060_start_tx (uint8_t channel);
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void si4060_stop_tx (void);
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void si4060_setup (uint8_t mod_type);
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uint8_t si4060_get_property_8 (uint8_t group, uint8_t prop);
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uint16_t si4060_part_info (void);
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/* ===== command definitions ===== */
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#define CMD_NOP 0x00
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#define CMD_PART_INFO 0x01
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#define CMD_POWER_UP 0x02
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#define CMD_SET_PROPERTY 0x11
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#define CMD_GET_PROPERTY 0x12
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#define CMD_GPIO_PIN_CFG 0x13
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#define CMD_START_TX 0x31
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#define CMD_REQUEST_STATE 0x33
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#define CMD_CHANGE_STATE 0x34
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#define CMD_READ_CMD_BUF 0x44
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/* ===== device states ===== */
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#define STATE_NOCHANGE 0x00
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#define STATE_SLEEP 0x01
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#define STATE_SPI_ACTIVE 0x02
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#define STATE_READY 0x03
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#define STATE_TX_TUNE 0x05
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#define STATE_TXA 0x07
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/* ===== property group definitions ===== */
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#define PROP_GLOBAL 0x00
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#define PROP_INT_CTL 0x01
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#define PROP_FRR_CTL 0x02
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#define PROP_PREAMBLE 0x10
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#define PROP_SYNC 0x11
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#define PROP_PKT 0x12
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#define PROP_MODEM 0x20
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#define PROP_PA 0x22
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#define PROP_SYNTH 0x23
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#define PROP_FREQ_CONTROL 0x40
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/* ===== property definitions ===== */
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/* global properties */
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#define GLOBAL_XO_TUNE 0x00
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#define GLOBAL_CONFIG 0x03
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/* preamble properties */
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#define PREAMBLE_TX_LENGTH 0x00
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/* sync properties */
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#define SYNC_CONFIG 0x11
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/* modem properties */
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#define MODEM_MOD_TYPE 0x00
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#define MODEM_FREQ_DEV 0x0a
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#define MODEM_FREQ_OFFSET 0x0d
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#define MODEM_CLKGEN_BAND 0x51
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/* PA properties */
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#define PA_MODE 0x00
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#define PA_PWR_LVL 0x01
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#define PA_BIAS_CLKDUTY 0x02
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/* synthesizer properties */
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#define SYNTH_PFDCP_CPFF 0x00
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#define SYNTH_PFDCP_CPINT 0x01
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#define SYNTH_VCO_KV 0x02
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#define SYNTH_LPFILT3 0x03
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#define SYNTH_LPFILT2 0x04
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#define SYNTH_LPFILT1 0x05
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#define SYNTH_LPFILT0 0x06
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#define SYNTH_VCO_KVCAL 0x07
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/* frequency control properties */
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/* INTE shall be decreased by 1, because FRAC shall be between 1 and 2 */
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#define FREQ_CONTROL_INTE 0x00
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/* FRAC shall be added to 2**19, to ensure MSB is set! */
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#define FREQ_CONTROL_FRAC 0x01
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#define FREQ_CONTROL_CHANNEL_STEP_SIZE 0x04
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#define FREQ_CONTROL_W_SIZE 0x06
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/* ===== command arguments ===== */
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/* POWER_UP arguments */
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/* byte 1 */
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#define PATCH ( 0x01 << 7) /* set patch mode */
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#define FUNC 0x01 /* power on device */
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/* byte 2 */
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#define TCXO 0x01/* select if TCXO (1) or crystal (0) is used */
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/* GPIO_PIN_CFG arguments */
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/* bytes 1 .. 6 */
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#define PULL_CTL 0x40 /* enable or disable pull-up resistor */
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/* bytes 1 .. 4 */
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#define GPIO_MODE_DONOTHING 0x00/* pin behaviour is not changed */
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#define GPIO_MODE_TRISTATE 0x01/* input and output drivers are disabled */
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#define GPIO_MODE_DRIVE0 0x02/* CMOS output "low" */
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#define GPIO_MODE_DRIVE1 0x03/* CMOS output "high" */
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#define GPIO_MODE_INPUT 0x04/* GPIO is input, for TXDATA etc, function is not configured here */
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#define GPIO_MODE_32K_CLK 0x05/* outputs the 32kHz CLK when selected in CLK32_CLK_SEL */
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#define GPIO_MODE_BOOT_CLK 0x06/* outputs boot clock when SPI_ACTIVE */
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#define GPIO_MODE_DIV_CLK 0x07/* outputs divided xtal clk */
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#define GPIO_MODE_CTS 0x08/* output, '1' when device is ready to accept new command */
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#define GPIO_MODE_INV_CNT 0x09/* output, inverted CTS */
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#define GPIO_MODE_CMD_OVERLAP 0x0a/* output, '1' if a command was issued while not ready */
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#define GPIO_MODE_SDO 0x0b/* output, serial data out for SPI */
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#define GPIO_MODE_POR 0x0c/* output, '0' while in POR state */
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#define GPIO_MODE_CAL_WUT 0x0d/* output, '1' on expiration of wake up timer */
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#define GPIO_MODE_WUT 0x0e/* wake up timer output */
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#define GPIO_MODE_EN_PA 0x0f/* output, '1' when PA is enabled */
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#define GPIO_MODE_TX_DATA_CLK 0x10/* data clock output, for TX direct sync mode */
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#define GPIO_MODE_TX_DATA 0x11/* data output from TX FIFO, for debugging purposes */
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#define GPIO_MODE_IN_SLEEP 0x12/* output, '0' when in sleep state */
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#define GPIO_MODE_TX_STATE 0x13/* output, '1' when in TX state */
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#define GPIO_MODE_TX_FIFO_EMPTY 0x14/* output, '1' when FIFO is empty */
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#define GPIO_MODE_LOW_BATT 0x15/* output, '1' if low battery is detected */
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/* byte 5 omitted - no IRQ support */
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#define NIRQ_MODE_DONOTHING 0x00
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/* byte 6 omitted - no SDO reconfiguration support */
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#define SDO_MODE_DONOTHING 0x00
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/* byte 7 */
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#define DRV_STRENGTH_HIGH ( 0x00 << 5)
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#define DRV_STRENGTH_MED_HIGH ( 0x01 << 5)
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#define DRV_STRENGTH_MED_LOW ( 0x02 << 5)
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#define DRV_STRENGTH_LOW ( 0x03 << 5)
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/* START_TX arguments */
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/* byte 2 */
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#define START_TX_TXC_STATE_NOCHANGE ( 0x00 << 4)
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#define START_TX_TXC_STATE_SLEEP ( 0x01 << 4)
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#define START_TX_TXC_STATE_SPI_ACTIVE ( 0x02 << 4)
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#define START_TX_TXC_STATE_READY ( 0x03 << 4)
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#define START_TX_RETRANSMIT_0 ( 0x00 << 2)/* send data that has been written to the TX FIFO */
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#define START_TX_START_IMM ( 0x00 << 0)/* start transmission immediately */
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/* ===== property values ===== */
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/* GLOBAL_CONFIG values */
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#define GLOBAL_RESERVED ( 0x01 << 6) /* shall be set to 1 */
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#define POWER_MODE_LOW_POWER 0x00/* default */
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#define POWER_MODE_HIGH_PERF 0x01
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#define SEQUENCER_MODE_FAST ( 0x00 << 5)/* default */
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#define SEQUENCER_MODE_GUARANT ( 0x01 << 5)
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/* SYNC_CONFIG values */
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#define SYNC_XMIT ( 0x00 << 7)/* default */
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#define SYNC_NO_XMIT ( 0x01 << 7)
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/* MODEM_MOD_TYPE values */
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#define MOD_TYPE_CW 0x00
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#define MOD_TYPE_OOK 0x01
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#define MOD_TYPE_2FSK 0x02/* default */
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#define MOD_TYPE_2GFSK 0x03
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#define MOD_TYPE_4FSK 0x04
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#define MOD_TYPE_4GFSK 0x05
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#define MOD_SOURCE_PACKET ( 0x00 << 3) /* default */
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#define MOD_SOURCE_DIRECT ( 0x01 << 3)
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#define MOD_SOURCE_PSEUDO ( 0x02 << 3)
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#define MOD_GPIO_0 ( 0x00 << 5) /* default */
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#define MOD_GPIO_1 ( 0x01 << 5)
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#define MOD_GPIO_2 ( 0x02 << 5)
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#define MOD_GPIO_3 ( 0x03 << 5)
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#define MOD_DIRECT_MODE_SYNC ( 0x00 << 7) /* default */
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#define MOD_DIRECT_MODE_ASYNC ( 0x01 << 7)
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/* MODEM_CLKGEN_BAND values */
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#define SY_SEL_0 ( 0x00 << 3) /* low power */
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#define SY_SEL_1 ( 0x01 << 3) /* default */
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#define FVCO_DIV_4 0x00 /* default */
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#define FVCO_DIV_6 0x01
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#define FVCO_DIV_8 0x02 /* for 70cm ISM band */
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#define FVCO_DIV_12 0x03
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#define FVCO_DIV_16 0x04
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#define FVCO_DIV_24 0x05
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#define FVCO_DIV_24_2 0x06
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#define FVCO_DIV_24_3 0x07
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/* PA_MODE values*/
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/* PA_BIAS_CLKDUTY values */
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#define PA_BIAS_CLKDUTY_SIN_25 (0x03 << 6) /* for si4060 */
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#define PA_BIAS_CLKDUTY_DIFF_50 (0x00 << 6) /* for si4063 */
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#endif
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