kopia lustrzana https://github.com/bristol-seds/pico-tracker
858 wiersze
28 KiB
C
858 wiersze
28 KiB
C
/**
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* SAM D20/D21/R21 Clock Driver
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*
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* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef SYSTEM_CLOCK_H_INCLUDED
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#define SYSTEM_CLOCK_H_INCLUDED
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/**
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* SAM D20/D21/R21 System Clock Management Driver (SYSTEM CLOCK)
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*
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* This driver for SAM D20/D21/R21 devices provides an interface for
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* the configuration and management of the device's clocking related
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* functions. This includes the various clock sources, bus clocks and
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* generic clocks within the device, with functions to manage the
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* enabling, disabling, source selection and prescaling of clocks to
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* various internal peripherals.
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*
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* The following peripherals are used by this module:
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*
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* - GCLK (Generic Clock Management)
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* - PM (Power Management)
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* - SYSCTRL (Clock Source Control)
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*
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* Module Overview
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*
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* The SAM D20/D21/R21 devices contain a sophisticated clocking
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* system, which is designed to give the maximum flexibility to the
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* user application. This system allows a system designer to tune the
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* performance and power consumption of the device in a dynamic
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* manner, to achieve the best trade-off between the two for a
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* particular application.
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*
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* This driver provides a set of functions for the configuration and
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* management of the various clock related functionality within the
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* device.
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*
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* Clock Sources
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*
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* The SAM D20/D21/R21 devices have a number of master clock source
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* modules, each of which being capable of producing a stabilized
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* output frequency which can then be fed into the various peripherals
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* and modules within the device.
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*
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* Possible clock source modules include internal R/C oscillators,
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* internal DFLL modules, as well as external crystal oscillators
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* and/or clock inputs.
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*
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* CPU / Bus Clocks
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*
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* The CPU and AHB/APBx buses are clocked by the same physical clock
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* source (referred in this module as the Main Clock), however the
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* APBx buses may have additional prescaler division ratios set to
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* give each peripheral bus a different clock speed.
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*
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* Clock Masking
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*
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* To save power, the input clock to one or more peripherals on the AHB and APBx
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* buses can be masked away - when masked, no clock is passed into the module.
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* Disabling of clocks of unused modules will prevent all access to the masked
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* module, but will reduce the overall device power consumption.
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*
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* Generic Clocks
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*
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* Within the SAM D20/D21/R21 devices are a number of Generic Clocks;
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* these are used to provide clocks to the various peripheral clock
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* domains in the device in a standardized manner. One or more master
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* source clocks can be selected as the input clock to a Generic Clock
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* Generator, which can prescale down the input frequency to a slower
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* rate for use in a peripheral.
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*
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* Additionally, a number of individually selectable Generic Clock
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* Channels are provided, which multiplex and gate the various
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* generator outputs for one or more peripherals within the
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* device. This setup allows for a single common generator to feed one
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* or more channels, which can then be enabled or disabled
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* individually as required.
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*
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* Generic Clock Generators
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*
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* Each Generic Clock generator within the device can source its input clock
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* from one of the provided Source Clocks, and prescale the output for one or
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* more Generic Clock Channels in a one-to-many relationship. The generators
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* thus allow for several clocks to be generated of different frequencies,
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* power usages and accuracies, which can be turned on and off individually to
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* disable the clocks to multiple peripherals as a group.
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*
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* Generic Clock Channels
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*
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* To connect a Generic Clock Generator to a peripheral within the
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* device, a Generic Clock Channel is used. Each peripheral or
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* peripheral group has an associated Generic Clock Channel, which serves as the
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* clock input for the peripheral(s). To supply a clock to the peripheral
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* module(s), the associated channel must be connected to a running Generic
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* Clock Generator and the channel enabled.
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*
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*/
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#include <assert.h>
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#include "samd20.h"
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#include "system/gclk.h"
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/**
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* Define system clock features set according to different device family.
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*/
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#if (SAMD21) || (SAMR21)
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/** Digital Phase Locked Loop (DPLL) feature support */
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# define FEATURE_SYSTEM_CLOCK_DPLL
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#endif
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/**
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* Clock status type
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*/
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enum clock_status_t {
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CLOCK_STATUS_OK = 0,
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CLOCK_STATUS_INVALID_ARG,
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};
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/**
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* Available external 32KHz oscillator start-up times, as a number of external
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* clock cycles.
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*/
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enum system_xosc32k_startup {
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/** Wait 0 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_0,
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/** Wait 32 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_32,
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/** Wait 2048 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_2048,
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/** Wait 4096 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_4096,
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/** Wait 16384 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_16384,
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/** Wait 32768 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_32768,
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/** Wait 65536 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_65536,
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/** Wait 131072 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC32K_STARTUP_131072,
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};
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/**
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* Available external oscillator start-up times, as a number of external clock
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* cycles.
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*/
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enum system_xosc_startup {
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/** Wait 1 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_1,
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/** Wait 2 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_2,
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/** Wait 4 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_4,
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/** Wait 8 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_8,
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/** Wait 16 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_16,
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/** Wait 32 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_32,
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/** Wait 64 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_64,
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/** Wait 128 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_128,
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/** Wait 256 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_256,
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/** Wait 512 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_512,
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/** Wait 1024 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_1024,
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/** Wait 2048 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_2048,
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/** Wait 4096 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_4096,
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/** Wait 8192 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_8192,
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/** Wait 16384 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_16384,
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/** Wait 32768 clock cycles until the clock source is considered stable */
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SYSTEM_XOSC_STARTUP_32768,
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};
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/**
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* Available internal 32KHz oscillator start-up times, as a number of internal
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* OSC32K clock cycles.
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*/
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enum system_osc32k_startup {
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/** Wait 3 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_3,
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/** Wait 4 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_4,
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/** Wait 6 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_6,
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/** Wait 10 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_10,
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/** Wait 18 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_18,
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/** Wait 34 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_34,
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/** Wait 66 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_66,
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/** Wait 130 clock cycles until the clock source is considered stable */
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SYSTEM_OSC32K_STARTUP_130,
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};
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/**
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* Available prescalers for the internal 8MHz (nominal) system clock.
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*/
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enum system_osc8m_div {
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/** Do not divide the 8MHz RC oscillator output */
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SYSTEM_OSC8M_DIV_1,
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/** Divide the 8MHz RC oscillator output by 2 */
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SYSTEM_OSC8M_DIV_2,
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/** Divide the 8MHz RC oscillator output by 4 */
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SYSTEM_OSC8M_DIV_4,
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/** Divide the 8MHz RC oscillator output by 8 */
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SYSTEM_OSC8M_DIV_8,
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};
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/**
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* Internal 8Mhz RC oscillator frequency range setting
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*/
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enum system_osc8m_frequency_range {
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/** Frequency range 4 Mhz to 6 Mhz */
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SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
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/** Frequency range 6 Mhz to 8 Mhz */
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SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
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/** Frequency range 8 Mhz to 11 Mhz */
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SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
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/** Frequency range 11 Mhz to 15 Mhz */
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SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
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};
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/**
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* Available division ratios for the CPU and APB/AHB bus clocks.
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*/
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enum system_main_clock_div {
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/** Divide Main clock by 1 */
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SYSTEM_MAIN_CLOCK_DIV_1,
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/** Divide Main clock by 2 */
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SYSTEM_MAIN_CLOCK_DIV_2,
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/** Divide Main clock by 4 */
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SYSTEM_MAIN_CLOCK_DIV_4,
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/** Divide Main clock by 8 */
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SYSTEM_MAIN_CLOCK_DIV_8,
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/** Divide Main clock by 16 */
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SYSTEM_MAIN_CLOCK_DIV_16,
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/** Divide Main clock by 32 */
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SYSTEM_MAIN_CLOCK_DIV_32,
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/** Divide Main clock by 64 */
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SYSTEM_MAIN_CLOCK_DIV_64,
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/** Divide Main clock by 128 */
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SYSTEM_MAIN_CLOCK_DIV_128,
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};
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/**
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* Available external clock source types.
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*/
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enum system_clock_external {
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/** The external clock source is a crystal oscillator */
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SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
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/** The connected clock source is an external logic level clock signal */
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SYSTEM_CLOCK_EXTERNAL_CLOCK,
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};
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/**
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* Available operating modes of the DFLL clock source module,
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*/
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enum system_clock_dfll_loop_mode {
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/** The DFLL is operating in open loop mode with no feedback */
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SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
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/** The DFLL is operating in closed loop mode with frequency feedback from
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* a low frequency reference clock
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*/
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SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
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/** The DFLL is operating in USB recovery mode with frequency feedback
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* from USB SOF
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*/
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};
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/**
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* DFLL lock behavior modes on device wake-up from sleep.
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*/
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enum system_clock_dfll_wakeup_lock {
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/** Keep DFLL lock when the device wakes from sleep */
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SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
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/** Lose DFLL lock when the devices wakes from sleep */
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SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
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};
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/**
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* DFLL fine tracking behavior modes after a lock has been acquired.
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*/
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enum system_clock_dfll_stable_tracking {
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/** Keep tracking after the DFLL has gotten a fine lock */
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SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
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/** Stop tracking after the DFLL has gotten a fine lock */
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SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
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};
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/**
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* DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
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* of time when the DFLL output frequency is not measured by the unit, to allow
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* the output to stabilize after a change in the input clock source.
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*/
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enum system_clock_dfll_chill_cycle {
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/** Enable a chill cycle, where the DFLL output frequency is not measured */
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SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
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/** Disable a chill cycle, where the DFLL output frequency is not measured */
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SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
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};
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/**
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* DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
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* the DFLL output frequency at the expense of accuracy.
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*/
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enum system_clock_dfll_quick_lock {
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/** Enable the QuickLock feature for looser lock requirements on the DFLL */
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SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
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/** Disable the QuickLock feature for strict lock requirements on the DFLL */
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SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
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};
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/**
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* Clock sources available to the GCLK generators
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*/
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enum system_clock_source {
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/** Internal 8MHz RC oscillator */
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SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,
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/** Internal 32kHz RC oscillator */
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SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
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/** External oscillator */
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SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
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/** External 32kHz oscillator */
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SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
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/** Digital Frequency Locked Loop (DFLL) */
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SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
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/** Internal Ultra Low Power 32kHz oscillator */
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SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
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/** Generator input pad */
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SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
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/** Generic clock generator 1 output */
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SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
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#ifdef FEATURE_SYSTEM_CLOCK_DPLL
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/** Digital Phase Locked Loop (DPLL). */
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SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
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#endif
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};
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/**
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* Available bus clock domains on the APB bus.
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*/
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enum system_clock_apb_bus {
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/** Peripheral bus A on the APB bus. */
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SYSTEM_CLOCK_APB_APBA,
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/** Peripheral bus B on the APB bus. */
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SYSTEM_CLOCK_APB_APBB,
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/** Peripheral bus C on the APB bus. */
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SYSTEM_CLOCK_APB_APBC,
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};
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/**
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* Possible NVM flash wait state settings
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*/
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enum system_wait_states {
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/** Wait state maximum frequencies at 1.8V */
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SYSTEM_WAIT_STATE_1_8V_14MHZ = 0,
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SYSTEM_WAIT_STATE_1_8V_28MHZ = 1,
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SYSTEM_WAIT_STATE_1_8V_42MHZ = 2,
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SYSTEM_WAIT_STATE_1_8V_48MHZ = 3,
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/** Wait state maximum frequencies at 3.3V */
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SYSTEM_WAIT_STATE_3_3V_24MHZ = 0,
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SYSTEM_WAIT_STATE_3_3V_48MHZ = 1,
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};
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void system_clock_source_osc8m_set_config(enum system_osc8m_div prescaler,
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bool run_in_standby,
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bool on_demand);
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void system_clock_source_osc8m_set_config_default(void);
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void system_clock_source_osc32k_set_config(enum system_osc32k_startup startup_time,
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bool enable_1khz_output,
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bool enable_32khz_output,
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bool run_in_standby,
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bool on_demand,
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bool write_once);
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void system_clock_source_osc32k_set_config_default(void);
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void system_clock_source_xosc_set_config(enum system_clock_external external_clock,
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enum system_xosc_startup startup_time,
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bool auto_gain_control,
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uint32_t frequency,
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bool run_in_standby,
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bool on_demand);
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void system_clock_source_xosc_set_config_default(void);
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void system_clock_source_xosc32k_set_config(enum system_clock_external external_clock,
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enum system_xosc32k_startup startup_time,
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bool auto_gain_control,
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bool enable_1khz_output,
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bool enable_32khz_output,
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bool run_in_standby,
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bool on_demand,
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bool write_once);
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void system_clock_source_xosc32k_set_config_default(void);
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void system_clock_source_dfll_set_config(
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enum system_clock_dfll_loop_mode loop_mode,
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bool on_demand,
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enum system_clock_dfll_quick_lock quick_lock,
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enum system_clock_dfll_chill_cycle chill_cycle,
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enum system_clock_dfll_wakeup_lock wakeup_lock,
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enum system_clock_dfll_stable_tracking stable_tracking,
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uint8_t coarse_value,
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uint16_t fine_value,
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uint8_t coarse_max_step,
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uint16_t fine_max_step,
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uint16_t multiply_factor);
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void system_clock_source_dfll_set_config_default(void);
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enum clock_status_t system_clock_source_write_calibration(
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const enum system_clock_source system_clock_source,
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const uint16_t calibration_value,
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const uint8_t freq_range);
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enum clock_status_t system_clock_source_enable(
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const enum system_clock_source system_clock_source);
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enum clock_status_t system_clock_source_disable(
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const enum system_clock_source clk_source);
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bool system_clock_source_is_ready(
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const enum system_clock_source clk_source);
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uint32_t system_clock_source_get_hz(
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const enum system_clock_source clk_source);
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/**
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* Enable or disable the main clock failure detection.
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*
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* This mechanism allows switching automatically the main clock to the safe
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* RCSYS clock, when the main clock source is considered off.
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*
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* This may happen for instance when an external crystal is selected as the
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* clock source of the main clock and the crystal dies. The mechanism is to
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* detect, during a RCSYS period, at least one rising edge of the main clock.
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* If no rising edge is seen the clock is considered failed.
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* As soon as the detector is enabled, the clock failure detector
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* CFD) will monitor the divided main clock. When a clock failure is detected,
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* the main clock automatically switches to the RCSYS clock and the CFD
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* interrupt is generated if enabled.
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*
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* \note The failure detect must be disabled if the system clock is the same or
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* slower than 32kHz as it will believe the system clock has failed with
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* a too-slow clock.
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*
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* \param[in] enable Boolean \c true to enable, \c false to disable detection
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*/
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static inline void system_main_clock_set_failure_detect(const bool enable)
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{
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if (enable) {
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// PM->CTRL.reg |= PM_CTRL_CFDEN;
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} else {
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// PM->CTRL.reg &= ~PM_CTRL_CFDEN;
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}
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}
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/**
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* Sets the clock divider used on the main clock to provide the CPU clock.
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*
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* \param[in] divider CPU clock divider to set
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*/
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static inline void system_cpu_clock_set_divider(
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const enum system_main_clock_div divider)
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{
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assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
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PM->CPUSEL.reg = (uint32_t)divider;
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}
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/**
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* Retrieves the operating frequency of the CPU core, obtained from the main
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* generic clock and the set CPU bus divider.
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*
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* \return Current CPU frequency in Hz.
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*/
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static inline uint32_t system_cpu_clock_get_hz(void)
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{
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return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
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}
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/**
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* Set APBx clock divider.
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*
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* Set the clock divider used on the main clock to provide the clock for the
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* given APBx bus.
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*
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* \param[in] divider APBx bus divider to set
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* \param[in] bus APBx bus to set divider for
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*
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* \returns Status of the clock division change operation.
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*
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* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
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* \retval STATUS_OK The APBx clock was set successfully
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*/
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static inline enum clock_status_t system_apb_clock_set_divider(
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const enum system_clock_apb_bus bus,
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const enum system_main_clock_div divider)
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{
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switch (bus) {
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case SYSTEM_CLOCK_APB_APBA:
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PM->APBASEL.reg = (uint32_t)divider;
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break;
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case SYSTEM_CLOCK_APB_APBB:
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PM->APBBSEL.reg = (uint32_t)divider;
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break;
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case SYSTEM_CLOCK_APB_APBC:
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PM->APBCSEL.reg = (uint32_t)divider;
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break;
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default:
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assert(false);
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return CLOCK_STATUS_INVALID_ARG;
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}
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return CLOCK_STATUS_OK;
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}
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/**
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* Retrieves the operating frequency of an APBx bus, obtained from the main
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* generic clock and the set APBx bus divider.
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*
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* \return Current APBx bus frequency in Hz.
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*/
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static inline uint32_t system_apb_clock_get_hz(
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const enum system_clock_apb_bus bus)
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{
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uint16_t bus_divider = 0;
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switch (bus) {
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case SYSTEM_CLOCK_APB_APBA:
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bus_divider = PM->APBASEL.reg;
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break;
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case SYSTEM_CLOCK_APB_APBB:
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bus_divider = PM->APBBSEL.reg;
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break;
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case SYSTEM_CLOCK_APB_APBC:
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bus_divider = PM->APBCSEL.reg;
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break;
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default:
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assert(false);
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return 0;
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}
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return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
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}
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/**
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* Set bits in the clock mask for the AHB bus.
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*
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* This function will set bits in the clock mask for the AHB bus.
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* Any bits set to 1 will enable that clock, 0 bits in the mask
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* will be ignored
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*
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* \param[in] ahb_mask AHB clock mask to enable
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*/
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static inline void system_ahb_clock_set_mask(const uint32_t ahb_mask)
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{
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PM->AHBMASK.reg |= ahb_mask;
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}
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/**
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* Clear bits in the clock mask for the AHB bus.
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*
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* This function will clear bits in the clock mask for the AHB bus.
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* Any bits set to 1 will disable that clock, 0 bits in the mask
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* will be ignored.
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*
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* \param[in] ahb_mask AHB clock mask to disable
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*/
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static inline void system_ahb_clock_clear_mask(const uint32_t ahb_mask)
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{
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PM->AHBMASK.reg &= ~ahb_mask;
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}
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/**
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* Set bits in the clock mask for an APBx bus.
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*
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* This function will set bits in the clock mask for an APBx bus.
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* Any bits set to 1 will enable the corresponding module clock, zero bits in
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* the mask will be ignored.
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*
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* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
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* the device header files
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* \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
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* constants from the device header files
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*
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* \returns Status indicating the result of the clock mask change operation.
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*
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* \retval STATUS_ERR_INVALID_ARG Invalid bus given
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* \retval STATUS_OK The clock mask was set successfully
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*/
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static inline enum clock_status_t system_apb_clock_set_mask(
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const enum system_clock_apb_bus bus,
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const uint32_t mask)
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{
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switch (bus) {
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case SYSTEM_CLOCK_APB_APBA:
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PM->APBAMASK.reg |= mask;
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break;
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case SYSTEM_CLOCK_APB_APBB:
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PM->APBBMASK.reg |= mask;
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break;
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case SYSTEM_CLOCK_APB_APBC:
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PM->APBCMASK.reg |= mask;
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break;
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default:
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assert(false);
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return CLOCK_STATUS_INVALID_ARG;
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}
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return CLOCK_STATUS_OK;
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}
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/**
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* Clear bits in the clock mask for an APBx bus.
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*
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* This function will clear bits in the clock mask for an APBx bus.
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* Any bits set to 1 will disable the corresponding module clock, zero bits in
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* the mask will be ignored.
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*
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* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
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* the device header files
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* \param[in] bus Bus to clear clock mask bits for
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*
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* \returns Status indicating the result of the clock mask change operation.
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*
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* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given.
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* \retval STATUS_OK The clock mask was changed successfully.
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*/
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static inline enum clock_status_t system_apb_clock_clear_mask(
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const enum system_clock_apb_bus bus,
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const uint32_t mask)
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{
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switch (bus) {
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case SYSTEM_CLOCK_APB_APBA:
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PM->APBAMASK.reg &= ~mask;
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break;
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case SYSTEM_CLOCK_APB_APBB:
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PM->APBBMASK.reg &= ~mask;
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break;
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case SYSTEM_CLOCK_APB_APBC:
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PM->APBCMASK.reg &= ~mask;
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break;
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default:
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assert(false);
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return CLOCK_STATUS_INVALID_ARG;
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}
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return CLOCK_STATUS_OK;
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}
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#ifdef FEATURE_SYSTEM_CLOCK_DPLL
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/**
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* Reference clock source of the DPLL module
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*/
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enum system_clock_source_dpll_reference_clock {
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/** Select CLK_DPLL_REF0 as clock reference */
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SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0,
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/** Select CLK_DPLL_REF1 as clock reference */
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SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1,
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/** Select GCLK_DPLL as clock reference */
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SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
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};
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/**
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* Lock time-out value of the DPLL module
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*/
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enum system_clock_source_dpll_lock_time {
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/** Set no time-out as default */
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SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
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/** Set time-out if no lock within 8 ms */
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SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
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/** Set time-out if no lock within 9 ms */
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SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
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/** Set time-out if no lock within 10 ms */
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SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
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/** Set time-out if no lock within 11 ms */
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SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
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};
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/**
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* Filter type of the DPLL module
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*/
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enum system_clock_source_dpll_filter {
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/** Default filter mode */
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SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
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/** Low bandwidth filter */
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SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
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/** High bandwidth filter */
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|
SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
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|
/** High damping filter */
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|
SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
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|
};
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|
|
/**
|
|
* Configuration structure for DPLL
|
|
*
|
|
* DPLL oscillator configuration structure.
|
|
*/
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struct system_clock_source_dpll_config {
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|
/** Run On Demand. If this is set the DPLL won't run
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|
* until requested by a peripheral */
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|
bool on_demand;
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|
/** Keep the DPLL enabled in standby sleep mode */
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|
bool run_in_standby;
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|
/** Bypass lock signal */
|
|
bool lock_bypass;
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|
/** Wake up fast. If this is set DPLL output clock is enabled after
|
|
* the startup time */
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|
bool wake_up_fast;
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|
/** Enable low power mode */
|
|
bool low_power_enable;
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|
|
|
/** Output frequency of the clock */
|
|
uint32_t output_frequency;
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|
/** Reference frequency of the clock */
|
|
uint32_t reference_frequency;
|
|
/** Devider of reference clock */
|
|
uint16_t reference_divider;
|
|
|
|
/** Filter type of the DPLL module */
|
|
enum system_clock_source_dpll_filter filter;
|
|
/** Lock time-out value of the DPLL module */
|
|
enum system_clock_source_dpll_lock_time lock_time;
|
|
/** Reference clock source of the DPLL module */
|
|
enum system_clock_source_dpll_reference_clock reference_clock;
|
|
};
|
|
|
|
/**
|
|
* \brief Retrieve the default configuration for DPLL
|
|
*
|
|
* Fills a configuration structure with the default configuration for a
|
|
* DPLL oscillator module:
|
|
* - Run only when requested by peripheral (on demand)
|
|
* - Don't run in STANDBY sleep mode
|
|
* - Lock bypass disabled
|
|
* - Fast wake up disabled
|
|
* - Low power mode disabled
|
|
* - Output frequency is 48MHz
|
|
* - Reference clock frequency is 32768Hz
|
|
* - Not divide reference clock
|
|
* - Select REF0 as reference clock
|
|
* - Set lock time to default mode
|
|
* - Use default filter
|
|
*
|
|
* \param[out] config Configuration structure to fill with default values
|
|
*/
|
|
static inline void system_clock_source_dpll_get_config_defaults(
|
|
struct system_clock_source_dpll_config *const config)
|
|
{
|
|
config->on_demand = true;
|
|
config->run_in_standby = false;
|
|
config->lock_bypass = false;
|
|
config->wake_up_fast = false;
|
|
config->low_power_enable = false;
|
|
|
|
config->output_frequency = 48000000;
|
|
config->reference_frequency = 32768;
|
|
config->reference_divider = 1;
|
|
config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0;
|
|
|
|
config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
|
|
config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
|
|
};
|
|
|
|
void system_clock_source_dpll_set_config(
|
|
struct system_clock_source_dpll_config *const config);
|
|
|
|
#endif
|
|
|
|
void system_clock_init(void);
|
|
|
|
/**
|
|
* Set flash controller wait states
|
|
*
|
|
* Will set the number of wait states that are used by the onboard
|
|
* flash memory. The number of wait states depend on both device
|
|
* supply voltage and CPU speed. The required number of wait states
|
|
* can be found in the electrical characteristics of the device.
|
|
*
|
|
* \param[in] wait_states Number of wait states to use for internal flash
|
|
*/
|
|
static inline void system_flash_set_waitstates(const enum system_wait_states wait_states)
|
|
{
|
|
assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
|
|
((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
|
|
|
|
NVMCTRL->CTRLB.bit.RWS = wait_states;
|
|
}
|
|
|
|
/**
|
|
* - This driver implements workaround for errata 10558
|
|
*
|
|
* "Several reset values of SYSCTRL.INTFLAG are wrong (BOD and DFLL)"
|
|
* When system_init is called it will reset these interrupts flags before they are used.
|
|
*
|
|
* - This driver implements experimental workaround for errata 9905
|
|
*
|
|
* "The DFLL clock must be requested before being configured otherwise a
|
|
* write access to a DFLL register can freeze the device."
|
|
* This driver will enable and configure the DFLL before the ONDEMAND bit is set.
|
|
*
|
|
*/
|
|
|
|
#endif /* SYSTEM_CLOCK_H_INCLUDED */
|