kopia lustrzana https://github.com/bristol-seds/pico-tracker
308 wiersze
9.9 KiB
C
308 wiersze
9.9 KiB
C
/**
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* SAM D20/D21/R21 GPIO Port Driver
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*
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* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef PORT_H_INCLUDED
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#define PORT_H_INCLUDED
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/**
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* Port Driver (PORT)
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*
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* This driver for SAM D20/D21/R21 devices provides an interface for
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* the configuration and management of the device's General Purpose
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* Input/Output (GPIO) pin functionality, for manual pin state reading
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* and writing.
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*
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* The following peripherals are used by this module:
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*
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* - PORT (GPIO Management)
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*
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* Module Overview
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*
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* The device GPIO (PORT) module provides an interface between the
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* user application logic and external hardware peripherals, when
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* general pin state manipulation is required. This driver provides an
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* easy-to-use interface to the physical pin input samplers and output
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* drivers, so that pins can be read from or written to for general
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* purpose external hardware control.
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*
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* Physical and Logical GPIO Pins
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*
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* SAM D20/D21/R21 devices use two naming conventions for the I/O pins
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* in the device; one physical, and one logical. Each physical pin on
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* a device package is assigned both a physical port and pin
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* identifier (e.g. "PORTA.0") as well as a monotonically incrementing
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* logical GPIO number (e.g. "GPIO0"). While the former is used to map
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* physical pins to their physical internal device module
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* counterparts, for simplicity the design of this driver uses the
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* logical GPIO numbers instead.
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*
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* Special Considerations
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*
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* The SAM D20/D21/R21 port pin input sampler can be disabled when the pin is configured
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* in pure output mode to save power; reading the pin state of a pin configured
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* in output-only mode will read the logical output state that was last set.
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*
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*/
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#include "system/pinmux.h"
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/** Convenience definition for GPIO module group A on the device (if
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* available). */
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#if (PORT_GROUPS > 0)
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# define PORTA PORT->Group[0]
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#endif
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#if (PORT_GROUPS > 1)
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/** Convenience definition for GPIO module group B on the device (if
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* available). */
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# define PORTB PORT->Group[1]
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#endif
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#if (PORT_GROUPS > 2)
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/** Convenience definition for GPIO module group C on the device (if
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* available). */
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# define PORTC PORT->Group[2]
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#endif
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#if (PORT_GROUPS > 3)
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/** Convenience definition for GPIO module group D on the device (if
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* available). */
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# define PORTD PORT->Group[3]
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#endif
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/**
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* Enum for the possible pin direction settings of the port pin configuration
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* structure, to indicate the direction the pin should use.
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*/
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enum port_pin_dir {
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/** The pin's input buffer should be enabled, so that the pin state can
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* be read. */
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PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,
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/** The pin's output buffer should be enabled, so that the pin state can
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* be set. */
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PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
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/** The pin's output and input buffers should be enabled, so that the pin
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* state can be set and read back. */
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PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
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};
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/**
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* Enum for the possible pin pull settings of the port pin configuration
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* structure, to indicate the type of logic level pull the pin should use.
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*/
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enum port_pin_pull {
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/** No logical pull should be applied to the pin. */
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PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
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/** Pin should be pulled up when idle. */
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PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
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/** Pin should be pulled down when idle. */
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PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
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};
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/**
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* Retrieves the PORT module group instance from a given GPIO pin number.
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*
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* Retrieves the PORT module group instance associated with a given
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* logical GPIO pin number.
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*
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* \param[in] gpio_pin Index of the GPIO pin to convert.
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*
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* \return Base address of the associated PORT module.
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*/
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static inline PortGroup* port_get_group_from_gpio_pin(const uint8_t gpio_pin)
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{
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return system_pinmux_get_group_from_gpio_pin(gpio_pin);
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}
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/**
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* Retrieves the state of a group of port pins that are configured as inputs.
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*
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* Reads the current logic level of a port module's pins and returns
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* the current levels as a bitmask.
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*
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* \param[in] port Base of the PORT module to read from.
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* \param[in] mask Mask of the port pin(s) to read.
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*
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* \return Status of the port pin(s) input buffers.
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*/
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static inline uint32_t port_group_get_input_level(const PortGroup *const port,
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const uint32_t mask)
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{
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/* Sanity check arguments */
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assert(port);
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return (port->IN.reg & mask);
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}
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/**
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* Retrieves the state of a group of port pins that are configured as outputs.
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*
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* Reads the current logical output level of a port module's pins and
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* returns the current levels as a bitmask.
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*
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* \param[in] port Base of the PORT module to read from.
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* \param[in] mask Mask of the port pin(s) to read.
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*
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* \return Status of the port pin(s) output buffers.
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*/
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static inline uint32_t port_group_get_output_level(const PortGroup *const port,
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const uint32_t mask)
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{
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/* Sanity check arguments */
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assert(port);
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return (port->OUT.reg & mask);
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}
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/**
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* Sets the state of a group of port pins that are configured as outputs.
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*
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* \param[out] port Base of the PORT module to write to.
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* \param[in] mask Mask of the port pin(s) to change.
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* \param[in] level_mask Mask of the port level(s) to set.
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*/
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static inline void port_group_set_output_level(PortGroup *const port,
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const uint32_t mask,
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const uint32_t level_mask)
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{
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/* Sanity check arguments */
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assert(port);
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port->OUTSET.reg = (mask & level_mask);
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port->OUTCLR.reg = (mask & ~level_mask);
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}
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/**
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* Toggles the state of a group of port pins that are configured as an outputs.
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*
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* \param[out] port Base of the PORT module to write to.
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* \param[in] mask Mask of the port pin(s) to toggle.
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*/
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static inline void port_group_toggle_output_level(PortGroup *const port,
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const uint32_t mask)
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{
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/* Sanity check arguments */
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assert(port);
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port->OUTTGL.reg = mask;
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}
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void port_pin_set_config(const uint8_t gpio_pin,
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enum port_pin_dir direction,
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enum port_pin_pull input_pull,
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bool powersave);
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void port_pin_set_config_default(const uint8_t gpio_pin);
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void port_group_set_config(PortGroup *const port,
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const uint32_t mask,
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enum port_pin_dir direction,
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enum port_pin_pull input_pull,
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bool powersave);
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void port_group_set_config_default(PortGroup *const port,
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const uint32_t mask);
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/**
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* Reads the current logic level of a port pin and returns the current
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* level as a boolean value.
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*
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* \param[in] gpio_pin Index of the GPIO pin to read.
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*
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* \return Status of the port pin's input buffer.
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*/
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static inline bool port_pin_get_input_level(const uint8_t gpio_pin)
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{
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PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
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uint32_t pin_mask = (1UL << (gpio_pin % 32));
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return (port_base->IN.reg & pin_mask);
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}
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/**
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* Reads the current logical output level of a port pin and returns the current
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* level as a boolean value.
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*
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* \param[in] gpio_pin Index of the GPIO pin to read.
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*
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* \return Status of the port pin's output buffer.
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*/
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static inline bool port_pin_get_output_level(const uint8_t gpio_pin)
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{
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PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
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uint32_t pin_mask = (1UL << (gpio_pin % 32));
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return (port_base->OUT.reg & pin_mask);
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}
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/**
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* Sets the current output level of a port pin to a given logic level.
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*
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* \param[in] gpio_pin Index of the GPIO pin to write to.
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* \param[in] level Logical level to set the given pin to.
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*/
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static inline void port_pin_set_output_level(const uint8_t gpio_pin,
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const bool level)
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{
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PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
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uint32_t pin_mask = (1UL << (gpio_pin % 32));
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/* Set the pin to high or low atomically based on the requested level */
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if (level) {
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port_base->OUTSET.reg = pin_mask;
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} else {
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port_base->OUTCLR.reg = pin_mask;
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}
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}
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/**
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* Toggles the current output level of a port pin.
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*
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* \param[in] gpio_pin Index of the GPIO pin to toggle.
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*/
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static inline void port_pin_toggle_output_level(const uint8_t gpio_pin)
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{
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PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
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uint32_t pin_mask = (1UL << (gpio_pin % 32));
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/* Toggle pin output level */
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port_base->OUTTGL.reg = pin_mask;
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}
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#endif
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