Updated design notes

hardware/design_notes/Makefile

@@ -5,6 +5,9 @@ all: fbri-notes.pdf Parts.md
 %.pdf: %.tex
 	pdflatex $<
 
+# Turns any farnell part numbers (specified as "Farnell | [xxxxxx] |")
+# into hyperlinks.
+#
 .PHONY: Parts.md
 Parts.md:
 	sed -i 's/[Ff]arnell.*|.*\[\([0-9]*\)\].*|/Farnell | [\1](http:\/\/uk.farnell.com\/jsp\/search\/browse.jsp;jsessionid=0?N=0\&Ntk=partnumbers\&Ntt=*\1*) |/g' Parts.md

hardware/design_notes/Parts.md

@@ -2,7 +2,7 @@
 
 | ID | Part Number | Description | Supplier | Order Code | Quantity | Notes
 | --- | --- | --- | --- | --- | --- | ---
-| U1 | ATSAMD20E17A-MU | Microcontroller Atmel SAM D20, 128kB Flash, 16kB SRAM, -40 to 85°C, QFN-32 | Farnell | [2361006](http://uk.farnell.com/jsp/search/browse.jsp;jsessionid=0?N=0&Ntk=partnumbers&Ntt=*2361006*) | Derate Flash / RAM as to minimum for firmware
+| U1 | ATSAMD20E17A-MU | Microcontroller Atmel SAM D20, 128kB Flash, 16kB SRAM, -40 to 85°C, QFN-32 | Farnell | [2361006](http://uk.farnell.com/jsp/search/browse.jsp;jsessionid=0?N=0&Ntk=partnumbers&Ntt=*2361006*) | 1 | Derate Flash / RAM
 | JTAG1 | 20021121-00010C4LF | 2x5 Pin Header, SMT, 1.27mm Pitch, Gold Plate | Farnell | [1865279](http://uk.farnell.com/jsp/search/browse.jsp;jsessionid=0?N=0&Ntk=partnumbers&Ntt=*1865279*) |
 | U2 | SI4060-B1B-FM | RF Tx SPI 142MHZ-1.05GHZ, QFN-20 | Farnell | [2414373](http://uk.farnell.com/jsp/search/browse.jsp;jsessionid=0?N=0&Ntk=partnumbers&Ntt=*2414373*) |
 | U3 | MAX1947ETA18+T | DC-DC Step-Up Converter, 18V, QFN-8 | Farnell | [1609613](http://uk.farnell.com/jsp/search/browse.jsp;jsessionid=0?N=0&Ntk=partnumbers&Ntt=*1609613*) | 1

hardware/design_notes/fbri-notes.tex

@@ -28,7 +28,7 @@ circuit diagram, and hence firmware should be generally interoperable
 between the two.
 
 However to allow detection of the hardware version PA02 is shorted to
-ground on the developement version while is will be pulled high
+ground on the development version while is will be pulled high
 internally on the flight version.
 
 \subsection{Dimensions}
@@ -43,6 +43,12 @@ components on a 1/4 mm grid.
 The board is routed with 6 mil traces for data and 6 / 16 mil traces
 for power. Where nessesary the traces  All via are 0.3mm (12mil) drill.
 
+\section{Components}
+
+\subsection{Development}
+
+The
+
 \section{Design}
 
 \subsection{HF Clock}
@@ -79,5 +85,10 @@ In any case the SI4060 tune API allows ramping up the internal
 capacitance to 11pF, which will drop Q at the expense of the time
 constant.
 
+\subsection {Firmware}
+
+Check flight WG2 on habhub for gps string formatting gone wrong
+
+Get so much test data.
 
 \end{document}