From d477adeecce273da747ff54826bb4465b43206a2 Mon Sep 17 00:00:00 2001
From: Richard Eoin Meadows <richardeoin@gmail.com>
Date: Wed, 27 Aug 2014 20:57:52 +0100
Subject: [PATCH] HF = DFLL version

---
 firmware/inc/hw_config.h |  2 +-
 firmware/inc/si4060.h    |  4 ++--
 firmware/src/main.c      | 10 +++++++---
 firmware/src/si4060.c    |  2 +-
 firmware/src/timepulse.c |  8 ++++----
 5 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/firmware/inc/hw_config.h b/firmware/inc/hw_config.h
index 5870f67..4946682 100644
--- a/firmware/inc/hw_config.h
+++ b/firmware/inc/hw_config.h
@@ -76,7 +76,7 @@
 #define GPS_TIME_PIN		PIN_PA28
 #define GPS_TIME_PINMUX		PINMUX_PA28H_GCLK_IO0
 #define GPS_SERCOM_MUX		USART_RX_1_TX_0_XCK_1
-#define GPS_TIMEPULSE_FREQ      24000000
+#define GPS_TIMEPULSE_FREQ      4000000
 // 32768
 #define GPS_PLATFORM_MODEL	UBX_PLATFORM_MODEL_AIRBORNE_1G
 
diff --git a/firmware/inc/si4060.h b/firmware/inc/si4060.h
index 5da766f..96bfd61 100644
--- a/firmware/inc/si4060.h
+++ b/firmware/inc/si4060.h
@@ -33,11 +33,11 @@
 void si4060_shutdown(void);
 
 
-#define XO_FREQ 12000000UL
+#define XO_FREQ 16000000UL
 #define RF_FREQ_HZ 434600000.0f
 #define RF_DEV_HZ 100.0f
 
-#define F_INT (2 * XO_FREQ / 4)
+#define F_INT (2 * XO_FREQ / 8)
 #define FDIV_INTE ( (RF_FREQ_HZ / F_INT) - 1)
 #define FDIV_FRAC ( (RF_FREQ_HZ - F_INT*(int)FDIV_INTE) * ((uint32_t)1 << 19)  ) / F_INT
 #define FDEV ( ( ( (uint32_t)1 << 19) * 8 * RF_DEV_HZ)/ (2*XO_FREQ))
diff --git a/firmware/src/main.c b/firmware/src/main.c
index 6317754..38b6be0 100644
--- a/firmware/src/main.c
+++ b/firmware/src/main.c
@@ -108,14 +108,18 @@ int main(void)
 
   /* For the moment output GCLK_MAIN / 2 on HF CLK */
   switch_gclk_main_to_timepulse();
-  half_glck_main_on_hf_clk();
- /* Wait for HF CLK to stabilise */
+  /* Wait for GCLK to stabilise */
+  for (int i = 0; i < 1000*100; i++);
+
+  //half_glck_main_on_hf_clk();
+  timepulse_init();
+  /* Wait for HF CLK to stabilise */
   for (int i = 0; i < 1000*100; i++);
 
   semihost_printf("GCLK_MAIN = %d\n", gclk_main_frequency());
 
   /* Drop the CPU clock to 1.5Mhz */
-  system_cpu_clock_set_divider(SYSTEM_MAIN_CLOCK_DIV_16);
+  //system_cpu_clock_set_divider(SYSTEM_MAIN_CLOCK_DIV_16);
 
   /* Initialise Si4060 */
   si4060_hw_init();
diff --git a/firmware/src/si4060.c b/firmware/src/si4060.c
index 84395a3..4a42867 100644
--- a/firmware/src/si4060.c
+++ b/firmware/src/si4060.c
@@ -421,7 +421,7 @@ void si4060_setup(uint8_t mod_type) {
   /* setup divider to 8 (for 70cm ISM band */
   si4060_set_property_8(PROP_MODEM,
 			MODEM_CLKGEN_BAND,
-			SY_SEL_1 | FVCO_DIV_4);
+			SY_SEL_1 | FVCO_DIV_8);
   /* set up the PA power level */
   si4060_set_property_8(PROP_PA,
 			PA_PWR_LVL,
diff --git a/firmware/src/timepulse.c b/firmware/src/timepulse.c
index ac19ef7..5a0f10b 100644
--- a/firmware/src/timepulse.c
+++ b/firmware/src/timepulse.c
@@ -32,9 +32,9 @@
 #define DFLL48_MUL	(DFLL48M_CLK / GPS_TIMEPULSE_FREQ)
 
 /* Check that DFLL48_MUL is an integer */
-//#if ((DFLL48M_CLK * 100000000) / GPS_TIMEPULSE_FREQ != (DFLL48_MUL * 100000000))
-//#error DFLL48M_CLK must be a integer multiple of GPS_TIMEPULSE_FREQ!
-//#endif
+#if ((DFLL48M_CLK * 100000000) / GPS_TIMEPULSE_FREQ != (DFLL48_MUL * 100000000))
+#error DFLL48M_CLK must be a integer multiple of GPS_TIMEPULSE_FREQ!
+#endif
 
 void timepulse_init(void)
 {
@@ -74,7 +74,7 @@ void timepulse_init(void)
   system_gclk_gen_set_config(SI406X_HF_GCLK,
 			     GCLK_SOURCE_DFLL48M, /* Source 		*/
 			     false,		/* High When Disabled	*/
-			     48,		/* Division Factor	*/
+			     3,			/* Division Factor = 16MHz*/
 			     false,		/* Run in standby	*/
 			     true);		/* Output Pin Enable	*/