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Initial bring-up of v0.96.0 hardware. GPS functioning

rocketry
Richard Eoin Meadows 2014-10-06 19:05:11 +01:00
rodzic b79b3299cd
commit cbd2a5c18f
4 zmienionych plików z 240 dodań i 228 usunięć
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36
firmware/inc/hw_config.h
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@ -56,15 +56,9 @@
#ifdef XPLAINED
#define LED0_PIN PIN_PA14
#else
#define LED0_PIN PIN_PA25 /* Shared with Radio GPIO */
#define LED0_PIN PIN_PA15
#endif
/**
* Reset
*/
#define RESET_DUMMY1_PIN PIN_PA05
#define RESET_DUMMY2_PIN PIN_PA15
/**
* GPS
*/
@ -73,17 +67,11 @@
#define GPS_SERCOM_MOGI_PINMUX PINMUX_PA00D_SERCOM1_PAD0
#define GPS_SERCOM_MIGO_PIN PIN_PA01
#define GPS_SERCOM_MIGO_PINMUX PINMUX_PA01D_SERCOM1_PAD1
#define GPS_TIME_PIN PIN_PA28
#define GPS_TIME_PINMUX PINMUX_PA28H_GCLK_IO0
#define GPS_SERCOM_MUX USART_RX_1_TX_0_XCK_1
#define GPS_TIMEPULSE_FREQ 1000
#define GPS_PLATFORM_MODEL UBX_PLATFORM_MODEL_AIRBORNE_1G
/**
* DFLL48
*/
#define DFLL48M_GCLK GCLK_GENERATOR_0
#define DFLL48M_CLK 48000000
#define GPS_TIMEPULSE_PIN PIN_PA05
#define GPS_TIMEPULSE_PINMUX PINMUX_PA05F_TC0_WO1
#define GPS_TIMEPULSE_FREQ 10
/**
* USART Loopback Testing
@ -123,19 +111,19 @@
#define SI406X_SEL_PIN PIN_PA18
#define SI406X_IRQ_PIN PIN_PA24
#define SI406X_IRQ_PINMUX PINMUX_PA24A_EIC_EXTINT12
#define SI406X_HF_GCLK GCLK_GENERATOR_3
#define SI406X_HF_CLK_PIN PIN_PA17
#define SI406X_HF_CLK_PINMUX PINMUX_PA17H_GCLK_IO3
/* Currently half GPS TIMEPULSE */
#define SI406X_HF_FREQUENCY (GPS_TIMEPULSE_FREQ / 2)
#define SI406X_SDN_PIN PIN_PA16
#define SI406X_GPIO0_PIN PIN_PA27
#define SI406X_GPIO1_PIN PIN_PA25 /* Shared with LED */
#define SI406X_GPIO1_PIN PIN_PA25
#define SI406X_TCXO_PIN PIN_PA17
#define SI406X_TCXO_PINMUX PINMUX_PA17H_GCLK_IO3
#define SI406X_TCXO_GCLK GCLK_GENERATOR_3
#define SI406X_TCXO_FREQUENCY 16369000
/**
* Watchdog Timer
* External Watchdog Timer
*/
#define WDT_GCLK GCLK_GENERATOR_4
#define WDT_WDI_PIN PIN_PA28
/**
* SWD

117
firmware/src/main.c
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@ -1,5 +1,5 @@
/*
* Bristol Longshot
* Bristol SEDS pico-tracker
* Copyright (C) 2014 Richard Meadows <richardeoin>
*
* Permission is hereby granted, free of charge, to any person obtaining
@ -84,6 +84,37 @@ void si4060_gpio_init()
false); /* Powersave */
port_pin_set_output_level(SI406X_GPIO1_PIN, 0);
}
/**
* Initialises the status LED
*/
static inline void led_init(void)
{
port_pin_set_config(LED0_PIN,
PORT_PIN_DIR_OUTPUT, /* Direction */
PORT_PIN_PULL_NONE, /* Pull */
false); /* Powersave */
port_pin_set_output_level(LED0_PIN, 1); /* LED is active low */
}
/**
* Turns the status LED on
*/
static inline void led_on(void)
{
port_pin_set_output_level(LED0_PIN, 0); /* LED is active low */
}
/**
* Turns the status lED off
*/
static inline void led_off(void)
{
port_pin_set_output_level(LED0_PIN, 1); /* LED is active low */
}
void set_timer(uint32_t time)
{
bool capture_channel_enables[] = {false, false};
@ -117,27 +148,32 @@ void set_timer(uint32_t time)
tc_start_counter(TC2);
}
void wdt_init() {
/* 64 seconds timeout. So 2^(15+6) cycles of the wdt clock */
system_gclk_gen_set_config(WDT_GCLK,
GCLK_SOURCE_OSCULP32K, /* Source */
false, /* High When Disabled */
128, /* Division Factor */
false, /* Run in standby */
true); /* Output Pin Enable */
system_gclk_gen_enable(WDT_GCLK);
/* void wdt_init() { */
/* /\* 64 seconds timeout. So 2^(15+6) cycles of the wdt clock *\/ */
/* system_gclk_gen_set_config(WDT_GCLK, */
/* GCLK_SOURCE_OSCULP32K, /\* Source *\/ */
/* false, /\* High When Disabled *\/ */
/* 128, /\* Division Factor *\/ */
/* false, /\* Run in standby *\/ */
/* true); /\* Output Pin Enable *\/ */
/* system_gclk_gen_enable(WDT_GCLK); */
/* Set the watchdog timer. On 256Hz gclk 4 */
wdt_set_config(true, /* Lock WDT */
true, /* Enable WDT */
GCLK_GENERATOR_4, /* Clock Source */
WDT_PERIOD_16384CLK, /* Timeout Period */
WDT_PERIOD_NONE, /* Window Period */
WDT_PERIOD_NONE); /* Early Warning Period */
}
/* /\* Set the watchdog timer. On 256Hz gclk 4 *\/ */
/* wdt_set_config(true, /\* Lock WDT *\/ */
/* true, /\* Enable WDT *\/ */
/* GCLK_GENERATOR_4, /\* Clock Source *\/ */
/* WDT_PERIOD_16384CLK, /\* Timeout Period *\/ */
/* WDT_PERIOD_NONE, /\* Window Period *\/ */
/* WDT_PERIOD_NONE); /\* Early Warning Period *\/ */
/* } */
int main(void)
{
/**
* Internal initialisation
* ---------------------------------------------------------------------------
*/
/* Clock up to 14MHz with 0 wait states */
system_flash_set_waitstates(SYSTEM_WAIT_STATE_1_8V_14MHZ);
@ -156,24 +192,20 @@ int main(void)
system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_0);
//TODO: system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
semihost_printf("Hello World %fHz\n", RF_FREQ_HZ);
/* Set the wdt here. We should get to the first reset in one min */
wdt_init();
wdt_reset_count();
/* Initialise GPS */
gps_init();
/* Wait for GPS timepulse to stabilise */
for (int i = 0; i < 1000*100; i++);
/* Configure the SysTick for 50Hz triggering */
SysTick_Config(SystemCoreClock / 50);
/**
* System initialisation
* ---------------------------------------------------------------------------
*/
led_init();
gps_init();
/* Initialise Si4060 */
si4060_hw_init();
/* reset the radio chip from shutdown */
si4060_reset();
/* check radio communication */
@ -182,32 +214,31 @@ int main(void)
while(1);
}
si4060_power_up();
si4060_setup(MOD_TYPE_2FSK);
/* si4060_power_up(); */
/* si4060_setup(MOD_TYPE_2FSK); */
si4060_gpio_init();
si4060_start_tx(0);
/* si4060_gpio_init(); */
/* si4060_start_tx(0); */
while (1) {
/* Send the last packet */
while (rtty_active());
//while (rtty_active());
port_pin_set_output_level(SI406X_GPIO0_PIN, 0);
/* Watchdog */
wdt_reset_count();
//port_pin_set_output_level(SI406X_GPIO0_PIN, 0);
/* Send requests to the gps */
gps_update();
/* Wait between frames */
led_on();
for (int i = 0; i < 100*1000; i++);
led_off();
for (int i = 0; i < 100*1000; i++);
/* Set the next packet */
set_telemetry_string();
port_pin_set_output_level(SI406X_GPIO0_PIN, 1);
//set_telemetry_string();
// port_pin_set_output_level(SI406X_GPIO0_PIN, 1);
//system_sleep();
}

2
firmware/src/si406x.c
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@ -32,7 +32,7 @@
#define RADIO_FREQ 434600000
// Quite low power
#define RADIO_PWR 0x7f
#define VCXO_FREQ SI406X_HF_FREQUENCY
#define VCXO_FREQ SI406X_TCXO_FREQUENCY
uint32_t active_freq = RADIO_FREQ;
uint8_t active_pwr = RADIO_PWR;

313
firmware/src/timepulse.c
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@ -29,187 +29,180 @@
#include "tc/tc_driver.h"
#include "hw_config.h"
#define DFLL48_MUL (DFLL48M_CLK / GPS_TIMEPULSE_FREQ)
/* void timepulse_init(void) */
/* { */
/* /\* Set up the DFLL GCLK channel *\/ */
/* system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, DFLL48M_GCLK); */
/* system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); */
/* Check that DFLL48_MUL is an integer */
#if ((DFLL48M_CLK * 100000000) / GPS_TIMEPULSE_FREQ != (DFLL48_MUL * 100000000))
#error DFLL48M_CLK must be a integer multiple of GPS_TIMEPULSE_FREQ!
#endif
/* /\* Configure DFLL48 *\/ */
/* system_clock_source_dfll_set_config( */
/* SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED, /\* Loop Mode *\/ */
/* false, /\* On demand *\/ */
/* SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE, /\* Quick Lock *\/ */
/* SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, /\* Chill Cycle *\/ */
/* SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, /\* Lock during wakeup *\/ */
/* SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, */
/* 0x1f / 4, /\* Open Loop - Coarse calibration value *\/ */
/* 0xff / 4, /\* Open Loop - Fine calibration value *\/ */
/* 1, /\* Closed Loop - Coarse Maximum step *\/ */
/* 1, /\* Closed Loop - Fine Maximum step *\/ */
/* DFLL48_MUL); /\* Frequency Multiplication Factor *\/ */
void timepulse_init(void)
{
/* Set up the DFLL GCLK channel */
system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, DFLL48M_GCLK);
system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
/* /\* Enable DFLL48 *\/ */
/* system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); */
/* Configure DFLL48 */
system_clock_source_dfll_set_config(
SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED, /* Loop Mode */
false, /* On demand */
SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE, /* Quick Lock */
SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, /* Chill Cycle */
SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, /* Lock during wakeup */
SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
0x1f / 4, /* Open Loop - Coarse calibration value */
0xff / 4, /* Open Loop - Fine calibration value */
1, /* Closed Loop - Coarse Maximum step */
1, /* Closed Loop - Fine Maximum step */
DFLL48_MUL); /* Frequency Multiplication Factor */
/* /\* Wait for it to be ready *\/ */
/* while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); */
/* Enable DFLL48 */
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
/* /\* system_clock_source_xosc_set_config(SYSTEM_CLOCK_EXTERNAL_CLOCK, *\/ */
/* /\* SYSTEM_XOSC_STARTUP_16384, *\/ */
/* /\* true, /\\* Auto gain control *\\/ *\/ */
/* /\* 16000000UL, /\\* Frequency *\\/ *\/ */
/* /\* true, /\\* Run in Standby *\\/ *\/ */
/* /\* false); /\\* Run on demand *\\/ *\/ */
/* /\* system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); *\/ */
/* Wait for it to be ready */
while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
/* /\* Configure the HF GCLK *\/ */
/* system_gclk_gen_set_config(SI406X_HF_GCLK, */
/* GCLK_SOURCE_DFLL48M, /\* Source *\/ */
/* false, /\* High When Disabled *\/ */
/* 3, /\* Division Factor = 16MHz*\/ */
/* false, /\* Run in standby *\/ */
/* true); /\* Output Pin Enable *\/ */
/* system_clock_source_xosc_set_config(SYSTEM_CLOCK_EXTERNAL_CLOCK, */
/* SYSTEM_XOSC_STARTUP_16384, */
/* true, /\* Auto gain control *\/ */
/* 16000000UL, /\* Frequency *\/ */
/* true, /\* Run in Standby *\/ */
/* false); /\* Run on demand *\/ */
/* system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); */
/* /\* Configure the output pin *\/ */
/* system_pinmux_pin_set_config(SI406X_HF_CLK_PINMUX >> 16, /\* GPIO Pin *\/ */
/* SI406X_HF_CLK_PINMUX & 0xFFFF, /\* Mux Position *\/ */
/* SYSTEM_PINMUX_PIN_DIR_INPUT, /\* Direction *\/ */
/* SYSTEM_PINMUX_PIN_PULL_NONE, /\* Pull *\/ */
/* false); /\* Powersave *\/ */
/* Configure the HF GCLK */
system_gclk_gen_set_config(SI406X_HF_GCLK,
GCLK_SOURCE_DFLL48M, /* Source */
false, /* High When Disabled */
3, /* Division Factor = 16MHz*/
false, /* Run in standby */
true); /* Output Pin Enable */
/* /\* Enable the HF GCLK *\/ */
/* system_gclk_gen_enable(SI406X_HF_GCLK); */
/* } */
/* Configure the output pin */
system_pinmux_pin_set_config(SI406X_HF_CLK_PINMUX >> 16, /* GPIO Pin */
SI406X_HF_CLK_PINMUX & 0xFFFF, /* Mux Position */
SYSTEM_PINMUX_PIN_DIR_INPUT, /* Direction */
SYSTEM_PINMUX_PIN_PULL_NONE, /* Pull */
false); /* Powersave */
/* /\** */
/* * Switches GCLK_MAIN (a.k.a. GCLK0) to the gps timepulse */
/* *\/ */
/* void switch_gclk_main_to_timepulse(void) */
/* { */
/* /\* Enable GCLK_IO[0] *\/ */
/* system_pinmux_pin_set_config(GPS_TIME_PINMUX >> 16, /\* GPIO Pin *\/ */
/* GPS_TIME_PINMUX & 0xFFFF, /\* Mux Position *\/ */
/* SYSTEM_PINMUX_PIN_DIR_INPUT, /\* Direction *\/ */
/* SYSTEM_PINMUX_PIN_PULL_NONE, /\* Pull *\/ */
/* false); /\* Powersave *\/ */
/* Enable the HF GCLK */
system_gclk_gen_enable(SI406X_HF_GCLK);
}
/* /\* Switch GCLK_MAIN to GCLK_IO[0] *\/ */
/* system_gclk_gen_set_config(GCLK_GENERATOR_0, /\* GCLK 0 *\/ */
/* GCLK_SOURCE_GCLKIN,/\* Source from pin *\/ */
/* false, /\* High When Disabled *\/ */
/* 1, /\* Division Factor *\/ */
/* true, /\* Run in standby *\/ */
/* true); /\* Output Pin Enable *\/ */
/**
* Switches GCLK_MAIN (a.k.a. GCLK0) to the gps timepulse
*/
void switch_gclk_main_to_timepulse(void)
{
/* Enable GCLK_IO[0] */
system_pinmux_pin_set_config(GPS_TIME_PINMUX >> 16, /* GPIO Pin */
GPS_TIME_PINMUX & 0xFFFF, /* Mux Position */
SYSTEM_PINMUX_PIN_DIR_INPUT, /* Direction */
SYSTEM_PINMUX_PIN_PULL_NONE, /* Pull */
false); /* Powersave */
/* /\* Wait for switch? *\/ */
/* } */
/* Switch GCLK_MAIN to GCLK_IO[0] */
system_gclk_gen_set_config(GCLK_GENERATOR_0, /* GCLK 0 */
GCLK_SOURCE_GCLKIN,/* Source from pin */
false, /* High When Disabled */
1, /* Division Factor */
true, /* Run in standby */
true); /* Output Pin Enable */
/* /\** */
/* * Outputs GCLK0 div 2 on the HF CLK pin */
/* *\/ */
/* void half_glck_main_on_hf_clk(void) */
/* { */
/* bool capture_channel_enables[] = {true, true}; */
/* uint32_t compare_channel_values[] = {0x0000, 0x0000}; */
/* Wait for switch? */
}
/* tc_init(TC2, */
/* GCLK_GENERATOR_0, */
/* TC_COUNTER_SIZE_8BIT, */
/* TC_CLOCK_PRESCALER_DIV1, */
/* TC_WAVE_GENERATION_NORMAL_FREQ, */
/* TC_RELOAD_ACTION_GCLK, */
/* TC_COUNT_DIRECTION_UP, */
/* TC_WAVEFORM_INVERT_OUTPUT_NONE, */
/* false, /\* Oneshot = false *\/ */
/* false, /\* Run in standby = false *\/ */
/* 0x0000, /\* Initial value *\/ */
/* 0x0000, /\* Top value *\/ */
/* capture_channel_enables, /\* Capture Channel Enables *\/ */
/* compare_channel_values); /\* Compare Channels Values *\/ */
/**
* Outputs GCLK0 div 2 on the HF CLK pin
*/
void half_glck_main_on_hf_clk(void)
{
bool capture_channel_enables[] = {true, true};
uint32_t compare_channel_values[] = {0x0000, 0x0000};
/* /\* Enable the output pin *\/ */
/* system_pinmux_pin_set_config(PINMUX_PA17F_TC2_WO1 >> 16, /\* GPIO Pin *\/ */
/* PINMUX_PA17F_TC2_WO1 & 0xFFFF, /\* Mux Position *\/ */
/* SYSTEM_PINMUX_PIN_DIR_INPUT, /\* Direction *\/ */
/* SYSTEM_PINMUX_PIN_PULL_NONE, /\* Pull *\/ */
/* false); /\* Powersave *\/ */
tc_init(TC2,
GCLK_GENERATOR_0,
TC_COUNTER_SIZE_8BIT,
TC_CLOCK_PRESCALER_DIV1,
TC_WAVE_GENERATION_NORMAL_FREQ,
TC_RELOAD_ACTION_GCLK,
TC_COUNT_DIRECTION_UP,
TC_WAVEFORM_INVERT_OUTPUT_NONE,
false, /* Oneshot = false */
false, /* Run in standby = false */
0x0000, /* Initial value */
0x0000, /* Top value */
capture_channel_enables, /* Capture Channel Enables */
compare_channel_values); /* Compare Channels Values */
/* tc_enable(TC2); */
/* tc_start_counter(TC2); */
/* } */
/* Enable the output pin */
system_pinmux_pin_set_config(PINMUX_PA17F_TC2_WO1 >> 16, /* GPIO Pin */
PINMUX_PA17F_TC2_WO1 & 0xFFFF, /* Mux Position */
SYSTEM_PINMUX_PIN_DIR_INPUT, /* Direction */
SYSTEM_PINMUX_PIN_PULL_NONE, /* Pull */
false); /* Powersave */
/* /\** */
/* * Returns the current GCLK_MAIN frequency, as measured against OSC8M */
/* *\/ */
/* uint32_t gclk_main_frequency(void) */
/* { */
/* uint32_t osc8m_frequency = 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; */
tc_enable(TC2);
tc_start_counter(TC2);
}
/* /\* Configure GCLK Gen 6 as reference *\/ */
/* system_gclk_gen_set_config(GCLK_GENERATOR_6, */
/* GCLK_SOURCE_OSC8M, /\* Source *\/ */
/* false, /\* High When Disabled *\/ */
/* 4, /\* Division Factor *\/ */
/* false, /\* Run in standby *\/ */
/* false); /\* Output Pin Enable *\/ */
/* /\* Enable GCLK 6 *\/ */
/* system_gclk_gen_enable(GCLK_GENERATOR_6); */
/**
* Returns the current GCLK_MAIN frequency, as measured against OSC8M
*/
uint32_t gclk_main_frequency(void)
{
uint32_t osc8m_frequency = 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
/* /\* Timer 0 free runs on GLCK 0 *\/ */
/* bool t0_capture_channel_enables[] = {false, false}; */
/* uint32_t t0_compare_channel_values[] = {0x0000, 0x0000}; */
/* Configure GCLK Gen 6 as reference */
system_gclk_gen_set_config(GCLK_GENERATOR_6,
GCLK_SOURCE_OSC8M, /* Source */
false, /* High When Disabled */
4, /* Division Factor */
false, /* Run in standby */
false); /* Output Pin Enable */
/* Enable GCLK 6 */
system_gclk_gen_enable(GCLK_GENERATOR_6);
/* tc_init(TC0, */
/* GCLK_GENERATOR_0, */
/* TC_COUNTER_SIZE_32BIT, */
/* TC_CLOCK_PRESCALER_DIV1, */
/* TC_WAVE_GENERATION_NORMAL_FREQ, */
/* TC_RELOAD_ACTION_GCLK, */
/* TC_COUNT_DIRECTION_UP, */
/* TC_WAVEFORM_INVERT_OUTPUT_NONE, */
/* false, /\* Oneshot *\/ */
/* false, /\* Run in standby *\/ */
/* 0x0000, /\* Initial value *\/ */
/* 0xFFFFFFFF, /\* Top value *\/ */
/* t0_capture_channel_enables, /\* Capture Channel Enables *\/ */
/* t0_compare_channel_values); /\* Compare Channels Values *\/ */
/* Timer 0 free runs on GLCK 0 */
bool t0_capture_channel_enables[] = {false, false};
uint32_t t0_compare_channel_values[] = {0x0000, 0x0000};
/* /\* Timer 3 counts 10000 cycles of GLCK 6 *\/ */
/* bool t1_capture_channel_enables[] = {false, false}; */
/* uint32_t t1_compare_channel_values[] = {10000, 0x0000}; */
tc_init(TC0,
GCLK_GENERATOR_0,
TC_COUNTER_SIZE_32BIT,
TC_CLOCK_PRESCALER_DIV1,
TC_WAVE_GENERATION_NORMAL_FREQ,
TC_RELOAD_ACTION_GCLK,
TC_COUNT_DIRECTION_UP,
TC_WAVEFORM_INVERT_OUTPUT_NONE,
false, /* Oneshot */
false, /* Run in standby */
0x0000, /* Initial value */
0xFFFFFFFF, /* Top value */
t0_capture_channel_enables, /* Capture Channel Enables */
t0_compare_channel_values); /* Compare Channels Values */
/* tc_init(TC3, */
/* GCLK_GENERATOR_6, */
/* TC_COUNTER_SIZE_16BIT, */
/* TC_CLOCK_PRESCALER_DIV1, */
/* TC_WAVE_GENERATION_NORMAL_FREQ, */
/* TC_RELOAD_ACTION_GCLK, */
/* TC_COUNT_DIRECTION_UP, */
/* TC_WAVEFORM_INVERT_OUTPUT_NONE, */
/* false, /\* Oneshot *\/ */
/* false, /\* Run in standby *\/ */
/* 0x0000, /\* Initial value *\/ */
/* 0xFFFF, /\* Top value *\/ */
/* t1_capture_channel_enables, /\* Capture Channel Enables *\/ */
/* t1_compare_channel_values); /\* Compare Channels Values *\/ */
/* Timer 3 counts 10000 cycles of GLCK 6 */
bool t1_capture_channel_enables[] = {false, false};
uint32_t t1_compare_channel_values[] = {10000, 0x0000};
/* tc_enable(TC0); */
/* tc_enable(TC3); */
/* tc_start_counter(TC0); */
/* tc_start_counter(TC3); */
tc_init(TC3,
GCLK_GENERATOR_6,
TC_COUNTER_SIZE_16BIT,
TC_CLOCK_PRESCALER_DIV1,
TC_WAVE_GENERATION_NORMAL_FREQ,
TC_RELOAD_ACTION_GCLK,
TC_COUNT_DIRECTION_UP,
TC_WAVEFORM_INVERT_OUTPUT_NONE,
false, /* Oneshot */
false, /* Run in standby */
0x0000, /* Initial value */
0xFFFF, /* Top value */
t1_capture_channel_enables, /* Capture Channel Enables */
t1_compare_channel_values); /* Compare Channels Values */
/* /\* Wait 10000 cycles of GCLK 6 *\/ */
/* while (!(tc_get_status(TC3) & TC_STATUS_CHANNEL_0_MATCH)); */
tc_enable(TC0);
tc_enable(TC3);
tc_start_counter(TC0);
tc_start_counter(TC3);
/* uint32_t gclk_main_count = tc_get_count_value(TC0) - 50; */
/* Wait 10000 cycles of GCLK 6 */
while (!(tc_get_status(TC3) & TC_STATUS_CHANNEL_0_MATCH));
uint32_t gclk_main_count = tc_get_count_value(TC0) - 50;
return gclk_main_count / 10;
}
/* return gclk_main_count / 10; */
/* } */