kopia lustrzana https://github.com/bristol-seds/pico-tracker
[memory] use internal flash for backlog
Richard Meadows
rodzic
f75b383e34
commit
8dc241b512
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@ -28,23 +28,18 @@
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/**
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/**
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* Memory layout:
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* Memory layout:
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*
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*
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* 256-byte pages
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* 64-byte pages
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* 4-kbyte sectors (erase) - 16 pages
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* 256-byte rows (erase) - 4 pages
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* 64-kbyte blocks - 16 sectors
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*/
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*/
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#define TOTAL_PAGES 0x800
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#define TOTAL_PAGES 0x100
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#define TOTAL_SECTORS 0x80
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#define TOTAL_ROWS 0x40
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#define TOTAL_BLOCKS 0x8
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#define MEMORY_MASK 0x7FFFF
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#define PAGE_MASK 0x7FFC0
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#define PAGE_MASK 0x7FF00
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#define ROW_MASK 0x7FF00
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#define SECTOR_MASK 0x7F000
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#define MEMORY_SIZE 0x80000
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#define PAGE_SIZE 0x00040
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#define PAGE_SIZE 0x00100
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#define ROW_SIZE 0x00100
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#define SECTOR_SIZE 0x01000
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#define BLOCK_SIZE 0x10000
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/**
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/**
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* Pages assigned to backlog. Currently 256 records
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* Pages assigned to backlog. Currently 256 records
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@ -52,6 +47,7 @@
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#define BACKLOG_START_PAGE 0x00
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#define BACKLOG_START_PAGE 0x00
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#define BACKLOG_END_PAGE 0xff
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#define BACKLOG_END_PAGE 0xff
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void mem_chip_erase(void);
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void mem_chip_erase(void);
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void mem_read_memory(uint32_t address, uint8_t* buffer, uint32_t length);
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void mem_read_memory(uint32_t address, uint8_t* buffer, uint32_t length);
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void mem_write_page(uint32_t address, uint8_t* buffer, uint16_t length);
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void mem_write_page(uint32_t address, uint8_t* buffer, uint16_t length);
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@ -99,8 +99,8 @@ void load_is_backlog_valid(void)
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*/
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*/
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void erase_backlog_item(uint16_t index) {
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void erase_backlog_item(uint16_t index) {
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uint32_t start_address = ADDRESS(index) & SECTOR_MASK;
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uint32_t start_address = ADDRESS(index) & ROW_MASK;
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uint32_t end_address = start_address + SECTOR_SIZE;
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uint32_t end_address = start_address + ROW_SIZE;
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uint16_t start_index = (start_address-BACKLOG_ADDRESS) / BACKLOG_ITEM_SIZE;
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uint16_t start_index = (start_address-BACKLOG_ADDRESS) / BACKLOG_ITEM_SIZE;
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uint16_t end_index = ceil((float)(end_address-BACKLOG_ADDRESS) / BACKLOG_ITEM_SIZE);
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uint16_t end_index = ceil((float)(end_address-BACKLOG_ADDRESS) / BACKLOG_ITEM_SIZE);
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uint16_t i;
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uint16_t i;
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@ -27,121 +27,24 @@
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#include "sercom/spi.h"
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#include "sercom/spi.h"
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#include "hw_config.h"
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#include "hw_config.h"
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enum memory_opcodes {
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MEM_OP_READ = 0x03,
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MEM_OP_ERASE_4KB_SECTOR = 0x20,
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MEM_OP_ERASE_64KB_BLOCK = 0xD8,
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MEM_OP_CHIP_ERASE = 0x60,
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MEM_OP_PAGE_PROGRAM = 0x02,
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MEM_OP_READ_STATUS_REGISTER = 0x05,
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MEM_OP_WRITE_STATUS_REGISTER = 0x01,
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MEM_OP_WRITE_ENABLE = 0x06,
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MEM_OP_WRITE_DISABLE = 0x04,
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MEM_OP_READ_ID = 0xAB,
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MEM_OP_READ_JEDEC_ID = 0x9F,
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MEM_OP_POWER_DOWN = 0xB9,
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MEM_OP_POWER_UP = 0xAB,
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};
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enum memory_status_register {
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MEM_STATUS_BUSY = (1 << 0),
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MEM_STATUS_WRITES_ENABLED = (1 << 1),
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};
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#define SST25WF040B_JEDEC_ID 0x00131662
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/**
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/**
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* Check initialised correctly
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* See Errata 10804 for more details, d/s §35.3.16
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* Silicon Revision C
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*/
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*/
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uint8_t memory_init_success = 0;
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#define FIX_ERRATA_REV_C_FLASH_10804
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#define MEM_SIZE 16384 /* 16 KB */
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/**
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* Allocate a 16KB section of flash memory, aligned to an NVM row
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*/
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const uint8_t nvm_section[MEM_SIZE] __attribute__ ((aligned (256))) = { 0xFF };
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/**
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/**
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* Chip Select. Active Low (High = Inactive, Low = Active)
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* Poll the status register until the busy bit is cleared
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*/
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#define _mem_cs_enable() \
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port_pin_set_output_level(FLASH_CSN_PIN, 0)
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#define _mem_cs_disable() \
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port_pin_set_output_level(FLASH_CSN_PIN, 1)
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/**
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* Transfers `length` bytes
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*/
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#define _mem_transfer(tx_data, rx_data, length) \
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spi_transceive_buffer_wait(FLASH_SERCOM, tx_data, rx_data, length)
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/**
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* Reads `length` bytes
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*/
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#define _mem_read(rx_data, length) \
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spi_read_buffer_wait(FLASH_SERCOM, rx_data, length, 0xFF)
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/**
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* Writes `length` bytes
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*/
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#define _mem_write(tx_data, length) \
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spi_write_buffer_wait(FLASH_SERCOM, tx_data, length)
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/**
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* Write a single command with no data
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*/
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void _mem_single_command(uint8_t command)
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{
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_mem_cs_enable();
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_mem_write(&command, 1);
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_mem_cs_disable();
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}
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/**
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* Read the status register until the busy bit is cleared
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*/
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*/
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void _mem_wait_for_done(void)
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void _mem_wait_for_done(void)
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{
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{
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uint8_t tx_data = MEM_OP_READ_STATUS_REGISTER;
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while ((NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY) == 0);
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uint8_t status_register;
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_mem_cs_enable();
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_mem_write(&tx_data, 1);
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do {
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_mem_read(&status_register, 1);
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// Sleep for a few hundred microseconds??
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for (int i = 0; i < 100; i++);
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} while (status_register & MEM_STATUS_BUSY);
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_mem_cs_disable();
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}
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/**
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* JEDEC ID
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*/
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uint32_t mem_read_jedec_id(void)
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{
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uint8_t tx_data;
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uint32_t rx_data_32;
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uint8_t* rx_data = (uint8_t*)&rx_data_32;
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tx_data = MEM_OP_READ_JEDEC_ID;
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_mem_cs_enable();
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_mem_write(&tx_data, 1); _mem_read(rx_data, 4);
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_mem_cs_disable();
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return rx_data_32;
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}
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/**
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* Enter Deep Power Down
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*/
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void mem_enter_deep_power_down(void)
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{
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_mem_single_command(MEM_OP_POWER_DOWN);
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}
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/**
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* Exit Deep Power Down
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*/
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void mem_exit_deep_power_down(void)
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{
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_mem_single_command(MEM_OP_POWER_UP);
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}
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}
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@ -156,16 +59,29 @@ void mem_exit_deep_power_down(void)
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*/
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*/
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void mem_chip_erase(void)
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void mem_chip_erase(void)
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{
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{
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if (memory_init_success) {
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#ifdef FIX_ERRATA_REV_C_FLASH_10804
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_mem_single_command(MEM_OP_WRITE_ENABLE);
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/* save CTRLB and disable cache */
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uint32_t temp = NVMCTRL->CTRLB.reg;
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NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
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#endif
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_mem_single_command(MEM_OP_CHIP_ERASE);
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/* erase each row */
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for (int n = 0; n < TOTAL_ROWS; n++) {
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/* Wait */
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/* write address */
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NVMCTRL->ADDR.reg = (uint32_t)(nvm_section + (n*ROW_SIZE)) >> 1;
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/* unlock */
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_UR;
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/* erase */
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
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_mem_wait_for_done();
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_mem_wait_for_done();
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/* lock */
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_mem_single_command(MEM_OP_WRITE_DISABLE);
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_LR;
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}
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}
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#ifdef FIX_ERRATA_REV_C_FLASH_10804
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/* restore CTRLB */
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NVMCTRL->CTRLB.reg = temp;
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#endif
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}
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}
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/**
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/**
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@ -173,167 +89,81 @@ void mem_chip_erase(void)
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*/
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*/
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void mem_read_memory(uint32_t address, uint8_t* buffer, uint32_t length)
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void mem_read_memory(uint32_t address, uint8_t* buffer, uint32_t length)
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{
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{
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uint8_t tx_data[4];
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memcpy(buffer, nvm_section + address, length);
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if (memory_init_success) {
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address &= MEMORY_MASK;
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tx_data[0] = MEM_OP_READ;
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tx_data[1] = (address >> 16) & 0xFF;
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tx_data[2] = (address >> 8) & 0xFF;
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tx_data[3] = (address >> 0) & 0xFF;
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_mem_cs_enable();
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_mem_write(tx_data, 4); _mem_read(buffer, length);
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_mem_cs_disable();
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}
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}
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}
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/**
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/**
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* Write 256-byte page. Address should be page aligned
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* Write 64-byte page. Address should be page aligned
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*/
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*/
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void mem_write_page(uint32_t address, uint8_t* buffer, uint16_t length)
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void mem_write_page(uint32_t address, uint8_t* buffer, uint16_t length)
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{
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{
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uint8_t tx_data[4];
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#ifdef FIX_ERRATA_REV_C_FLASH_10804
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/* save CTRLB and disable cache */
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uint32_t temp = NVMCTRL->CTRLB.reg;
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NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
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#endif
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if (memory_init_success) {
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if ((address < MEM_SIZE) && (length <= PAGE_SIZE)) {
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_mem_single_command(MEM_OP_WRITE_ENABLE);
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/* write address */
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NVMCTRL->ADDR.reg = (uint32_t)(nvm_section + address) >> 1;
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address &= PAGE_MASK;
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/* write data. length must be multiple of two */
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memcpy((void*)(nvm_section + address), buffer, length & ~0x1);
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tx_data[0] = MEM_OP_PAGE_PROGRAM;
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/* unlock */
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tx_data[1] = (address >> 16) & 0xFF;
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_UR;
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tx_data[2] = (address >> 8) & 0xFF;
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/* write page */
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tx_data[3] = (address >> 0) & 0xFF;
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
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_mem_cs_enable();
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_mem_write(tx_data, 4); _mem_write(buffer, length);
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_mem_cs_disable();
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/* Wait */
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_mem_wait_for_done();
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_mem_wait_for_done();
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/* lock */
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_mem_single_command(MEM_OP_WRITE_DISABLE);
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_LR;
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}
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}
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#ifdef FIX_ERRATA_REV_C_FLASH_10804
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/* restore CTRLB */
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NVMCTRL->CTRLB.reg = temp;
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#endif
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}
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}
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/**
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/**
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* Erase sector
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* Erase 256-byte sector.
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*/
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*/
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void mem_erase_sector(uint32_t address)
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void mem_erase_sector(uint32_t address)
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{
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{
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uint8_t tx_data[4];
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#ifdef FIX_ERRATA_REV_C_FLASH_10804
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/* save CTRLB and disable cache */
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uint32_t temp = NVMCTRL->CTRLB.reg;
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NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
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#endif
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if (memory_init_success) {
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if (address < MEM_SIZE) {
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_mem_single_command(MEM_OP_WRITE_ENABLE);
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/* write address */
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NVMCTRL->ADDR.reg = (uint32_t)(nvm_section + address) >> 1;
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address &= SECTOR_MASK;
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/* unlock */
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_UR;
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tx_data[0] = MEM_OP_ERASE_4KB_SECTOR;
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tx_data[1] = (address >> 16) & 0xFF;
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tx_data[2] = (address >> 8) & 0xFF;
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tx_data[3] = (address >> 0) & 0xFF;
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_mem_cs_enable();
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_mem_write(tx_data, 4);
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_mem_cs_disable();
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/* Wait */
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_mem_wait_for_done();
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_mem_wait_for_done();
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/* erase row */
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_mem_single_command(MEM_OP_WRITE_DISABLE);
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
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_mem_wait_for_done();
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/* lock */
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_LR;
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}
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}
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#ifdef FIX_ERRATA_REV_C_FLASH_10804
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/* restore CTRLB */
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NVMCTRL->CTRLB.reg = temp;
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#endif
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}
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}
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/**
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/**
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* Initialise and Power on Memory Interface
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* Initialise and Power on Memory Interface
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*
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*
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* Returns 1 on success, 0 on failute
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* Returns 1 on success, 0 on failure
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*/
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*/
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uint8_t mem_power_on(void)
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uint8_t mem_power_on(void)
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{
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{
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/* Configure the SPI select pin */
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/* NVMCTRL is enabled by default */
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port_pin_set_config(FLASH_CSN_PIN,
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return 1;
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PORT_PIN_DIR_OUTPUT, /* Direction */
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PORT_PIN_PULL_NONE, /* Pull */
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false); /* Powersave */
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/* Disable the SEL pin */
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_mem_cs_disable();
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spi_init(FLASH_SERCOM,
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SPI_MODE_MASTER, /** SPI mode */
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SPI_DATA_ORDER_MSB, /** Data order */
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SPI_TRANSFER_MODE_0, /** Transfer mode */
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FLASH_SERCOM_MUX, /** Mux setting */
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SPI_CHARACTER_SIZE_8BIT, /** SPI character size */
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false, /** Enabled in sleep */
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true, /** Enable receiver */
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1000*1000, /** Master - Baud rate */
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0, /** Slave - Frame format */
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0, /** Slave - Address mode */
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0, /** Slave - Address */
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0, /** Slave - Address mask */
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false, /** Slave - Preload data */
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GCLK_GENERATOR_0, /** GCLK generator to use */
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FLASH_SERCOM_MOSI_PINMUX, /** Pinmux */
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FLASH_SERCOM_MISO_PINMUX, /** Pinmux */
|
|
||||||
FLASH_SERCOM_SCK_PINMUX, /** Pinmux */
|
|
||||||
PINMUX_UNUSED); /** Pinmux */
|
|
||||||
|
|
||||||
spi_enable(FLASH_SERCOM);
|
|
||||||
|
|
||||||
/* Release from power down */
|
|
||||||
mem_exit_deep_power_down();
|
|
||||||
|
|
||||||
/* Make 3 attempts to read JEDEC chip ID */
|
|
||||||
for (int i = 0; i < 3; i++) {
|
|
||||||
|
|
||||||
uint32_t jedec = mem_read_jedec_id();
|
|
||||||
|
|
||||||
/* Check it's the chip we're expecting */
|
|
||||||
if (jedec == SST25WF040B_JEDEC_ID) {
|
|
||||||
/* Correct ID */
|
|
||||||
memory_init_success = 1;
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Memory failed to initialise correctly */
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
/**
|
/**
|
||||||
* Return memory to lowest power state
|
* Return memory to lowest power state
|
||||||
*/
|
*/
|
||||||
void mem_power_off(void)
|
void mem_power_off(void)
|
||||||
{
|
{
|
||||||
if (memory_init_success) {
|
|
||||||
/* Place memory in deep power down */
|
|
||||||
mem_enter_deep_power_down();
|
|
||||||
|
|
||||||
/* Disable SPI interface */
|
|
||||||
spi_disable(FLASH_SERCOM);
|
|
||||||
|
|
||||||
/* Return pins to default state (lowest power) */
|
|
||||||
system_pinmux_pin_set_config(FLASH_CSN_PIN,
|
|
||||||
SYSTEM_PINMUX_GPIO,
|
|
||||||
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
|
|
||||||
SYSTEM_PINMUX_PIN_PULL_NONE,
|
|
||||||
true);
|
|
||||||
system_pinmux_pin_set_config(FLASH_SERCOM_MOSI_PIN,
|
|
||||||
SYSTEM_PINMUX_GPIO,
|
|
||||||
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
|
|
||||||
SYSTEM_PINMUX_PIN_PULL_NONE,
|
|
||||||
true);
|
|
||||||
system_pinmux_pin_set_config(FLASH_SERCOM_MISO_PIN,
|
|
||||||
SYSTEM_PINMUX_GPIO,
|
|
||||||
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
|
|
||||||
SYSTEM_PINMUX_PIN_PULL_NONE,
|
|
||||||
true);
|
|
||||||
system_pinmux_pin_set_config(FLASH_SERCOM_SCK_PIN,
|
|
||||||
SYSTEM_PINMUX_GPIO,
|
|
||||||
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
|
|
||||||
SYSTEM_PINMUX_PIN_PULL_NONE,
|
|
||||||
true);
|
|
||||||
|
|
||||||
/* memory is no longer initialised */
|
|
||||||
memory_init_success = 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Ładowanie…
Reference in New Issue