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[memory] use internal flash for backlog

main-solar-only
Richard Meadows 2016-07-16 20:38:29 +01:00
rodzic f75b383e34
commit 8dc241b512
3 zmienionych plików z 89 dodań i 263 usunięć
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22
firmware/inc/memory.h
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@ -28,23 +28,18 @@
/**
* Memory layout:
*
* 256-byte pages
* 4-kbyte sectors (erase) - 16 pages
* 64-kbyte blocks - 16 sectors
* 64-byte pages
* 256-byte rows (erase) - 4 pages
*/
#define TOTAL_PAGES 0x800
#define TOTAL_SECTORS 0x80
#define TOTAL_BLOCKS 0x8
#define TOTAL_PAGES 0x100
#define TOTAL_ROWS 0x40
#define MEMORY_MASK 0x7FFFF
#define PAGE_MASK 0x7FF00
#define SECTOR_MASK 0x7F000
#define PAGE_MASK 0x7FFC0
#define ROW_MASK 0x7FF00
#define MEMORY_SIZE 0x80000
#define PAGE_SIZE 0x00100
#define SECTOR_SIZE 0x01000
#define BLOCK_SIZE 0x10000
#define PAGE_SIZE 0x00040
#define ROW_SIZE 0x00100
/**
* Pages assigned to backlog. Currently 256 records
@ -52,6 +47,7 @@
#define BACKLOG_START_PAGE 0x00
#define BACKLOG_END_PAGE 0xff
void mem_chip_erase(void);
void mem_read_memory(uint32_t address, uint8_t* buffer, uint32_t length);
void mem_write_page(uint32_t address, uint8_t* buffer, uint16_t length);

4
firmware/src/backlog.c
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@ -99,8 +99,8 @@ void load_is_backlog_valid(void)
*/
void erase_backlog_item(uint16_t index) {
uint32_t start_address = ADDRESS(index) & SECTOR_MASK;
uint32_t end_address = start_address + SECTOR_SIZE;
uint32_t start_address = ADDRESS(index) & ROW_MASK;
uint32_t end_address = start_address + ROW_SIZE;
uint16_t start_index = (start_address-BACKLOG_ADDRESS) / BACKLOG_ITEM_SIZE;
uint16_t end_index = ceil((float)(end_address-BACKLOG_ADDRESS) / BACKLOG_ITEM_SIZE);
uint16_t i;

326
firmware/src/memory.c
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@ -27,121 +27,24 @@
#include "sercom/spi.h"
#include "hw_config.h"
enum memory_opcodes {
MEM_OP_READ = 0x03,
MEM_OP_ERASE_4KB_SECTOR = 0x20,
MEM_OP_ERASE_64KB_BLOCK = 0xD8,
MEM_OP_CHIP_ERASE = 0x60,
MEM_OP_PAGE_PROGRAM = 0x02,
MEM_OP_READ_STATUS_REGISTER = 0x05,
MEM_OP_WRITE_STATUS_REGISTER = 0x01,
MEM_OP_WRITE_ENABLE = 0x06,
MEM_OP_WRITE_DISABLE = 0x04,
MEM_OP_READ_ID = 0xAB,
MEM_OP_READ_JEDEC_ID = 0x9F,
MEM_OP_POWER_DOWN = 0xB9,
MEM_OP_POWER_UP = 0xAB,
};
enum memory_status_register {
MEM_STATUS_BUSY = (1 << 0),
MEM_STATUS_WRITES_ENABLED = (1 << 1),
};
#define SST25WF040B_JEDEC_ID 0x00131662
/**
* Check initialised correctly
* See Errata 10804 for more details, d/s §35.3.16
* Silicon Revision C
*/
uint8_t memory_init_success = 0;
#define FIX_ERRATA_REV_C_FLASH_10804
#define MEM_SIZE 16384 /* 16 KB */
/**
* Allocate a 16KB section of flash memory, aligned to an NVM row
*/
const uint8_t nvm_section[MEM_SIZE] __attribute__ ((aligned (256))) = { 0xFF };
/**
* Chip Select. Active Low (High = Inactive, Low = Active)
*/
#define _mem_cs_enable() \
port_pin_set_output_level(FLASH_CSN_PIN, 0)
#define _mem_cs_disable() \
port_pin_set_output_level(FLASH_CSN_PIN, 1)
/**
* Transfers `length` bytes
*/
#define _mem_transfer(tx_data, rx_data, length) \
spi_transceive_buffer_wait(FLASH_SERCOM, tx_data, rx_data, length)
/**
* Reads `length` bytes
*/
#define _mem_read(rx_data, length) \
spi_read_buffer_wait(FLASH_SERCOM, rx_data, length, 0xFF)
/**
* Writes `length` bytes
*/
#define _mem_write(tx_data, length) \
spi_write_buffer_wait(FLASH_SERCOM, tx_data, length)
/**
* Write a single command with no data
*/
void _mem_single_command(uint8_t command)
{
_mem_cs_enable();
_mem_write(&command, 1);
_mem_cs_disable();
}
/**
* Read the status register until the busy bit is cleared
* Poll the status register until the busy bit is cleared
*/
void _mem_wait_for_done(void)
{
uint8_t tx_data = MEM_OP_READ_STATUS_REGISTER;
uint8_t status_register;
_mem_cs_enable();
_mem_write(&tx_data, 1);
do {
_mem_read(&status_register, 1);
// Sleep for a few hundred microseconds??
for (int i = 0; i < 100; i++);
} while (status_register & MEM_STATUS_BUSY);
_mem_cs_disable();
}
/**
* JEDEC ID
*/
uint32_t mem_read_jedec_id(void)
{
uint8_t tx_data;
uint32_t rx_data_32;
uint8_t* rx_data = (uint8_t*)&rx_data_32;
tx_data = MEM_OP_READ_JEDEC_ID;
_mem_cs_enable();
_mem_write(&tx_data, 1); _mem_read(rx_data, 4);
_mem_cs_disable();
return rx_data_32;
}
/**
* Enter Deep Power Down
*/
void mem_enter_deep_power_down(void)
{
_mem_single_command(MEM_OP_POWER_DOWN);
}
/**
* Exit Deep Power Down
*/
void mem_exit_deep_power_down(void)
{
_mem_single_command(MEM_OP_POWER_UP);
while ((NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY) == 0);
}
@ -156,16 +59,29 @@ void mem_exit_deep_power_down(void)
*/
void mem_chip_erase(void)
{
if (memory_init_success) {
_mem_single_command(MEM_OP_WRITE_ENABLE);
#ifdef FIX_ERRATA_REV_C_FLASH_10804
/* save CTRLB and disable cache */
uint32_t temp = NVMCTRL->CTRLB.reg;
NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
#endif
_mem_single_command(MEM_OP_CHIP_ERASE);
/* Wait */
/* erase each row */
for (int n = 0; n < TOTAL_ROWS; n++) {
/* write address */
NVMCTRL->ADDR.reg = (uint32_t)(nvm_section + (n*ROW_SIZE)) >> 1;
/* unlock */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_UR;
/* erase */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
_mem_wait_for_done();
_mem_single_command(MEM_OP_WRITE_DISABLE);
/* lock */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_LR;
}
#ifdef FIX_ERRATA_REV_C_FLASH_10804
/* restore CTRLB */
NVMCTRL->CTRLB.reg = temp;
#endif
}
/**
@ -173,167 +89,81 @@ void mem_chip_erase(void)
*/
void mem_read_memory(uint32_t address, uint8_t* buffer, uint32_t length)
{
uint8_t tx_data[4];
if (memory_init_success) {
address &= MEMORY_MASK;
tx_data[0] = MEM_OP_READ;
tx_data[1] = (address >> 16) & 0xFF;
tx_data[2] = (address >> 8) & 0xFF;
tx_data[3] = (address >> 0) & 0xFF;
_mem_cs_enable();
_mem_write(tx_data, 4); _mem_read(buffer, length);
_mem_cs_disable();
}
memcpy(buffer, nvm_section + address, length);
}
/**
* Write 256-byte page. Address should be page aligned
* Write 64-byte page. Address should be page aligned
*/
void mem_write_page(uint32_t address, uint8_t* buffer, uint16_t length)
{
uint8_t tx_data[4];
#ifdef FIX_ERRATA_REV_C_FLASH_10804
/* save CTRLB and disable cache */
uint32_t temp = NVMCTRL->CTRLB.reg;
NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
#endif
if (memory_init_success) {
_mem_single_command(MEM_OP_WRITE_ENABLE);
address &= PAGE_MASK;
tx_data[0] = MEM_OP_PAGE_PROGRAM;
tx_data[1] = (address >> 16) & 0xFF;
tx_data[2] = (address >> 8) & 0xFF;
tx_data[3] = (address >> 0) & 0xFF;
_mem_cs_enable();
_mem_write(tx_data, 4); _mem_write(buffer, length);
_mem_cs_disable();
/* Wait */
if ((address < MEM_SIZE) && (length <= PAGE_SIZE)) {
/* write address */
NVMCTRL->ADDR.reg = (uint32_t)(nvm_section + address) >> 1;
/* write data. length must be multiple of two */
memcpy((void*)(nvm_section + address), buffer, length & ~0x1);
/* unlock */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_UR;
/* write page */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
_mem_wait_for_done();
_mem_single_command(MEM_OP_WRITE_DISABLE);
/* lock */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_LR;
}
#ifdef FIX_ERRATA_REV_C_FLASH_10804
/* restore CTRLB */
NVMCTRL->CTRLB.reg = temp;
#endif
}
/**
* Erase sector
* Erase 256-byte sector.
*/
void mem_erase_sector(uint32_t address)
{
uint8_t tx_data[4];
#ifdef FIX_ERRATA_REV_C_FLASH_10804
/* save CTRLB and disable cache */
uint32_t temp = NVMCTRL->CTRLB.reg;
NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
#endif
if (memory_init_success) {
_mem_single_command(MEM_OP_WRITE_ENABLE);
address &= SECTOR_MASK;
tx_data[0] = MEM_OP_ERASE_4KB_SECTOR;
tx_data[1] = (address >> 16) & 0xFF;
tx_data[2] = (address >> 8) & 0xFF;
tx_data[3] = (address >> 0) & 0xFF;
_mem_cs_enable();
_mem_write(tx_data, 4);
_mem_cs_disable();
/* Wait */
if (address < MEM_SIZE) {
/* write address */
NVMCTRL->ADDR.reg = (uint32_t)(nvm_section + address) >> 1;
/* unlock */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_UR;
_mem_wait_for_done();
_mem_single_command(MEM_OP_WRITE_DISABLE);
/* erase row */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
_mem_wait_for_done();
/* lock */
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_LR;
}
#ifdef FIX_ERRATA_REV_C_FLASH_10804
/* restore CTRLB */
NVMCTRL->CTRLB.reg = temp;
#endif
}
/**
* Initialise and Power on Memory Interface
*
* Returns 1 on success, 0 on failute
* Returns 1 on success, 0 on failure
*/
uint8_t mem_power_on(void)
{
/* Configure the SPI select pin */
port_pin_set_config(FLASH_CSN_PIN,
PORT_PIN_DIR_OUTPUT, /* Direction */
PORT_PIN_PULL_NONE, /* Pull */
false); /* Powersave */
/* Disable the SEL pin */
_mem_cs_disable();
spi_init(FLASH_SERCOM,
SPI_MODE_MASTER, /** SPI mode */
SPI_DATA_ORDER_MSB, /** Data order */
SPI_TRANSFER_MODE_0, /** Transfer mode */
FLASH_SERCOM_MUX, /** Mux setting */
SPI_CHARACTER_SIZE_8BIT, /** SPI character size */
false, /** Enabled in sleep */
true, /** Enable receiver */
1000*1000, /** Master - Baud rate */
0, /** Slave - Frame format */
0, /** Slave - Address mode */
0, /** Slave - Address */
0, /** Slave - Address mask */
false, /** Slave - Preload data */
GCLK_GENERATOR_0, /** GCLK generator to use */
FLASH_SERCOM_MOSI_PINMUX, /** Pinmux */
FLASH_SERCOM_MISO_PINMUX, /** Pinmux */
FLASH_SERCOM_SCK_PINMUX, /** Pinmux */
PINMUX_UNUSED); /** Pinmux */
spi_enable(FLASH_SERCOM);
/* Release from power down */
mem_exit_deep_power_down();
/* Make 3 attempts to read JEDEC chip ID */
for (int i = 0; i < 3; i++) {
uint32_t jedec = mem_read_jedec_id();
/* Check it's the chip we're expecting */
if (jedec == SST25WF040B_JEDEC_ID) {
/* Correct ID */
memory_init_success = 1;
return 1;
}
}
/* Memory failed to initialise correctly */
return 0;
/* NVMCTRL is enabled by default */
return 1;
}
/**
* Return memory to lowest power state
*/
void mem_power_off(void)
{
if (memory_init_success) {
/* Place memory in deep power down */
mem_enter_deep_power_down();
/* Disable SPI interface */
spi_disable(FLASH_SERCOM);
/* Return pins to default state (lowest power) */
system_pinmux_pin_set_config(FLASH_CSN_PIN,
SYSTEM_PINMUX_GPIO,
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
SYSTEM_PINMUX_PIN_PULL_NONE,
true);
system_pinmux_pin_set_config(FLASH_SERCOM_MOSI_PIN,
SYSTEM_PINMUX_GPIO,
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
SYSTEM_PINMUX_PIN_PULL_NONE,
true);
system_pinmux_pin_set_config(FLASH_SERCOM_MISO_PIN,
SYSTEM_PINMUX_GPIO,
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
SYSTEM_PINMUX_PIN_PULL_NONE,
true);
system_pinmux_pin_set_config(FLASH_SERCOM_SCK_PIN,
SYSTEM_PINMUX_GPIO,
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
SYSTEM_PINMUX_PIN_PULL_NONE,
true);
/* memory is no longer initialised */
memory_init_success = 0;
}
}