strip pointless assert, saves about 6K flash

main-solar-only
Richard Meadows 2016-08-02 18:57:45 +01:00
rodzic ce310d89c6
commit 1e7d8eccd1
16 zmienionych plików z 110 dodań i 113 usunięć

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@ -960,7 +960,7 @@ enum adc_status_code adc_init(Adc *hw,
*/
static inline void adc_get_config_defaults(struct adc_config *const config)
{
Assert(config);
config->clock_source = GCLK_GENERATOR_0;
config->reference = ADC_REFERENCE_INT1V;
config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4;
@ -1046,7 +1046,7 @@ static inline uint32_t adc_get_status(void)
static inline void adc_clear_status(const uint32_t status_flags)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1113,7 +1113,7 @@ static inline bool adc_is_syncing(void)
static inline enum adc_status_code adc_enable(void)
{
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1139,7 +1139,7 @@ static inline enum adc_status_code adc_enable(void)
*/
static inline enum adc_status_code adc_disable(void)
{
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1163,7 +1163,7 @@ static inline enum adc_status_code adc_reset(void)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1195,8 +1195,8 @@ static inline void adc_enable_events(struct adc_events *const events)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Assert(events);
Adc *const adc_module = module_inst.hw;
@ -1230,8 +1230,8 @@ static inline void adc_disable_events(struct adc_events *const events)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Assert(events);
Adc *const adc_module = module_inst.hw;
@ -1260,7 +1260,7 @@ static inline void adc_disable_events(struct adc_events *const events)
static inline void adc_start_conversion(void)
{
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1288,8 +1288,8 @@ static inline void adc_start_conversion(void)
static inline enum adc_status_code adc_read(uint16_t *result)
{
Assert(module_inst.hw);
Assert(result);
if (!(adc_get_status() & ADC_STATUS_RESULT_READY)) {
/* Result not ready */
@ -1335,7 +1335,7 @@ static inline enum adc_status_code adc_read(uint16_t *result)
static inline void adc_flush(void)
{
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1362,7 +1362,7 @@ static inline void adc_set_window_mode(const enum adc_window_mode window_mode,
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1401,7 +1401,7 @@ static inline void adc_set_gain(const enum adc_gain_factor gain_factor)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1441,7 +1441,7 @@ static inline enum adc_status_code adc_set_pin_scan_mode(uint8_t inputs_to_scan,
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1500,7 +1500,7 @@ static inline void adc_set_positive_input(const enum adc_positive_input positive
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1528,7 +1528,7 @@ static inline void adc_set_negative_input(const enum adc_negative_input negative
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
@ -1554,7 +1554,7 @@ static inline void adc_enable_interrupt(enum adc_interrupt_flag interrupt)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
/* Enable interrupt */
@ -1573,7 +1573,7 @@ static inline void adc_disable_interrupt(enum adc_interrupt_flag interrupt)
{
/* Sanity check arguments */
Assert(module_inst.hw);
Adc *const adc_module = module_inst.hw;
/* Enable interrupt */

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@ -587,7 +587,7 @@ struct spi_slave_inst_config {
static inline void spi_slave_inst_get_config_defaults(
struct spi_slave_inst_config *const config)
{
assert(config);
config->ss_pin = 10;
config->address_enabled = false;
@ -606,8 +606,8 @@ static inline void spi_slave_inst_get_config_defaults(
static inline void spi_attach_slave(struct spi_slave_inst *const slave)
// struct spi_slave_inst_config *const config)
{
assert(slave);
// Assert(config);
//
// slave->ss_pin = config->ss_pin;
// slave->address_enabled = config->address_enabled;
@ -658,7 +658,7 @@ enum sercom_status_t spi_init_default(SercomSpi *const hw);
static inline void spi_enable(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
// system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
@ -676,7 +676,7 @@ static inline void spi_enable(SercomSpi* const hw)
static inline void spi_disable(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
// system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
@ -706,7 +706,7 @@ enum sercom_status_t spi_set_baudrate(SercomSpi* const hw,
static inline bool spi_is_write_complete(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Check interrupt flag */
return (hw->INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC);
@ -724,7 +724,7 @@ static inline bool spi_is_write_complete(SercomSpi* const hw)
static inline bool spi_is_ready_to_write(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Check interrupt flag */
return (hw->INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE);
@ -742,7 +742,7 @@ static inline bool spi_is_ready_to_write(SercomSpi* const hw)
static inline bool spi_is_ready_to_read(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Check interrupt flag */
return (hw->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC);
@ -773,7 +773,7 @@ static inline enum sercom_status_t spi_write(SercomSpi* const hw,
uint16_t tx_data)
{
/* Sanity check arguments */
assert(hw);
/* Check if the data register has been copied to the shift register */
if (!spi_is_ready_to_write(hw)) {
@ -812,7 +812,7 @@ static inline enum sercom_status_t spi_read(SercomSpi* const hw,
uint16_t *rx_data)
{
/* Sanity check arguments */
assert(hw);
/* Check if data is ready to be read */
if (!spi_is_ready_to_read(hw)) {

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@ -406,7 +406,7 @@ enum usart_transceiver_type {
static inline void usart_enable(SercomUsart* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Wait until synchronization is complete */
USART_WAIT_FOR_SYNC(hw);
@ -423,7 +423,7 @@ static inline void usart_enable(SercomUsart* const hw)
static inline void usart_disable(SercomUsart* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Wait until synchronization is complete */
USART_WAIT_FOR_SYNC(hw);
@ -440,7 +440,7 @@ static inline void usart_disable(SercomUsart* const hw)
static inline void usart_reset(SercomUsart* const hw)
{
/* Sanity check arguments */
assert(hw);
usart_disable(hw);
@ -461,7 +461,7 @@ static inline void usart_enable_transceiver(SercomUsart* const hw,
enum usart_transceiver_type transceiver_type)
{
/* Sanity check arguments */
assert(hw);
/* Wait until synchronization is complete */
USART_WAIT_FOR_SYNC(hw);
@ -489,7 +489,7 @@ static inline void usart_disable_transceiver(SercomUsart* const hw,
enum usart_transceiver_type transceiver_type)
{
/* Sanity check arguments */
assert(hw);
/* Wait until synchronization is complete */
USART_WAIT_FOR_SYNC(hw);

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@ -132,7 +132,7 @@
*
*/
#include <assert.h>
#include "samd20.h"
#include "system/gclk.h"
@ -508,7 +508,7 @@ static inline void system_main_clock_set_failure_detect(const bool enable)
static inline void system_cpu_clock_set_divider(
const enum system_main_clock_div divider)
{
assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
PM->CPUSEL.reg = (uint32_t)divider;
}
@ -552,7 +552,7 @@ static inline enum clock_status_t system_apb_clock_set_divider(
PM->APBCSEL.reg = (uint32_t)divider;
break;
default:
assert(false);
return CLOCK_STATUS_INVALID_ARG;
}
@ -581,7 +581,7 @@ static inline uint32_t system_apb_clock_get_hz(
bus_divider = PM->APBCSEL.reg;
break;
default:
assert(false);
return 0;
}
@ -652,7 +652,7 @@ static inline enum clock_status_t system_apb_clock_set_mask(
break;
default:
assert(false);
return CLOCK_STATUS_INVALID_ARG;
}
@ -694,7 +694,7 @@ static inline enum clock_status_t system_apb_clock_clear_mask(
break;
default:
assert(false);
return CLOCK_STATUS_INVALID_ARG;
}
@ -834,9 +834,6 @@ void system_clock_init(void);
*/
static inline void system_flash_set_waitstates(const enum system_wait_states wait_states)
{
assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
NVMCTRL->CTRLB.bit.RWS = wait_states;
}

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@ -41,7 +41,7 @@
#ifndef PINMUX_H_INCLUDED
#define PINMUX_H_INCLUDED
#include <assert.h>
#include <stdlib.h>
#include <stdbool.h>
#include "samd20.h"
@ -210,7 +210,6 @@ static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
if (port_index < PORT_INST_NUM) {
return &(ports[port_index]->Group[group_index]);
} else {
assert(false);
return NULL;
}
}

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@ -164,7 +164,7 @@ static inline uint32_t port_group_get_input_level(const PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
assert(port);
return (port->IN.reg & mask);
}
@ -184,7 +184,7 @@ static inline uint32_t port_group_get_output_level(const PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
assert(port);
return (port->OUT.reg & mask);
}
@ -201,7 +201,7 @@ static inline void port_group_set_output_level(PortGroup *const port,
const uint32_t level_mask)
{
/* Sanity check arguments */
assert(port);
port->OUTSET.reg = (mask & level_mask);
port->OUTCLR.reg = (mask & ~level_mask);
@ -217,7 +217,7 @@ static inline void port_group_toggle_output_level(PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
assert(port);
port->OUTTGL.reg = mask;
}

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@ -244,7 +244,7 @@ static inline void system_voltage_reference_enable(
break;
default:
assert(false);
return;
}
}
@ -267,7 +267,7 @@ static inline void system_voltage_reference_disable(
break;
default:
assert(false);
return;
}
}

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@ -137,7 +137,7 @@ static inline void _adc_configure_ain_pin(uint32_t pin)
if (pin <= ADC_EXTCHANNEL_MSB) {
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
system_pinmux_pin_set_config(pin_map_result,
1, // B
@ -487,8 +487,8 @@ enum adc_status_code adc_init(Adc *hw,
{
/* Sanity check arguments */
Assert(hw);
Assert(config);
/* Associate the software module instance with the hardware module */
module_inst.hw = hw;
@ -582,7 +582,7 @@ void adc_register_callback(
enum adc_callback callback_type)
{
/* Sanity check arguments */
Assert(callback_func);
/* Register callback function */
module_inst.callback[callback_type] = callback_func;
@ -632,8 +632,8 @@ enum adc_status_code adc_read_buffer_job(
uint16_t *buffer,
uint16_t samples)
{
Assert(samples);
Assert(buffer);
if(module_inst.remaining_conversions != 0 ||
module_inst.job_status == ADC_STATUS_BUSY){

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@ -67,7 +67,7 @@ uint8_t _sercom_get_sercom_inst_index(Sercom *const sercom_instance)
}
/* Invalid data given. */
assert(false);
while (1);
return 0;
}
@ -292,6 +292,6 @@ uint32_t _sercom_get_default_pad(Sercom* const sercom_module,
#endif
}
assert(false);
while(1);
return 0;
}

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@ -59,7 +59,7 @@
void spi_reset(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Disable the module */
spi_disable(hw);
@ -86,7 +86,7 @@ enum sercom_status_t spi_set_baudrate(SercomSpi* const hw,
uint32_t baudrate)
{
/* Sanity check arguments */
assert(hw);
/* Value to write to BAUD register */
uint16_t baud = 0;
@ -130,7 +130,7 @@ enum sercom_status_t spi_set_baudrate(SercomSpi* const hw,
static void _spi_clear_tx_complete_flag(SercomSpi* const hw)
{
/* Sanity check arguments */
assert(hw);
/* Clear interrupt flag */
hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
@ -177,7 +177,7 @@ enum sercom_status_t spi_init(SercomSpi *const hw,
{
/* Sanity check arguments */
assert(hw);
/* Check if module is enabled. */
if (hw->CTRLA.reg & SERCOM_SPI_CTRLA_ENABLE) {
@ -392,7 +392,7 @@ enum sercom_status_t spi_read_buffer_wait(SercomSpi* const hw,
uint16_t dummy)
{
/* Sanity check arguments */
assert(hw);
/* Sanity check arguments */
if (length == 0) {
@ -462,7 +462,7 @@ enum sercom_status_t spi_transceive_wait(SercomSpi* const hw,
uint16_t *rx_data)
{
/* Sanity check arguments */
assert(hw);
uint16_t j;
enum sercom_status_t retval = SERCOM_STATUS_OK;
@ -535,7 +535,7 @@ enum sercom_status_t spi_select_slave(SercomSpi* const hw,
const bool select)
{
/* Sanity check arguments */
assert(hw);
/* Check that the SPI module is operating in master mode */
if (!SPI_MODE_MASTER(hw)) {
@ -607,7 +607,7 @@ enum sercom_status_t spi_write_buffer_wait(SercomSpi* const hw,
uint16_t length)
{
/* Sanity check arguments */
assert(hw);
if (length == 0) {
return SERCOM_STATUS_INVALID_ARG;
@ -679,7 +679,7 @@ enum sercom_status_t spi_transceive_buffer_wait(SercomSpi* const hw,
uint16_t length)
{
/* Sanity check arguments */
assert(hw);
/* Sanity check arguments */
if (length == 0) {

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@ -98,7 +98,7 @@ enum sercom_status_t usart_init(SercomUsart* const hw,
{
/* Sanity check arguments */
assert(hw);
/* Unused */
(void)encoding_format_enable;
@ -347,7 +347,7 @@ enum sercom_status_t usart_write_wait(SercomUsart* const hw,
const uint16_t tx_data)
{
/* Sanity check arguments */
assert(hw);
/* Check if USART is ready for new data */
if (!(hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
@ -394,7 +394,7 @@ enum sercom_status_t usart_read_wait(SercomUsart* const hw,
uint16_t *const rx_data)
{
/* Sanity check arguments */
assert(hw);
/* Error variable */
uint8_t error_code;
@ -480,7 +480,7 @@ enum sercom_status_t usart_write_buffer_wait(SercomUsart* const hw,
uint16_t length)
{
/* Sanity check arguments */
assert(hw);
/* Wait until synchronization is complete */
USART_WAIT_FOR_SYNC(hw);
@ -558,7 +558,7 @@ enum sercom_status_t usart_read_buffer_wait(SercomUsart* hw,
uint16_t length)
{
/* Sanity check arguments */
assert(hw);
uint16_t rx_pos = 0;

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@ -564,7 +564,7 @@ enum clock_status_t system_clock_source_enable(
return CLOCK_STATUS_OK;
default:
assert(false);
while(1);
return CLOCK_STATUS_INVALID_ARG;
}
@ -608,7 +608,7 @@ enum clock_status_t system_clock_source_disable(
/* Not possible to disable */
default:
assert(false);
while(1);
return CLOCK_STATUS_INVALID_ARG;
}

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@ -342,7 +342,9 @@ void system_gclk_chan_disable(const uint8_t channel)
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
/* Sanity check WRTLOCK */
assert(!GCLK->CLKCTRL.bit.WRTLOCK);
if(GCLK->CLKCTRL.bit.WRTLOCK) {
while(1);
}
/* Switch to known-working source so that the channel can be disabled */
uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;

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@ -41,7 +41,6 @@
#include "system/interrupt.h"
#include <stdbool.h>
#include <assert.h>
static volatile uint32_t cpu_irq_critical_section_counter;
static volatile bool cpu_irq_prev_interrupt_state;
@ -64,7 +63,9 @@ void cpu_irq_leave_critical(void)
{
/* Check if the user is trying to leave a critical section when not
* in a critical section */
assert(cpu_irq_critical_section_counter > 0);
if(cpu_irq_critical_section_counter == 0) {
while (1);
}
cpu_irq_critical_section_counter--;

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@ -61,7 +61,7 @@ static void _system_pinmux_config(PortGroup *const port,
const enum system_pinmux_pin_pull input_pull,
bool powersave)
{
assert(port);
/* Track the configuration bits into a temporary variable before writing */
uint32_t pin_cfg = 0;
@ -181,7 +181,7 @@ void system_pinmux_group_set_config(PortGroup *const port,
const enum system_pinmux_pin_pull input_pull,
bool powersave)
{
assert(port);
for (int i = 0; i < 32; i++) {
if (mask & (1UL << i)) {
@ -203,7 +203,7 @@ void system_pinmux_group_set_input_sample_mode(PortGroup *const port,
const uint32_t mask,
const enum system_pinmux_pin_sample mode)
{
assert(port);
if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
port->CTRL.reg |= mask;

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@ -39,8 +39,6 @@
*
*/
#include <assert.h>
#include "system/clock.h"
#include "tc/tc_driver.h"
#include "samd20.h"
@ -73,7 +71,7 @@
*/
void tc_enable(Tc* const hw)
{
assert(hw);
WAIT_FOR_SYNC(hw);
@ -85,7 +83,7 @@ void tc_enable(Tc* const hw)
*/
void tc_disable(Tc* const hw)
{
assert(hw);
WAIT_FOR_SYNC(hw);
@ -98,7 +96,7 @@ void tc_disable(Tc* const hw)
*/
void tc_start_counter(Tc* const hw)
{
assert(hw);
/* Make certain that there are no conflicting commands in the register */
WAIT_FOR_SYNC(hw);
@ -116,7 +114,7 @@ void tc_start_counter(Tc* const hw)
*/
void tc_stop_counter(Tc* const hw)
{
assert(hw);
WAIT_FOR_SYNC(hw);
@ -137,7 +135,7 @@ void tc_stop_counter(Tc* const hw)
*/
uint32_t tc_get_status(Tc* const hw)
{
assert(hw);
uint32_t int_flags = hw->COUNT8.INTFLAG.reg;
uint32_t status_flags = 0;
@ -177,7 +175,7 @@ uint32_t tc_get_status(Tc* const hw)
void tc_clear_status(Tc* const hw,
const uint32_t status_flags)
{
assert(hw);
uint32_t int_flags = 0;
@ -220,20 +218,20 @@ void tc_clear_status(Tc* const hw,
*/
void tc_set_count_value(Tc* const hw, const uint32_t count)
{
assert(hw);
WAIT_FOR_SYNC(hw);
/* Write to based on the TC counter_size */
switch (hw->COUNT8.CTRLA.reg & TC_CTRLA_MODE_Msk) {
case TC_COUNTER_SIZE_8BIT:
assert((count & ~0xFF) == 0);
hw->COUNT8.COUNT.reg = (uint8_t)count;
return;
case TC_COUNTER_SIZE_16BIT:
assert((count & ~0xFFFF) == 0);
hw->COUNT16.COUNT.reg = (uint16_t)count;
return;
@ -243,7 +241,7 @@ void tc_set_count_value(Tc* const hw, const uint32_t count)
return;
default:
assert(TC_ERROR_INVALID_STATE);
while (1);
}
}
@ -257,7 +255,7 @@ void tc_set_count_value(Tc* const hw, const uint32_t count)
*/
uint32_t tc_get_count_value(Tc* const hw)
{
assert(hw);
WAIT_FOR_SYNC(hw);
@ -273,7 +271,7 @@ uint32_t tc_get_count_value(Tc* const hw)
return hw->COUNT32.COUNT.reg;
default:
assert(TC_ERROR_INVALID_STATE);
return 0;
}
}
@ -289,7 +287,7 @@ uint32_t tc_get_count_value(Tc* const hw)
uint32_t tc_get_capture_value(Tc* const hw,
const enum tc_compare_capture_channel channel_index)
{
assert(hw);
WAIT_FOR_SYNC(hw);
@ -311,11 +309,11 @@ uint32_t tc_get_capture_value(Tc* const hw,
}
default:
assert(TC_ERROR_INVALID_STATE);
return 0;
}
assert(TC_ERROR_INVALID_ARG);
return 0;
}
@ -335,7 +333,7 @@ void tc_set_compare_value(Tc* const hw,
const enum tc_compare_capture_channel channel_index,
const uint32_t compare)
{
assert(hw);
WAIT_FOR_SYNC(hw);
@ -360,12 +358,12 @@ void tc_set_compare_value(Tc* const hw,
}
default:
assert(TC_ERROR_INVALID_STATE);
return;
}
/* Channel index was wrong */
assert(TC_ERROR_INVALID_ARG);
return;
}
@ -384,7 +382,7 @@ static inline uint32_t tc_get_instance_number(Tc* const hw)
}
}
assert(TC_ERROR_INVALID_DEVICE);
return 0;
}
/**
@ -405,7 +403,7 @@ const Tc* tc_get_slave_instance(Tc* const hw) {
}
}
assert(TC_ERROR_NO_32BIT_SLAVE_EXISTS);
return 0;
}
@ -428,7 +426,7 @@ const Tc* tc_get_slave_instance(Tc* const hw) {
void tc_reset(Tc* const hw)
{
if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
assert(TC_ERROR_INVALID_DEVICE);
return;
}
@ -474,12 +472,12 @@ void tc_set_top_value(Tc* const hw,
switch (hw->COUNT8.CTRLA.reg & TC_CTRLA_MODE_Msk) {
case TC_COUNTER_SIZE_8BIT:
assert((top_value & ~0xFF) == 0);
hw->COUNT8.PER.reg = (uint8_t)top_value;
return;
case TC_COUNTER_SIZE_16BIT:
assert((top_value & ~0xFFFF) == 0);
hw->COUNT16.CC[0].reg = (uint16_t)top_value;
return;
@ -488,7 +486,7 @@ void tc_set_top_value(Tc* const hw,
return;
default:
assert(TC_ERROR_INVALID_STATE);
while(1);
}
return;
@ -509,8 +507,8 @@ void tc_enable_events(Tc* const hw,
struct tc_events *const events)
{
/* Sanity check arguments */
assert(hw);
assert(events);
uint32_t event_mask = 0;
@ -547,8 +545,8 @@ void tc_enable_events(Tc* const hw,
void tc_disable_events(Tc* const hw,
struct tc_events *const events)
{
assert(hw);
assert(events);
uint32_t event_mask = 0;
@ -594,7 +592,7 @@ enum tc_status_t tc_init(Tc* const hw,
bool* enable_capture_channels,
uint32_t* compare_channel_values)
{
assert(hw);
const Tc* slave;
uint16_t ctrla_tmp = 0;