kopia lustrzana https://github.com/bristol-seds/pico-tracker
Remove si4060.c / si4060.h. They haven't been used for a while
Richard Meadows
rodzic
262a3b29a6
commit
1624057970
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@ -1,223 +0,0 @@
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/*
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* si4060 software library
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*
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* Stefan Biereigel
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*
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*/
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#ifndef SI4060_H_
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#define SI4060_H_
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#include <inttypes.h>
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#include "samd20.h"
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#include "system/port.h"
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#include "hw_config.h"
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/**
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* Chip Select. Active Low (High = Inactive, Low = Active)
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*/
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#define _si406x_cs_enable() \
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port_pin_set_output_level(SI406X_SEL_PIN, 0)
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#define _si406x_cs_disable() \
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port_pin_set_output_level(SI406X_SEL_PIN, 1)
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#define spi_select _si406x_cs_enable
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#define spi_deselect _si406x_cs_disable
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#define spi_write spi_bitbang_transfer
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#define spi_read() spi_bitbang_transfer(0xff)
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#define __delay_cycles(n) do { \
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for (int cyc = 0; cyc < n; cyc++) { __NOP(); } \
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} while(0)
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void si4060_shutdown(void);
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#define XO_FREQ 16369000UL
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#define RF_FREQ_HZ 434600000.0f
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#define RF_DEV_HZ 200.0f
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#define F_INT (2 * XO_FREQ / 8)
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#define FDIV_INTE ( (RF_FREQ_HZ / F_INT) - 1)
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#define FDIV_FRAC ( (RF_FREQ_HZ - F_INT*(int)FDIV_INTE) * ((uint32_t)1 << 19) ) / F_INT
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#define FDEV ( ( ( (uint32_t)1 << 19) * 8 * RF_DEV_HZ)/ (2*XO_FREQ))
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/* function prototypes */
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void si4060_shutdown (void);
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void si4060_wakeup (void);
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void si4060_reset (void);
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void si4060_power_up (void);
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void si4060_nop (void);
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uint8_t si4060_get_state(void);
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void si4060_get_freq(void);
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float si4060_get_temperature(void);
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void si4060_start_tx (uint8_t channel);
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void si4060_stop_tx (void);
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void si4060_setup (uint8_t mod_type);
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uint8_t si4060_get_property_8 (uint8_t group, uint8_t prop);
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uint16_t si4060_part_info (void);
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/* ===== command definitions ===== */
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#define CMD_NOP 0x00
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#define CMD_PART_INFO 0x01
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#define CMD_POWER_UP 0x02
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#define CMD_SET_PROPERTY 0x11
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#define CMD_GET_PROPERTY 0x12
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#define CMD_GPIO_PIN_CFG 0x13
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#define CMD_START_TX 0x31
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#define CMD_REQUEST_STATE 0x33
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#define CMD_CHANGE_STATE 0x34
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#define CMD_READ_CMD_BUF 0x44
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#define CMD_GET_ADC_READING 0x14
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/* ===== device states ===== */
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#define STATE_NOCHANGE 0x00
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#define STATE_SLEEP 0x01
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#define STATE_SPI_ACTIVE 0x02
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#define STATE_READY 0x03
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#define STATE_TX_TUNE 0x05
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#define STATE_TXA 0x07
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/* ===== property group definitions ===== */
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#define PROP_GLOBAL 0x00
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#define PROP_INT_CTL 0x01
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#define PROP_FRR_CTL 0x02
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#define PROP_PREAMBLE 0x10
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#define PROP_SYNC 0x11
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#define PROP_PKT 0x12
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#define PROP_MODEM 0x20
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#define PROP_PA 0x22
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#define PROP_SYNTH 0x23
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#define PROP_FREQ_CONTROL 0x40
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/* ===== property definitions ===== */
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/* global properties */
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#define GLOBAL_XO_TUNE 0x00
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#define GLOBAL_CONFIG 0x03
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/* preamble properties */
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#define PREAMBLE_TX_LENGTH 0x00
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/* sync properties */
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#define SYNC_CONFIG 0x11
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/* modem properties */
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#define MODEM_MOD_TYPE 0x00
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#define MODEM_FREQ_DEV 0x0a
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#define MODEM_FREQ_OFFSET 0x0d
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#define MODEM_CLKGEN_BAND 0x51
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/* PA properties */
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#define PA_MODE 0x00
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#define PA_PWR_LVL 0x01
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#define PA_BIAS_CLKDUTY 0x02
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/* synthesizer properties */
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#define SYNTH_PFDCP_CPFF 0x00
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#define SYNTH_PFDCP_CPINT 0x01
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#define SYNTH_VCO_KV 0x02
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#define SYNTH_LPFILT3 0x03
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#define SYNTH_LPFILT2 0x04
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#define SYNTH_LPFILT1 0x05
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#define SYNTH_LPFILT0 0x06
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#define SYNTH_VCO_KVCAL 0x07
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/* frequency control properties */
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/* INTE shall be decreased by 1, because FRAC shall be between 1 and 2 */
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#define FREQ_CONTROL_INTE 0x00
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/* FRAC shall be added to 2**19, to ensure MSB is set! */
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#define FREQ_CONTROL_FRAC 0x01
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#define FREQ_CONTROL_CHANNEL_STEP_SIZE 0x04
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#define FREQ_CONTROL_W_SIZE 0x06
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/* ===== command arguments ===== */
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/* POWER_UP arguments */
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/* byte 1 */
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#define PATCH ( 0x01 << 7) /* set patch mode */
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#define FUNC 0x01 /* power on device */
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/* byte 2 */
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#define TCXO 0x01/* select if TCXO (1) or crystal (0) is used */
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/* GPIO_PIN_CFG arguments */
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/* bytes 1 .. 6 */
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#define PULL_CTL 0x40 /* enable or disable pull-up resistor */
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/* bytes 1 .. 4 */
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#define GPIO_MODE_DONOTHING 0x00/* pin behaviour is not changed */
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#define GPIO_MODE_TRISTATE 0x01/* input and output drivers are disabled */
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#define GPIO_MODE_DRIVE0 0x02/* CMOS output "low" */
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#define GPIO_MODE_DRIVE1 0x03/* CMOS output "high" */
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#define GPIO_MODE_INPUT 0x04/* GPIO is input, for TXDATA etc, function is not configured here */
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#define GPIO_MODE_32K_CLK 0x05/* outputs the 32kHz CLK when selected in CLK32_CLK_SEL */
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#define GPIO_MODE_BOOT_CLK 0x06/* outputs boot clock when SPI_ACTIVE */
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#define GPIO_MODE_DIV_CLK 0x07/* outputs divided xtal clk */
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#define GPIO_MODE_CTS 0x08/* output, '1' when device is ready to accept new command */
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#define GPIO_MODE_INV_CNT 0x09/* output, inverted CTS */
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#define GPIO_MODE_CMD_OVERLAP 0x0a/* output, '1' if a command was issued while not ready */
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#define GPIO_MODE_SDO 0x0b/* output, serial data out for SPI */
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#define GPIO_MODE_POR 0x0c/* output, '0' while in POR state */
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#define GPIO_MODE_CAL_WUT 0x0d/* output, '1' on expiration of wake up timer */
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#define GPIO_MODE_WUT 0x0e/* wake up timer output */
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#define GPIO_MODE_EN_PA 0x0f/* output, '1' when PA is enabled */
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#define GPIO_MODE_TX_DATA_CLK 0x10/* data clock output, for TX direct sync mode */
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#define GPIO_MODE_TX_DATA 0x11/* data output from TX FIFO, for debugging purposes */
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#define GPIO_MODE_IN_SLEEP 0x12/* output, '0' when in sleep state */
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#define GPIO_MODE_TX_STATE 0x13/* output, '1' when in TX state */
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#define GPIO_MODE_TX_FIFO_EMPTY 0x14/* output, '1' when FIFO is empty */
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#define GPIO_MODE_LOW_BATT 0x15/* output, '1' if low battery is detected */
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/* byte 5 omitted - no IRQ support */
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#define NIRQ_MODE_DONOTHING 0x00
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/* byte 6 omitted - no SDO reconfiguration support */
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#define SDO_MODE_DONOTHING 0x00
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/* byte 7 */
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#define DRV_STRENGTH_HIGH ( 0x00 << 5)
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#define DRV_STRENGTH_MED_HIGH ( 0x01 << 5)
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#define DRV_STRENGTH_MED_LOW ( 0x02 << 5)
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#define DRV_STRENGTH_LOW ( 0x03 << 5)
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/* START_TX arguments */
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/* byte 2 */
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#define START_TX_TXC_STATE_NOCHANGE ( 0x00 << 4)
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#define START_TX_TXC_STATE_SLEEP ( 0x01 << 4)
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#define START_TX_TXC_STATE_SPI_ACTIVE ( 0x02 << 4)
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#define START_TX_TXC_STATE_READY ( 0x03 << 4)
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#define START_TX_RETRANSMIT_0 ( 0x00 << 2)/* send data that has been written to the TX FIFO */
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#define START_TX_START_IMM ( 0x00 << 0)/* start transmission immediately */
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/* ===== property values ===== */
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/* GLOBAL_CONFIG values */
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#define GLOBAL_RESERVED ( 0x01 << 6) /* shall be set to 1 */
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#define POWER_MODE_LOW_POWER 0x00/* default */
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#define POWER_MODE_HIGH_PERF 0x01
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#define SEQUENCER_MODE_FAST ( 0x00 << 5)/* default */
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#define SEQUENCER_MODE_GUARANT ( 0x01 << 5)
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/* SYNC_CONFIG values */
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#define SYNC_XMIT ( 0x00 << 7)/* default */
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#define SYNC_NO_XMIT ( 0x01 << 7)
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/* MODEM_MOD_TYPE values */
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#define MOD_TYPE_CW 0x00
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#define MOD_TYPE_OOK 0x01
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#define MOD_TYPE_2FSK 0x02/* default */
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#define MOD_TYPE_2GFSK 0x03
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#define MOD_TYPE_4FSK 0x04
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#define MOD_TYPE_4GFSK 0x05
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#define MOD_SOURCE_PACKET ( 0x00 << 3) /* default */
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#define MOD_SOURCE_DIRECT ( 0x01 << 3)
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#define MOD_SOURCE_PSEUDO ( 0x02 << 3)
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#define MOD_GPIO_0 ( 0x00 << 5) /* default */
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#define MOD_GPIO_1 ( 0x01 << 5)
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#define MOD_GPIO_2 ( 0x02 << 5)
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#define MOD_GPIO_3 ( 0x03 << 5)
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#define MOD_DIRECT_MODE_SYNC ( 0x00 << 7) /* default */
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#define MOD_DIRECT_MODE_ASYNC ( 0x01 << 7)
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/* MODEM_CLKGEN_BAND values */
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#define SY_SEL_0 ( 0x00 << 3) /* low power */
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#define SY_SEL_1 ( 0x01 << 3) /* default */
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#define FVCO_DIV_4 0x00 /* default */
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#define FVCO_DIV_6 0x01
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#define FVCO_DIV_8 0x02 /* for 70cm ISM band */
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#define FVCO_DIV_12 0x03
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#define FVCO_DIV_16 0x04
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#define FVCO_DIV_24 0x05
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#define FVCO_DIV_24_2 0x06
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#define FVCO_DIV_24_3 0x07
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/* PA_MODE values*/
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/* PA_BIAS_CLKDUTY values */
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#define PA_BIAS_CLKDUTY_SIN_25 (0x03 << 6) /* for si4060 */
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#define PA_BIAS_CLKDUTY_DIFF_50 (0x00 << 6) /* for si4063 */
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#endif
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@ -1,481 +0,0 @@
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/*
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* si4060 software library
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*
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* API description: see EZRadioPRO-API-v1.1.2.zip
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*
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* Stefan Biereigel
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*
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*/
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#include <inttypes.h>
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#include "spi_bitbang.h"
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#include "si4060.h"
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#include "samd20.h"
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#include "semihosting.h"
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#include "hw_config.h"
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#include "system/port.h"
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/*
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* si4060_shutdown
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*
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* makes the Si4060 go to shutdown state.
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* all register content is lost.
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*/
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void si4060_shutdown(void) {
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//P1OUT |= SI_SHDN;
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port_pin_set_output_level(SI406X_SDN_PIN, 1);
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/* wait 10us */
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__delay_cycles(2000);
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}
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/*
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* si4060_wakeup
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*
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* wakes up the Si4060 from shutdown state.
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* si4060_power_up and si4060_setup have to be called afterwards
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*/
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void si4060_wakeup(void) {
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//P1OUT &= ~SI_SHDN;
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port_pin_set_output_level(SI406X_SDN_PIN, 0);
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/* wait 20ms */
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__delay_cycles(20000);
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}
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/*
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* si4060_reset
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*
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* cleanly does the POR as specified in datasheet
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*/
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void si4060_reset(void) {
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si4060_shutdown();
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si4060_wakeup();
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}
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/*
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* si4060_read_cmd_buf
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*
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* reads the Si4060 command buffer from via SPI
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*
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* deselect: whether to deselect the slave after reading the response or not.
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* any command reading subsequent bytes after the CTS should use this
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* function to get CTS and continue doing spi_read afterwards
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* and finally deselecting the slave.
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*
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* returns:the value of the first command buffer byte (i.e. CTS or not)
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*/
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uint8_t si4060_read_cmd_buf(uint8_t deselect) {
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uint8_t ret;
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spi_select();
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spi_write(CMD_READ_CMD_BUF);
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ret = spi_read();
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if (deselect) {
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spi_deselect();
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}
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return ret;
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}
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/*
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* si4060_power_up
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*
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* powers up the Si4060 by issuing the POWER_UP command
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*
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* warning: the si4060 can lock after issuing this command if input clock
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* is not available for the internal RC oscillator calibration.
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*/
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void si4060_power_up(void) {
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/* wait for CTS */
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while (si4060_read_cmd_buf(1) != 0xff);
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spi_select();
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spi_write(CMD_POWER_UP);
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spi_write(FUNC);
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spi_write(0x01);/* TCXO used */
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spi_write((uint8_t) (XO_FREQ >> 24));
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spi_write((uint8_t) (XO_FREQ >> 16));
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spi_write((uint8_t) (XO_FREQ >> 8));
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spi_write((uint8_t) XO_FREQ);
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spi_deselect();
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/* wait for CTS */
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while (si4060_read_cmd_buf(1) != 0xff);
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}
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/*
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* si4060_change_state
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*
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* changes the internal state machine state of the Si4060
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*/
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void si4060_change_state(uint8_t state) {
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spi_select();
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spi_write(CMD_CHANGE_STATE);
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spi_write(state);
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spi_deselect();
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while (si4060_read_cmd_buf(1) != 0xff);
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}
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/*
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* si4060_nop
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*
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* implements the NOP command on the Si4060
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*/
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void si4060_nop(void) {
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spi_select();
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spi_write(CMD_NOP);
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spi_deselect();
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while (si4060_read_cmd_buf(1) != 0xff);
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}
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/*
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* si4060_set_property_8
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*
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* sets an 8 bit (1 byte) property in the Si4060
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*
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* group:the group number of the property
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* prop:the number (index) of the property
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* val:the value to set
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*/
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void si4060_set_property_8(uint8_t group, uint8_t prop, uint8_t val) {
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spi_select();
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spi_write(CMD_SET_PROPERTY);
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spi_write(group);
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spi_write(1);
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spi_write(prop);
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spi_write(val);
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spi_deselect();
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while (si4060_read_cmd_buf(1) != 0xff);
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}
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/*
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* si4060_get_property_8
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*
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* gets an 8 bit (1 byte) property in the Si4060
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*
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* group:the group number of the property
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* prop:the number (index) of the property
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*
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* returns:the value of the property
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*/
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uint8_t si4060_get_property_8(uint8_t group, uint8_t prop) {
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uint8_t temp = 0;
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spi_select();
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spi_write(CMD_GET_PROPERTY);
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spi_write(group);
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spi_write(1);
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spi_write(prop);
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spi_deselect();
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while (temp != 0xff) {
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temp = si4060_read_cmd_buf(0);
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if (temp != 0xff) {
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spi_deselect();
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}
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}
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temp = spi_read(); /* read property */
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spi_deselect();
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return temp;
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}
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/*
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* si4060_set_property_16
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*
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* sets an 16 bit (2 byte) property in the Si4060
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*
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* group:the group number of the property
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* prop:the number (index) of the property
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* val:the value to set
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*/
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void si4060_set_property_16(uint8_t group, uint8_t prop, uint16_t val) {
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spi_select();
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spi_write(CMD_SET_PROPERTY);
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spi_write(group);
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spi_write(2);
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spi_write(prop);
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spi_write(val >> 8);
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spi_write(val);
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spi_deselect();
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while (si4060_read_cmd_buf(1) != 0xff);
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}
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/*
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* si4060_set_property_24
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*
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* sets an 24 bit (3 byte) property in the Si4060
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*
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* group:the group number of the property
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* prop:the number (index) of the property
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* val:the value to set
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*/
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void si4060_set_property_24(uint8_t group, uint8_t prop, uint32_t val) {
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spi_select();
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||||
spi_write(CMD_SET_PROPERTY);
|
||||
spi_write(group);
|
||||
spi_write(3);
|
||||
spi_write(prop);
|
||||
spi_write(val >> 16);
|
||||
spi_write(val >> 8);
|
||||
spi_write(val);
|
||||
spi_deselect();
|
||||
while (si4060_read_cmd_buf(1) != 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_set_property_32
|
||||
*
|
||||
* sets an 32 bit (4 byte) property in the Si4060
|
||||
*
|
||||
* group:the group number of the property
|
||||
* prop:the number (index) of the property
|
||||
* val:the value to set
|
||||
*/
|
||||
void si4060_set_property_32(uint8_t group, uint8_t prop, uint32_t val) {
|
||||
spi_select();
|
||||
spi_write(CMD_SET_PROPERTY);
|
||||
spi_write(group);
|
||||
spi_write(4);
|
||||
spi_write(prop);
|
||||
spi_write(val >> 24);
|
||||
spi_write(val >> 16);
|
||||
spi_write(val >> 8);
|
||||
spi_write(val);
|
||||
spi_deselect();
|
||||
while (si4060_read_cmd_buf(1) != 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_gpio_pin_cfg
|
||||
*
|
||||
* configures the GPIOs on the Si4060
|
||||
* see the GPIO_*-defines for reference
|
||||
*
|
||||
* gpio(0..3):setting flags for respective GPIOs
|
||||
* drvstrength:the driver strength
|
||||
*/
|
||||
void si4060_gpio_pin_cfg(uint8_t gpio0, uint8_t gpio1, uint8_t gpio2, uint8_t gpio3, uint8_t drvstrength) {
|
||||
spi_select();
|
||||
spi_write(CMD_GPIO_PIN_CFG);
|
||||
spi_write(gpio0);
|
||||
spi_write(gpio1);
|
||||
spi_write(gpio2);
|
||||
spi_write(gpio3);
|
||||
spi_write(NIRQ_MODE_DONOTHING);
|
||||
spi_write(SDO_MODE_DONOTHING);
|
||||
spi_write(drvstrength);
|
||||
spi_deselect();
|
||||
while (si4060_read_cmd_buf(1) != 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_part_info
|
||||
*
|
||||
* gets the PART_ID from the Si4060
|
||||
* this can be used to check for successful communication.
|
||||
* as the SPI bus returns 0xFF (MISO=high) when no slave is connected,
|
||||
* reading CTS can not verify communication to the Si4060.
|
||||
*
|
||||
* returns:the PART_ID - should be 0x4060
|
||||
*/
|
||||
uint16_t si4060_part_info(void) {
|
||||
uint16_t temp;
|
||||
|
||||
temp = 0;
|
||||
spi_select();
|
||||
spi_write(CMD_PART_INFO);
|
||||
spi_deselect();
|
||||
/* do not deselect after reading CTS */
|
||||
while (temp != 0xff) {
|
||||
temp = si4060_read_cmd_buf(0);
|
||||
if (temp != 0xff) {
|
||||
spi_deselect();
|
||||
}
|
||||
}
|
||||
spi_read(); /* ignore CHIPREV */
|
||||
temp = spi_read(); /* read PART[0] */
|
||||
temp = temp << 8;
|
||||
temp |= spi_read(); /* read PART[1] */
|
||||
spi_deselect();
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* si4060_get_state
|
||||
*
|
||||
* gets the current state of the Si4060
|
||||
*/
|
||||
uint8_t si4060_get_state(void)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
temp = 0;
|
||||
spi_select();
|
||||
spi_write(CMD_REQUEST_STATE);
|
||||
spi_deselect();
|
||||
/* do not deselect after reading CTS */
|
||||
while (temp != 0xff) {
|
||||
temp = si4060_read_cmd_buf(0);
|
||||
if (temp != 0xff) {
|
||||
spi_deselect();
|
||||
}
|
||||
}
|
||||
temp = spi_read() & 0x0F; /* Get MAIN_STATE */
|
||||
spi_deselect();
|
||||
return temp;
|
||||
}
|
||||
/**
|
||||
* si4060_get_freq
|
||||
*/
|
||||
void si4060_get_freq(void)
|
||||
{
|
||||
uint32_t inte, frac;
|
||||
uint16_t temp;
|
||||
|
||||
spi_select();
|
||||
spi_write(CMD_GET_PROPERTY);
|
||||
spi_write(PROP_FREQ_CONTROL);
|
||||
spi_write(0x4);
|
||||
spi_write(FREQ_CONTROL_INTE);
|
||||
spi_deselect();
|
||||
/* do not deselect after reading CTS */
|
||||
while (temp != 0xff) {
|
||||
temp = si4060_read_cmd_buf(0);
|
||||
if (temp != 0xff) {
|
||||
spi_deselect();
|
||||
}
|
||||
}
|
||||
|
||||
inte = spi_read(); /* Get FREQ_CONTROL_INTE */
|
||||
|
||||
frac = (spi_read() << 16); /* Get FREQ_CONTROL_FRAC MSB */
|
||||
frac |= (spi_read() << 8); /* Get FREQ_CONTROL_FRAC */
|
||||
frac |= (spi_read() << 0); /* Get FREQ_CONTROL_FRAC LSB */
|
||||
spi_deselect();
|
||||
|
||||
semihost_printf("INTE = 0x%02x, FRAC = 0x%06x\n", inte, frac);
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_get_temperature
|
||||
*
|
||||
* gets the temperature
|
||||
*/
|
||||
float si4060_get_temperature(void)
|
||||
{
|
||||
uint16_t temp, result;
|
||||
|
||||
spi_select();
|
||||
spi_write(CMD_GET_ADC_READING);
|
||||
spi_write(0x10); /* Temperature */
|
||||
spi_write(0); /* ADC_CFG = 0 */
|
||||
spi_deselect();
|
||||
|
||||
/* do not deselect after reading CTS */
|
||||
while (temp != 0xff) {
|
||||
temp = si4060_read_cmd_buf(0);
|
||||
if (temp != 0xff) {
|
||||
spi_deselect();
|
||||
}
|
||||
}
|
||||
|
||||
/* GPIO */
|
||||
spi_read(); spi_read();
|
||||
|
||||
/* Battery */
|
||||
spi_read(); spi_read();
|
||||
|
||||
/* Temperature */
|
||||
result = (spi_read() & 0xFF) << 8;
|
||||
result |= (spi_read() & 0xFF);
|
||||
|
||||
spi_deselect();
|
||||
|
||||
return (((float)result * 568.0) / 2560.0) - 297.0;
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_start_tx
|
||||
*
|
||||
* starts transmission by the Si4060.
|
||||
*
|
||||
* channel:the channel to start transmission on
|
||||
*/
|
||||
void si4060_start_tx(uint8_t channel) {
|
||||
spi_select();
|
||||
spi_write(CMD_START_TX);
|
||||
spi_write(channel);
|
||||
spi_write(START_TX_TXC_STATE_SLEEP | START_TX_RETRANSMIT_0 | START_TX_START_IMM);
|
||||
/* set length to 0 for direct mode (is this correct?) */
|
||||
spi_write(0x00);
|
||||
spi_write(0x00);
|
||||
spi_deselect();
|
||||
while (si4060_read_cmd_buf(1) != 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_stop_tx
|
||||
*
|
||||
* makes the Si4060 stop all transmissions by transistioning to SLEEP state
|
||||
*/
|
||||
void si4060_stop_tx(void) {
|
||||
si4060_change_state(STATE_SLEEP);
|
||||
}
|
||||
|
||||
/*
|
||||
* si4060_setup
|
||||
*
|
||||
* initializes the Si4060 by setting all neccesary internal registers.
|
||||
* has to be called after si4060_power_up.
|
||||
*
|
||||
* mod_type:the type of modulation to use, use the MODEM_MOD_TYPE values (MOD_TYPE_*)
|
||||
*/
|
||||
void si4060_setup(uint8_t mod_type) {
|
||||
|
||||
/* set high performance mode */
|
||||
si4060_set_property_8(PROP_GLOBAL,
|
||||
GLOBAL_CONFIG,
|
||||
GLOBAL_RESERVED | POWER_MODE_HIGH_PERF | SEQUENCER_MODE_FAST);
|
||||
/* set up GPIOs */
|
||||
si4060_gpio_pin_cfg(GPIO_MODE_INPUT,
|
||||
PULL_CTL + GPIO_MODE_INPUT,
|
||||
GPIO_MODE_DONOTHING,
|
||||
PULL_CTL + GPIO_MODE_INPUT,
|
||||
DRV_STRENGTH_HIGH);
|
||||
/* disable preamble */
|
||||
si4060_set_property_8(PROP_PREAMBLE,
|
||||
PREAMBLE_TX_LENGTH,
|
||||
0);
|
||||
/* do not transmit sync word */
|
||||
si4060_set_property_8(PROP_SYNC,
|
||||
SYNC_CONFIG,
|
||||
SYNC_NO_XMIT);
|
||||
/* use 2FSK from async GPIO0 */
|
||||
si4060_set_property_8(PROP_MODEM,
|
||||
MODEM_MOD_TYPE,
|
||||
(mod_type & 0x07) | MOD_SOURCE_DIRECT | MOD_GPIO_1 | MOD_DIRECT_MODE_ASYNC);
|
||||
/* setup frequency deviation */
|
||||
si4060_set_property_24(PROP_MODEM,
|
||||
MODEM_FREQ_DEV,
|
||||
(uint32_t)FDEV);
|
||||
/* setup frequency deviation offset */
|
||||
si4060_set_property_16(PROP_MODEM,
|
||||
MODEM_FREQ_OFFSET,
|
||||
0x0000);
|
||||
/* setup divider to 8 (for 70cm ISM band */
|
||||
si4060_set_property_8(PROP_MODEM,
|
||||
MODEM_CLKGEN_BAND,
|
||||
SY_SEL_1 | FVCO_DIV_8);
|
||||
/* set up the PA power level */
|
||||
si4060_set_property_8(PROP_PA,
|
||||
PA_PWR_LVL,
|
||||
0x3f);
|
||||
/* set up the PA duty cycle */
|
||||
si4060_set_property_8(PROP_PA,
|
||||
PA_BIAS_CLKDUTY,
|
||||
PA_BIAS_CLKDUTY_DIFF_50);
|
||||
/* set up the integer divider */
|
||||
si4060_set_property_8(PROP_FREQ_CONTROL,
|
||||
FREQ_CONTROL_INTE,
|
||||
(uint8_t)(FDIV_INTE));
|
||||
/* set up the fractional divider */
|
||||
si4060_set_property_24(PROP_FREQ_CONTROL,
|
||||
FREQ_CONTROL_FRAC,
|
||||
(uint32_t)(FDIV_FRAC));
|
||||
/* TODO set the channel step size (if SPI frequency changing is used) */
|
||||
|
||||
}
|
||||
Ładowanie…
Reference in New Issue