Typo
rodzic
4a6ac015d2
commit
532a6b00e0
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@ -9,10 +9,10 @@ from machine import mem32
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SIO_BASE = 0xD0000000
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# INTERP0 registers
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INTERP0_ACCUM0 = 0xD0000000 + 0x80
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INTERP0_BASE0 = 0xD0000000 + 0x88
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INTERP0_POP_LANE0 = 0xD0000000 + 0x94
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INTERP0_CTRL_LANE0 = 0xD0000000 + 0xAC
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INTERP0_ACCUM0 = SIO_BASE + 0x80
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INTERP0_BASE0 = SIO_BASE + 0x88
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INTERP0_POP_LANE0 = SIO_BASE + 0x94
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INTERP0_CTRL_LANE0 = SIO_BASE + 0xAC
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# initialise lane 0 on interp: set that we are using all 32 bits
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mem32[INTERP0_CTRL_LANE0] = 0x1F << 10
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