kopia lustrzana https://github.com/raspberrypi/pico-extras
Add Support for Composite SYNC
Gavin Andrews
rodzic
747ce32a8e
commit
2d0cf7e070
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@ -123,6 +123,12 @@ extern "C" {
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// most likely 24000000
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extern const uint32_t video_clock_freq;
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// Apply CSYNC flag to HSYNC polarity
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// - Extend : Extends HSYNC during VSYNC pulse period
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// - Suppress : HSYNC inhibit during VSYNC period
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#define CSYNC_EXTEND 2
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#define CSYNC_SUPPRESS 4
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// todo pragma pack?
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typedef struct scanvideo_timing {
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uint32_t clock_freq;
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@ -63,6 +63,12 @@ extern "C" {
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// most likely 24000000
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extern const uint32_t vga_clock_freq;
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// Apply CSYNC flag to HSYNC polarity
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// - Extend : Extends HSYNC during VSYNC pulse period
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// - Suppress : HSYNC inhibit during VSYNC period
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#define CSYNC_EXTEND 2
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#define CSYNC_SUPPRESS 4
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// todo pragma pack?
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struct video_timing
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{
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@ -198,18 +198,21 @@ static struct {
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int32_t v_total;
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int32_t v_pulse_start;
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int32_t v_pulse_end;
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// todo replace with plain polarity
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uint32_t vsync_bits_pulse;
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uint32_t vsync_bits_no_pulse;
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uint32_t a, a_vblank, b1, b2, c, c_vblank;
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uint32_t vsync_bits;
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uint16_t dma_state_index;
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uint16_t dma_state_mode;
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int32_t timing_scanline;
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} timing_state;
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#define DMA_STATE_COUNT 4
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static uint32_t dma_states[DMA_STATE_COUNT];
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#define DMA_STATE_MODE_COUNT 3
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#define DMA_STATE_MODE_V_ACTIVE 0
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#define DMA_STATE_MODE_V_BLANK 1
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#define DMA_STATE_MODE_V_BLANK_PULSE 2
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#define DMA_STATE_COUNT 5
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static uint32_t dma_states[DMA_STATE_MODE_COUNT][DMA_STATE_COUNT];
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// todo get rid of this altogether
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#undef PICO_SCANVIDEO_ENABLE_VIDEO_CLOCK_DOWN
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@ -903,16 +906,13 @@ static void __video_time_critical_func(prepare_for_vblank_scanline_irqs_enabled)
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}
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}
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#define setup_dma_states_vblank() if (true) { dma_states[0] = timing_state.a_vblank; dma_states[1] = timing_state.b1; dma_states[2] = timing_state.b2; dma_states[3] = timing_state.c_vblank; } else __builtin_unreachable()
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#define setup_dma_states_no_vblank() if (true) { dma_states[0] = timing_state.a; dma_states[1] = timing_state.b1; dma_states[2] = timing_state.b2; dma_states[3] = timing_state.c; } else __builtin_unreachable()
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static inline void top_up_timing_pio_fifo() {
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// todo better irq reset ... we are seeing irq get set again, handled in this loop, then we re-enter here when we don't need to
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// keep filling until SM3 TX is full
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while (!(video_pio->fstat & (1u << (PICO_SCANVIDEO_TIMING_SM + PIO_FSTAT_TXFULL_LSB)))) {
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DEBUG_PINS_XOR(video_irq, 1);
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DEBUG_PINS_XOR(video_irq, 1);
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pio_sm_put(video_pio, PICO_SCANVIDEO_TIMING_SM, dma_states[timing_state.dma_state_index] | timing_state.vsync_bits);
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pio_sm_put(video_pio, PICO_SCANVIDEO_TIMING_SM, dma_states[timing_state.dma_state_mode][timing_state.dma_state_index]);
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// todo simplify this now we have a1, a2, b, c
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// todo display enable (only goes positive on start of screen)
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@ -926,14 +926,14 @@ static inline void top_up_timing_pio_fifo() {
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if (timing_state.timing_scanline >= timing_state.v_total) {
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timing_state.timing_scanline = 0;
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// active display - gives irq 0 and irq 4
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setup_dma_states_no_vblank();
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timing_state.dma_state_mode = DMA_STATE_MODE_V_ACTIVE; // In V Active Region
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} else if (timing_state.timing_scanline <= timing_state.v_pulse_end) {
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if (timing_state.timing_scanline == timing_state.v_active) {
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setup_dma_states_vblank();
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timing_state.dma_state_mode = DMA_STATE_MODE_V_BLANK; // In V Front Porch
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} else if (timing_state.timing_scanline == timing_state.v_pulse_start) {
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timing_state.vsync_bits = timing_state.vsync_bits_pulse;
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timing_state.dma_state_mode = DMA_STATE_MODE_V_BLANK_PULSE; // In V Pulse
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} else if (timing_state.timing_scanline == timing_state.v_pulse_end) {
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timing_state.vsync_bits = timing_state.vsync_bits_no_pulse;
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timing_state.dma_state_mode = DMA_STATE_MODE_V_BLANK; // In V Back Porch
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}
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}
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}
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@ -1576,9 +1576,6 @@ bool scanvideo_setup_with_timing(const scanvideo_mode_t *mode, const scanvideo_t
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timing_state.v_active = timing->v_active;
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timing_state.v_pulse_start = timing->v_active + timing->v_front_porch;
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timing_state.v_pulse_end = timing_state.v_pulse_start + timing->v_pulse;
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const uint32_t vsync_bit = 0x40000000;
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timing_state.vsync_bits_pulse = timing->v_sync_polarity ? 0 : vsync_bit;
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timing_state.vsync_bits_no_pulse = timing->v_sync_polarity ? vsync_bit : 0;
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// these are read bitwise backwards (lsb to msb) by PIO pogram
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@ -1594,14 +1591,13 @@ bool scanvideo_setup_with_timing(const scanvideo_mode_t *mode, const scanvideo_t
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#define C_CMD SET_IRQ_SCANLINE
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#define C_CMD_VBLANK CLEAR_IRQ_SCANLINE
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int h_sync_bit = timing->h_sync_polarity ? 0 : 1;
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timing_state.a = timing_encode(A_CMD, 4, h_sync_bit);
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const uint32_t hsync_bit = 0x00000001; // HSYNC Pin 0
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int hsync_bit_pulse = (timing->h_sync_polarity & 1) ? 0 : hsync_bit;
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int hsync_bit_no_pulse = (timing->h_sync_polarity & 1) ? hsync_bit : 0;
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static_assert(HTIMING_MIN >= 4, "");
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timing_state.a_vblank = timing_encode(A_CMD_VBLANK, 4, h_sync_bit);
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int h_back_porch = timing->h_total - timing->h_front_porch - timing->h_pulse - timing->h_active;
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valid_params_if(SCANVIDEO_DPI, timing->h_pulse - 4 >= HTIMING_MIN);
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timing_state.b1 = timing_encode(B1_CMD, timing->h_pulse - 4, h_sync_bit);
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// todo decide on what these should be - we should really be asserting the timings
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//
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@ -1611,15 +1607,70 @@ bool scanvideo_setup_with_timing(const scanvideo_mode_t *mode, const scanvideo_t
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// (separate from the needs of setting the hsync pulse)
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valid_params_if(SCANVIDEO_DPI, timing->h_active >= HTIMING_MIN);
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//assert(timing->h_front_porch >= HTIMING_MIN);
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int h_back_porch = timing->h_total - timing->h_front_porch - timing->h_pulse - timing->h_active;
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valid_params_if(SCANVIDEO_DPI, h_back_porch >= HTIMING_MIN);
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valid_params_if(SCANVIDEO_DPI, (timing->h_total - h_back_porch - timing->h_pulse) >= HTIMING_MIN);
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timing_state.b2 = timing_encode(B2_CMD, h_back_porch, !h_sync_bit);
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timing_state.c = timing_encode(C_CMD, timing->h_total - h_back_porch - timing->h_pulse, 4 | !h_sync_bit);
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timing_state.c_vblank = timing_encode(C_CMD_VBLANK, timing->h_total - h_back_porch - timing->h_pulse, !h_sync_bit);
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const uint32_t vsync_bit = 0x00000002; // VSYNC Pin 1
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uint32_t vsync_bit_pulse = timing->v_sync_polarity ? 0 : vsync_bit;
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uint32_t vsync_bit_no_pulse = timing->v_sync_polarity ? vsync_bit : 0;
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const uint32_t display_on_bit = 0x00000004; // Display On?
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// setup_dma_states_no_vblank()
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dma_states[DMA_STATE_MODE_V_ACTIVE][0]
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= timing_encode(A_CMD, 4, hsync_bit_pulse | vsync_bit_no_pulse);
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dma_states[DMA_STATE_MODE_V_ACTIVE][1]
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= timing_encode(B1_CMD, timing->h_pulse - 4, hsync_bit_pulse | vsync_bit_no_pulse);
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dma_states[DMA_STATE_MODE_V_ACTIVE][2]
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= timing_encode(B2_CMD, h_back_porch, hsync_bit_no_pulse | vsync_bit_no_pulse);
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dma_states[DMA_STATE_MODE_V_ACTIVE][3]
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= timing_encode(C_CMD, timing->h_total - h_back_porch - timing->h_pulse, display_on_bit | hsync_bit_no_pulse | vsync_bit_no_pulse);
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// setup_dma_states_vblank
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dma_states[DMA_STATE_MODE_V_BLANK][0]
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= timing_encode(A_CMD_VBLANK, 4, hsync_bit_pulse | vsync_bit_no_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK][1]
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= timing_encode(B1_CMD, timing->h_pulse - 4, hsync_bit_pulse | vsync_bit_no_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK][2]
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= timing_encode(B2_CMD, h_back_porch, hsync_bit_no_pulse | vsync_bit_no_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK][3]
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= timing_encode(C_CMD_VBLANK, timing->h_total - h_back_porch - timing->h_pulse, hsync_bit_no_pulse | vsync_bit_no_pulse);
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// setup_dma_states_vblank() with pulse
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if (timing->h_sync_polarity & CSYNC_EXTEND != 0) { // Widen HSYNC during VSYNC
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// CSYNC : Extend HSYNC during VSYNC period, 4 then h_back_porch-4, then off for h_pulse
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][0] = timing_encode(A_CMD_VBLANK, 4, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][1] = timing_encode(B1_CMD, h_back_porch-4, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][2] = timing_encode(B2_CMD, timing->h_pulse, hsync_bit_no_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][3]
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= timing_encode(C_CMD_VBLANK, timing->h_total - h_back_porch - timing->h_pulse, hsync_bit_no_pulse | vsync_bit_pulse);
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} else if (timing->h_sync_polarity & CSYNC_SUPPRESS != 0)
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{
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// CSYNC : HSYNC pulse overriden by VSYNC pulse
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][0] = timing_encode(A_CMD_VBLANK, 4, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][1] = timing_encode(B1_CMD, timing->h_pulse - 4, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][2] = timing_encode(B2_CMD, h_back_porch, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][3]
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= timing_encode(C_CMD_VBLANK, timing->h_total - h_back_porch - timing->h_pulse, hsync_bit_pulse | vsync_bit_pulse);
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} else
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{
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// Seperate SYNC : HSYNC pulse for 4 then hsync_bit_pulse-4
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][0] = timing_encode(A_CMD_VBLANK, 4, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][1] = timing_encode(B1_CMD, timing->h_pulse - 4, hsync_bit_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][2] = timing_encode(B2_CMD, h_back_porch, hsync_bit_no_pulse | vsync_bit_pulse);
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dma_states[DMA_STATE_MODE_V_BLANK_PULSE][3]
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= timing_encode(C_CMD_VBLANK, timing->h_total - h_back_porch - timing->h_pulse, hsync_bit_no_pulse | vsync_bit_pulse);
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}
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// this is two scanlines in vblank
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setup_dma_states_vblank();
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timing_state.vsync_bits = timing_state.vsync_bits_no_pulse;
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timing_state.dma_state_index = 0;
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timing_state.dma_state_mode = DMA_STATE_MODE_V_BLANK;
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// Build the DMA States
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scanvideo_set_scanline_repeat_fn(NULL);
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return true;
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}
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