From fe68f49820f3a9837286ff4825874ae5d12ec55b Mon Sep 17 00:00:00 2001 From: Sven Steudte Date: Thu, 31 Aug 2017 03:55:28 +0200 Subject: [PATCH] Removed backup files --- tracker/software/drivers/ov2640-ss.c | 1090 --------------- .../software/drivers/ov2640_lptim_working.c | 1146 --------------- tracker/software/drivers/ov2640_old.c | 958 ------------- tracker/software/drivers/ov2640_old2.c | 1046 -------------- tracker/software/drivers/ov2640_old3.c | 1090 --------------- tracker/software/drivers/ov2640_old4.c | 1131 --------------- tracker/software/drivers/ov2640_old5.c | 1069 -------------- .../drivers/ov5640_working_patch_tim8.c | 1234 ----------------- 8 files changed, 8764 deletions(-) delete mode 100644 tracker/software/drivers/ov2640-ss.c delete mode 100644 tracker/software/drivers/ov2640_lptim_working.c delete mode 100644 tracker/software/drivers/ov2640_old.c delete mode 100644 tracker/software/drivers/ov2640_old2.c delete mode 100644 tracker/software/drivers/ov2640_old3.c delete mode 100644 tracker/software/drivers/ov2640_old4.c delete mode 100644 tracker/software/drivers/ov2640_old5.c delete mode 100644 tracker/software/drivers/ov5640_working_patch_tim8.c diff --git a/tracker/software/drivers/ov2640-ss.c b/tracker/software/drivers/ov2640-ss.c deleted file mode 100644 index 75221e3..0000000 --- a/tracker/software/drivers/ov2640-ss.c +++ /dev/null @@ -1,1090 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(1) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN | COM8_BNDF_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - dmaStreamEnable(dmastp); - return 0; -} - - -inline int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - return 0; -} - - -inline int32_t dma_release(void) { - dmaStreamRelease(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Nothing really to do at half way point. */ - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* End of transfer. */ - palSetLine(LINE_IO_LED1); - /* Stop DMA initiation from TIM1 trigger input. */ - TIM1->DIER &= ~TIM_DIER_TDE; - /* - * Stop DMA for this HREF. - * We enable it again with existing settings for (if) next HREF. - * Else on VSYNC trailing edge frame capture terminates. - */ - dma_stop(); - } -} - -/* - * The TIM1 interrupt handler. - */ - - /* Not defined by Chibios. */ -#define STM32_TIM1_TRG_HANDLER VectorA8 -#define STM32_TIM1_UP_NUMBER 25 - -OSAL_IRQ_HANDLER(STM32_TIM1_TRG_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - TIM1->SR &= ~TIM_SR_TIF; - - OSAL_IRQ_EPILOGUE(); - -} - -static bool LptimRdy; -static bool image_finished; - -/* - * The LPTIM interrupt handler. - */ -OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { - - /* Note: - * STM32F4 vectors defined by Chibios currently stop at 98. - * Need to allocate more space in vector table for LPTIM1. - * LPTIM1 is vector 97. Vector table is expanded in increments of 8. - * Change CORTEX_NUM_PARAMS in cmparams.h to 106. - */ - OSAL_IRQ_PROLOGUE(); - /* Reset interrupt flag for ARR. */ - LPTIM1->ICR = LPTIM_ICR_ARRMCF; - /* - * LPTIM interrupts can be disabled at this stage. - * We don't need this interrupt again until a new capture is started. - */ - LPTIM1->IER &= ~LPTIM_IER_ARRMIE; - - palToggleLine(LINE_IO_LED1); - - /* - * The first interrupt indicates LPTIM core has been initialized by PCLK. - * This flag is used to synchronise capture start. - * If on leading edge of VSYNC lptim_rdy is true then capture can start. - * If not wait for the next VSYNC. - * This is needed because of LPTIM core setup requirement when clocked externally. - */ - LptimRdy = true; - - OSAL_IRQ_EPILOGUE(); - -} - -// This is the vector for HREF (EXTI2) (stolen from hal_ext_lld_isr.c) -CH_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - if (LptimRdy) { - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - /* - * Start or re-start dma. The transfer count already set will be used. - * The M0AR (DMA memory address) register is set for autoincrement. - * It will be pointing to the next buffer address when DMA is re-started. - */ - dma_start(); - /* Set TIM1 trigger to initate DMA. */ - TIM1->DIER |= TIM_DIER_TDE; - } - } - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -/* - * Note: VSYNC is a pulse the full length of a frame. - * This is contrary to the OV2640 datasheet which shows VSYNC as pulses. -*/ -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - if (LptimRdy) { - // VSYNC handling - if(gpioc & 0x2) { - // VSYNC rising edge - // Start capturing image even if HREF is still low. We do this - // because the timers need some clocks to initialize. Therefore - // we will capture some bytes additionally in the beginning which - // we will remove later - //dma_start(); - // TIM1->DIER |= TIM_DIER_TDE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - } else { - // VSYNC falling edge - end if JPEG frame. Stop the DMA, disable - // capture LED and signal the semaphore (data can be processed). - TIM1->DIER &= ~TIM_DIER_TDE; - dma_stop(); - /* Capture complete so release the stream. */ - dma_release(); - if(ov2640_conf->ram_buffer[0] == 0xFF) // Picture correctly sampled FIXME: That should actually not be neccessary (workaround) - { - nvicDisableVector(EXTI1_IRQn); // Disable interrupt - nvicDisableVector(EXTI2_IRQn); // Disable interrupt - - palSetLine(LINE_IO_LED1); // Indicate that picture is captured completly - image_finished = true; - } - } - } else { - /* - * LPTIM1 is not yet started. - * So we enable LPTIM1 to start counting. - * The PCLK should be low at the leading edge of VSYNC. - * Thus we get a clean start of LPTIM1 clocking on next leading edge of PCLK. - * After the LPTIM core is initialised PCLK and LPTIM_OUT >should< be synchronous. - * This needs to be verified as the ST RM document is not precise on this matter. - */ - LPTIM1->CR |= LPTIM_CR_CNTSTRT; - } - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - -void OV2640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(6) | - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_HTIE; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - - // Setup timer for PCLCK - rccResetLPTIM1(); - rccEnableLPTIM1(FALSE); - - /* - * The setting of CKSEL & COUNTMODE are not completely clear. - * The change below switches to using internal clock sampling the external clock. - * - */ - //LPTIM1->CFGR = (LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL_1); - LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1); - LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; - LPTIM1->CR |= LPTIM_CR_ENABLE; - LPTIM1->IER |= LPTIM_IER_ARRMIE; - - LPTIM1->CMP = 1; - LPTIM1->ARR = 2; - - /* Set vector, clear flag and start the counter. */ - nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt - LptimRdy = false; - - /* - * Setup slave timer to trigger DMA. - * We have to use TIM1 because... - * > it can be triggered from LPTIM1 - * > and TIM1_TRIG is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccResetTIM1(); - rccEnableTIM1(FALSE); - - TIM1->SMCR = TIM_SMCR_TS_1; // Select ITR2 as trigger - TIM1->SMCR |= TIM_SMCR_SMS_2; // Set timer in reset mode - /* - * IC1 is mapped to TRC which means we are in Input mode. - * The timer will reset and trigger DMA on the leading edge of LPTIM1_OUT. - * The counter will count up while LPTIM1_OUT is high. - * We don't care what the count is. - * We just use the DMA from the trigger which is independant of counting. - */ - TIM1->CCMR1 |= (TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC1S_1); - //TIM1->DIER |= TIM_DIER_TDE; // Enable DMA on trigger in. (=> Is done in VSYNC and HREF interrupts) - //TIM1->DIER |= TIM_DIER_TIE; // Enable interrupt on trigger request - - //TIM1->CR1 |= TIM_CR1_CEN; // Enable the timer - - nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, 7); // Enable interrupt - - //TIM1->CR1 |= TIM_CR1_CEN; /* Enable the timer. */ - - image_finished = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 | EXTI_IMR_MR2; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 | EXTI_RTSR_TR2; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 | EXTI_FTSR_TR2; // Listen on falling edge too - - nvicEnableVector(EXTI1_IRQn, 2); // Enable interrupt - nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - chThdSleepMilliseconds(100); - } while(!image_finished); - TRACE_DEBUG("CAM > Image %02x %02x %02x %02x", ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - TRACE_INFO("CAM > Capture finished"); -} - - - -/** - * Initializes GPIO (for DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(1)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov2640_lptim_working.c b/tracker/software/drivers/ov2640_lptim_working.c deleted file mode 100644 index 1eb2d32..0000000 --- a/tracker/software/drivers/ov2640_lptim_working.c +++ /dev/null @@ -1,1146 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSYNC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(8) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN | COM8_BNDF_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - //{ COM10, COM10_PCLK_RISE }, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - for(uint32_t i=0; i<320; i++) - TRACE_DEBUG("%02x %02x %02x %02x %02x %02x %02x %02x", -ov2640_conf->ram_buffer[i*8+0], -ov2640_conf->ram_buffer[i*8+1], -ov2640_conf->ram_buffer[i*8+2], -ov2640_conf->ram_buffer[i*8+3], -ov2640_conf->ram_buffer[i*8+4], -ov2640_conf->ram_buffer[i*8+5], -ov2640_conf->ram_buffer[i*8+6], -ov2640_conf->ram_buffer[i*8+7]); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - /* Clear any pending inerrupts. */ - dmaStreamClearInterrupt(dmastp); - dmaStreamEnable(dmastp); - return 0; -} - -inline int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - dmaStreamRelease(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Deprecate - Nothing really to do at half way point. */ - return; - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* End of transfer. */ - palSetLine(LINE_IO_LED1); - - /* - * Stop PCLK from LPTIM1 and disable TIM1 DMA trigger. - * Stop and release DMA channel. - * Either DMA count full or VSNC traling edge can terminate frame capture - */ - TIM1->DIER &= ~TIM_DIER_TDE; - LPTIM1->CR &= ~LPTIM_CR_CNTSTRT; - dma_stop(); - return; - } - /* - * TODO: Anything else is an error. - * Maybe set an error flag? - */ -} - -/* - * The TIM1 interrupt handler (to be deprecated - not used). - */ - - /* Not defined by Chibios. */ -#define STM32_TIM1_TRG_HANDLER VectorA8 -#define STM32_TIM1_UP_NUMBER 25 - -OSAL_IRQ_HANDLER(STM32_TIM1_TRG_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - TIM1->SR &= ~TIM_SR_TIF; - - OSAL_IRQ_EPILOGUE(); - -} - -static bool LptimRdy; -static bool image_finished; - -/* - * The LPTIM interrupt handler. - */ -OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { - - /* Note: - * STM32F4 vectors defined by Chibios currently stop at 98. - * Need to allocate more space in vector table for LPTIM1. - * LPTIM1 is vector 97. Vector table is expanded in increments of 8. - * Change CORTEX_NUM_PARAMS in cmparams.h to 106. - */ - OSAL_IRQ_PROLOGUE(); - /* Reset interrupt flag for ARR. */ - LPTIM1->ICR = LPTIM_ICR_ARRMCF; - /* - * LPTIM interrupts can be disabled at this stage. - * We don't need this interrupt again until a new capture is started. - */ - LPTIM1->IER &= ~LPTIM_IER_ARRMIE; - - palToggleLine(LINE_IO_LED1); - - /* - * The first interrupt indicates LPTIM core has been initialized by PCLK. - * This flag is used to synchronise capture start. - * If on leading edge of VSYNC lptim_rdy is true then capture can start. - * If not wait for the next VSYNC. - * This is needed because of LPTIM core setup requirement when clocked externally. - */ - LptimRdy = true; - - OSAL_IRQ_EPILOGUE(); - -} - -// This is the vector for HREF (EXTI2) (stolen from hal_ext_lld_isr.c) -/* To be deprecated - not used. */ -CH_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - if (LptimRdy) { - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - /* - * Start or re-start dma. The transfer count already set will be used. - * The M0AR (DMA memory address) register is set for autoincrement. - * It will be pointing to the next buffer address when DMA is re-started. - */ - //dma_start(); - /* Set TIM1 trigger to initate DMA. */ - TIM1->DIER |= TIM_DIER_TDE; - } else { - /* Set TIM1 trigger to initate DMA. */ - TIM1->DIER &= ~TIM_DIER_TDE; - } - - } - - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -bool vsync = false; - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -/* - * Note: VSYNC is a pulse the full length of a frame. - * This is contrary to the OV2640 datasheet which shows VSYNC as pulses. -*/ -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - if (LptimRdy) { - // VSYNC handling - if(!vsync && palReadLine(LINE_CAM_VSYNC)) { - /* - * Rising edge of VSYNC after LPTIM1 has been initiualized. - * Start DMA channel. - * Enable TIM1 trigger of DMA. - */ - dma_start(); - TIM1->DIER |= TIM_DIER_TDE; - //TIM1->DIER |= TIM_DIER_TDE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - vsync = true; - } else if(vsync) { - /* VSYNC falling edge - end of JPEG frame. - * Stop & release the DMA channel. - * Disable TIM1 trigger of DMA and stop PCLK via LPTIM1 - * These should have already been disabled in DMA interrupt if was filled. - */ - dma_stop(); - TIM1->DIER &= ~TIM_DIER_TDE; - LPTIM1->CR &= ~LPTIM_CR_CNTSTRT; - - /* Disable VYSNC edge interrupts. */ - nvicDisableVector(EXTI1_IRQn); - //nvicDisableVector(EXTI2_IRQn); - /* Turn on capture LED and signal the semaphore (data can be processed). */ - palSetLine(LINE_IO_LED1); - image_finished = true; - vsync = false; - } - } else { - /* - * LPTIM1 is not yet initialised. - * So we enable LPTIM1 to start counting. - * The PCLK should be low at the leading edge of VSYNC. - * Thus we get a clean start of LPTIM1 clocking on next leading edge of PCLK. - * After the LPTIM core is initialised PCLK and LPTIM_OUT >should< be synchronous. - * This needs to be verified as the ST RM document is not precise on this matter. - */ - LPTIM1->CR |= LPTIM_CR_CNTSTRT; - } - - palToggleLine(LINE_IO_LED1); - - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - -bool OV2640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(6) | - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - /*STM32_DMA_CR_CIRC |*/ - STM32_DMA_CR_TCIE /*| - STM32_DMA_CR_HTIE*/; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - - // Setup timer for PCLCK - rccResetLPTIM1(); - rccEnableLPTIM1(FALSE); - - /* - * The setting of CKSEL & COUNTMODE are not completely clear. - * The change below switches to using internal clock sampling the external clock. - * - */ - //LPTIM1->CFGR = (LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL_1); - LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL); - LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; - LPTIM1->CR |= LPTIM_CR_ENABLE; - LPTIM1->IER |= LPTIM_IER_ARRMIE; - - LPTIM1->CMP = 0; - LPTIM1->ARR = 1; - - /* Set vector and clear flag. */ - nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt - LptimRdy = false; - - /* - * Setup slave timer to trigger DMA. - * We have to use TIM1 because... - * > it can be triggered from LPTIM1 - * > and TIM1_TRIG is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccResetTIM1(); - rccEnableTIM1(FALSE); - - TIM1->SMCR = TIM_SMCR_TS_1; // Select ITR2 as trigger - TIM1->SMCR |= TIM_SMCR_SMS_2; // Set timer in reset mode - /* - * IC1 is mapped to TRC which means we are in Input mode. - * The timer will reset and trigger DMA on the leading edge of LPTIM1_OUT. - * The counter will count up while LPTIM1_OUT is high. - * We don't care what the count is. - * We just use the DMA initiated by the trigger which is independant of counting. - */ - TIM1->CCMR1 |= (TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC1S_1); - //TIM1->DIER |= TIM_DIER_TDE; // Enable DMA on trigger in. (=> Is done in VSYNC and HREF interrupts) - //TIM1->DIER |= TIM_DIER_TIE; // Enable interrupt on trigger request - - //TIM1->CR1 |= TIM_CR1_CEN; // Enable the timer - - //nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, 7); // Enable interrupt - - //TIM1->CR1 |= TIM_CR1_CEN; /* Enable the timer. */ - - image_finished = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 | EXTI_IMR_MR2; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 | EXTI_RTSR_TR2; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 | EXTI_FTSR_TR2; // Listen on falling edge too - - nvicEnableVector(EXTI1_IRQn, 2); // Enable interrupt - nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - chThdSleepMilliseconds(100); - } while(!image_finished); - - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - - TRACE_DEBUG("CAM > Have a look for SOI"); - uint32_t soi; // Start of Image - for(soi=0; soi<65533; soi++) - { - if(ov2640_conf->ram_buffer[soi] == 0xFF && ov2640_conf->ram_buffer[soi+1] == 0xD8) - break; - } - - if(soi == 65533) { - TRACE_ERROR("CAM > Could not find SOI flag"); - return false; // We failed to sample the picture correctly because we didn't find the JPEG SOI flag - } - - TRACE_DEBUG("SOI=%d", soi) - - // Found SOI, move bytes - for(uint32_t i=0; i<65535; i++) - ov2640_conf->ram_buffer[i] = ov2640_conf->ram_buffer[i+soi]; - - TRACE_DEBUG("CAM > Image %02x %02x %02x %02x %02x %02x", ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3], ov2640_conf->ram_buffer[4], ov2640_conf->ram_buffer[5]); - TRACE_INFO("CAM > Capture finished"); - - return true; -} - - - -/** - * Initializes GPIO (for DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(1)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov2640_old.c b/tracker/software/drivers/ov2640_old.c deleted file mode 100644 index 01d2fad..0000000 --- a/tracker/software/drivers/ov2640_old.c +++ /dev/null @@ -1,958 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(2) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN | COM8_BNDF_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -const stm32_dma_stream_t *dmastp; - -int32_t dma_start(void) { - dmaStreamEnable(dmastp); - return 0; -} - - -int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { // I think we dont need this - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { // I think that stands for "memory filled completly" - palSetLine(LINE_IO_LED1); - dma_stop(); // Stop DMA - } -} - - - -// This is the vector for EXTI2 (stolen from hal_ext_lld_isr.c) -CH_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - TIM5->DIER |= TIM_DIER_TDE; - } else { - // HREF falling edge, stop capturing - TIM5->DIER &= ~TIM_DIER_TDE; - } - - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - - // VSYNC handling - if(gpioc & 0x2) { - // VSYNC rising edge - // Start capturing image even if HREF is still low. We do this - // because the timers need some clocks to initialize. Therefore - // we will capture some bytes additionally in the beginning which - // we will remove later - dma_start(); - TIM5->DIER |= TIM_DIER_TDE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - } else { - // VSYNC falling edge - end if JPEG frame. Stop the DMA, disable - // capture LED and signal the semaphore (data can be processed). - TIM5->DIER &= ~TIM_DIER_TDE; - dma_stop(); - palSetLine(LINE_IO_LED1); // Indicate that picture is captured completly - } - - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - - -void OV2640_Capture(void) -{ - // Setup DMA - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(1, 2)); // TIM5_CH1 DMA1 Stream 2 - uint32_t dmamode = STM32_DMA_CR_CHSEL(6) | // Channel 6 - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_HTIE; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - - // Setup timer for PLCK - rccResetLPTIM1(); - rccEnableLPTIM1(FALSE); - - LPTIM1->CFGR = (LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL_1); - LPTIM1->OR |= LPTIM_OR_TIM5_ITR1_RMP; - - rccResetTIM5(); - rccEnableTIM5(FALSE); - - - TIM5->SMCR = TIM_SMCR_TS_0; // Select ITR1 as trigger - TIM5->SMCR |= TIM_SMCR_SMS_2; // Set timer in reset mode - TIM5->CCMR1 |= (TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC1S_1); // IC1 is mapped to TRC - //TIM5->DIER |= TIM_DIER_TDE; // Enable DMA on trigger request. - //TIM5->DIER |= TIM_DIER_TIE; // Enable interrupt on trigger request - - TIM5->CR1 |= TIM_CR1_CEN; // Enable the timer - //nvicEnableVector(TIM5_IRQn, 7); // Enable interrupt - - LPTIM1->CR |= LPTIM_CR_ENABLE; - - LPTIM1->CMP = 1; - LPTIM1->ARR = 2; - - LPTIM1->CR |= LPTIM_CR_CNTSTRT; - - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 | EXTI_IMR_MR2; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 | EXTI_RTSR_TR2; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 | EXTI_FTSR_TR2; // Listen on falling edge too - nvicEnableVector(EXTI1_IRQn, 1); // Enable interrupt - nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - while(true) { // Have a look for some bytes in memory for testing if capturing works - TRACE_DEBUG("CAM > BLA %d %d %d %d %d", TIM5->CNT, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1] -, ov2640_conf->ram_buffer[1024], ov2640_conf->ram_buffer[2048]); - chThdSleepMilliseconds(1); - } - TRACE_INFO("CAM > Stop capture"); -} - -/** - * Initializes GPIO (for DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(1)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov2640_old2.c b/tracker/software/drivers/ov2640_old2.c deleted file mode 100644 index a8bb747..0000000 --- a/tracker/software/drivers/ov2640_old2.c +++ /dev/null @@ -1,1046 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(1) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN | COM8_BNDF_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - dmaStreamEnable(dmastp); - return 0; -} - - -inline int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Nothing really to do at half way point. */ - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - palSetLine(LINE_IO_LED1); - dma_stop(); // Stop DMA - } -} - -/* - * The TIM1 interrupt handler. - */ - - /* Not defined buy Chibios. */ -#define STM32_TIM1_TRG_HANDLER VectorA8 -#define STM32_TIM1_UP_NUMBER 25 - -OSAL_IRQ_HANDLER(STM32_TIM1_TRG_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - TIM1->SR &= ~TIM_SR_TIF; - - OSAL_IRQ_EPILOGUE(); - -} - -static bool lptim_rdy; -static bool image_finished; - -/* - * The LPTIM interrupt handler. - */ -OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { - - /* Note: - * STM32F4 vectors defined by Chibios currently stop at 98. - * Need to allocate more space in vector table for LPTIM1. - * LPTIM1 is vector 97. Vector table is expanded in increments of 8. - * Change CORTEX_NUM_PARAMS in cmparams.h to 106. - */ - OSAL_IRQ_PROLOGUE(); - /* Reset interrupt flags. */ - LPTIM1->ICR = LPTIM1->ISR; - - palToggleLine(LINE_IO_LED1); - - /* - * The first interrupt indicates LPTIM core has been initialized by PIXCLK. - * This flag can be used to synchronise capture start. - * If on trailing edge of VSYNC lptim_rdy is set then capture can start. - * If not wait for the next VSYNC. - */ - lptim_rdy = true; - OSAL_IRQ_EPILOGUE(); - -} - -// This is the vector for EXTI2 (stolen from hal_ext_lld_isr.c) -CH_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - TIM1->DIER |= TIM_DIER_TDE; - } else { - // HREF falling edge, stop capturing - TIM1->DIER &= ~TIM_DIER_TDE; - } - - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -/* - * Note: VSYNC is a pulse sigfnifying start of frame. - * So the following code should start capture on falling edge. - * Then stop capture should be handled by the DMA end interrupt. -*/ -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - - // VSYNC handling - if(gpioc & 0x2) { - // VSYNC rising edge - // Start capturing image even if HREF is still low. We do this - // because the timers need some clocks to initialize. Therefore - // we will capture some bytes additionally in the beginning which - // we will remove later - dma_start(); -// TIM1->DIER |= TIM_DIER_TDE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - } else { - // VSYNC falling edge - end if JPEG frame. Stop the DMA, disable - // capture LED and signal the semaphore (data can be processed). - TIM1->DIER &= ~TIM_DIER_TDE; - dma_stop(); - - if(ov2640_conf->ram_buffer[0] == 0xFF) // Picture correctly sampled FIXME: That should actually not be neccessary (workaround) - { - nvicDisableVector(EXTI1_IRQn); // Disable interrupt - nvicDisableVector(EXTI2_IRQn); // Disable interrupt - - palSetLine(LINE_IO_LED1); // Indicate that picture is captured completly - image_finished = true; - } - } - - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - - -void OV2640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(6) | - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_HTIE; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - - // Setup timer for PCLCK - rccResetLPTIM1(); - rccEnableLPTIM1(FALSE); - - LPTIM1->CFGR = (LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL_1); - LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; - LPTIM1->CR |= LPTIM_CR_ENABLE; - //LPTIM1->IER |= LPTIM_IER_ARRMIE; - - LPTIM1->CMP = 1; - LPTIM1->ARR = 2; - - /* Start start the counter. */ - LPTIM1->CR |= LPTIM_CR_CNTSTRT; - - nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt - - /* - * Setup slave timer to trigger DMA. - * We have to use TIM1 because... - * > it can be triggered from LPTIM1 - * > and TIM1_TRIG is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccResetTIM1(); - rccEnableTIM1(FALSE); - - TIM1->SMCR = TIM_SMCR_TS_1; // Select ITR2 as trigger - TIM1->SMCR |= TIM_SMCR_SMS_2; // Set timer in reset mode - /* - * IC1 is mapped to TRC. - * The timer will reset and trigger DMA on the leading edge of LPTIM1_OUT. - * The counter will count up while LPTIM1_OUT is high. - * We don't care what the count is. - * We just need the DMA from the trigger. - */ - TIM1->CCMR1 |= (TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC1S_1); - //TIM1->DIER |= TIM_DIER_TDE; // Enable DMA on trigger in. (=> Is done in VSYNC and HREF interrupts) - //TIM1->DIER |= TIM_DIER_TIE; // Enable interrupt on trigger request - - TIM1->CR1 |= TIM_CR1_CEN; // Enable the timer - - nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, 7); // Enable interrupt - - TIM1->CR1 |= TIM_CR1_CEN; /* Enable the timer. */ - - image_finished = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 | EXTI_IMR_MR2; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 | EXTI_RTSR_TR2; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 | EXTI_FTSR_TR2; // Listen on falling edge too - - nvicEnableVector(EXTI1_IRQn, 2); // Enable interrupt - nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", TIM1->CNT, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - chThdSleepMilliseconds(100); - } while(!image_finished); - TRACE_DEBUG("CAM > Image %02x %02x %02x %02x", ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - TRACE_INFO("CAM > Capture finished"); -} - -/** - * Initializes GPIO (for DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(1)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov2640_old3.c b/tracker/software/drivers/ov2640_old3.c deleted file mode 100644 index 75221e3..0000000 --- a/tracker/software/drivers/ov2640_old3.c +++ /dev/null @@ -1,1090 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(1) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN | COM8_BNDF_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - dmaStreamEnable(dmastp); - return 0; -} - - -inline int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - return 0; -} - - -inline int32_t dma_release(void) { - dmaStreamRelease(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Nothing really to do at half way point. */ - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* End of transfer. */ - palSetLine(LINE_IO_LED1); - /* Stop DMA initiation from TIM1 trigger input. */ - TIM1->DIER &= ~TIM_DIER_TDE; - /* - * Stop DMA for this HREF. - * We enable it again with existing settings for (if) next HREF. - * Else on VSYNC trailing edge frame capture terminates. - */ - dma_stop(); - } -} - -/* - * The TIM1 interrupt handler. - */ - - /* Not defined by Chibios. */ -#define STM32_TIM1_TRG_HANDLER VectorA8 -#define STM32_TIM1_UP_NUMBER 25 - -OSAL_IRQ_HANDLER(STM32_TIM1_TRG_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - TIM1->SR &= ~TIM_SR_TIF; - - OSAL_IRQ_EPILOGUE(); - -} - -static bool LptimRdy; -static bool image_finished; - -/* - * The LPTIM interrupt handler. - */ -OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { - - /* Note: - * STM32F4 vectors defined by Chibios currently stop at 98. - * Need to allocate more space in vector table for LPTIM1. - * LPTIM1 is vector 97. Vector table is expanded in increments of 8. - * Change CORTEX_NUM_PARAMS in cmparams.h to 106. - */ - OSAL_IRQ_PROLOGUE(); - /* Reset interrupt flag for ARR. */ - LPTIM1->ICR = LPTIM_ICR_ARRMCF; - /* - * LPTIM interrupts can be disabled at this stage. - * We don't need this interrupt again until a new capture is started. - */ - LPTIM1->IER &= ~LPTIM_IER_ARRMIE; - - palToggleLine(LINE_IO_LED1); - - /* - * The first interrupt indicates LPTIM core has been initialized by PCLK. - * This flag is used to synchronise capture start. - * If on leading edge of VSYNC lptim_rdy is true then capture can start. - * If not wait for the next VSYNC. - * This is needed because of LPTIM core setup requirement when clocked externally. - */ - LptimRdy = true; - - OSAL_IRQ_EPILOGUE(); - -} - -// This is the vector for HREF (EXTI2) (stolen from hal_ext_lld_isr.c) -CH_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - if (LptimRdy) { - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - /* - * Start or re-start dma. The transfer count already set will be used. - * The M0AR (DMA memory address) register is set for autoincrement. - * It will be pointing to the next buffer address when DMA is re-started. - */ - dma_start(); - /* Set TIM1 trigger to initate DMA. */ - TIM1->DIER |= TIM_DIER_TDE; - } - } - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -/* - * Note: VSYNC is a pulse the full length of a frame. - * This is contrary to the OV2640 datasheet which shows VSYNC as pulses. -*/ -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - if (LptimRdy) { - // VSYNC handling - if(gpioc & 0x2) { - // VSYNC rising edge - // Start capturing image even if HREF is still low. We do this - // because the timers need some clocks to initialize. Therefore - // we will capture some bytes additionally in the beginning which - // we will remove later - //dma_start(); - // TIM1->DIER |= TIM_DIER_TDE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - } else { - // VSYNC falling edge - end if JPEG frame. Stop the DMA, disable - // capture LED and signal the semaphore (data can be processed). - TIM1->DIER &= ~TIM_DIER_TDE; - dma_stop(); - /* Capture complete so release the stream. */ - dma_release(); - if(ov2640_conf->ram_buffer[0] == 0xFF) // Picture correctly sampled FIXME: That should actually not be neccessary (workaround) - { - nvicDisableVector(EXTI1_IRQn); // Disable interrupt - nvicDisableVector(EXTI2_IRQn); // Disable interrupt - - palSetLine(LINE_IO_LED1); // Indicate that picture is captured completly - image_finished = true; - } - } - } else { - /* - * LPTIM1 is not yet started. - * So we enable LPTIM1 to start counting. - * The PCLK should be low at the leading edge of VSYNC. - * Thus we get a clean start of LPTIM1 clocking on next leading edge of PCLK. - * After the LPTIM core is initialised PCLK and LPTIM_OUT >should< be synchronous. - * This needs to be verified as the ST RM document is not precise on this matter. - */ - LPTIM1->CR |= LPTIM_CR_CNTSTRT; - } - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - -void OV2640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(6) | - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_HTIE; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - - // Setup timer for PCLCK - rccResetLPTIM1(); - rccEnableLPTIM1(FALSE); - - /* - * The setting of CKSEL & COUNTMODE are not completely clear. - * The change below switches to using internal clock sampling the external clock. - * - */ - //LPTIM1->CFGR = (LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL_1); - LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1); - LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; - LPTIM1->CR |= LPTIM_CR_ENABLE; - LPTIM1->IER |= LPTIM_IER_ARRMIE; - - LPTIM1->CMP = 1; - LPTIM1->ARR = 2; - - /* Set vector, clear flag and start the counter. */ - nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt - LptimRdy = false; - - /* - * Setup slave timer to trigger DMA. - * We have to use TIM1 because... - * > it can be triggered from LPTIM1 - * > and TIM1_TRIG is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccResetTIM1(); - rccEnableTIM1(FALSE); - - TIM1->SMCR = TIM_SMCR_TS_1; // Select ITR2 as trigger - TIM1->SMCR |= TIM_SMCR_SMS_2; // Set timer in reset mode - /* - * IC1 is mapped to TRC which means we are in Input mode. - * The timer will reset and trigger DMA on the leading edge of LPTIM1_OUT. - * The counter will count up while LPTIM1_OUT is high. - * We don't care what the count is. - * We just use the DMA from the trigger which is independant of counting. - */ - TIM1->CCMR1 |= (TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC1S_1); - //TIM1->DIER |= TIM_DIER_TDE; // Enable DMA on trigger in. (=> Is done in VSYNC and HREF interrupts) - //TIM1->DIER |= TIM_DIER_TIE; // Enable interrupt on trigger request - - //TIM1->CR1 |= TIM_CR1_CEN; // Enable the timer - - nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, 7); // Enable interrupt - - //TIM1->CR1 |= TIM_CR1_CEN; /* Enable the timer. */ - - image_finished = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 | EXTI_IMR_MR2; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 | EXTI_RTSR_TR2; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 | EXTI_FTSR_TR2; // Listen on falling edge too - - nvicEnableVector(EXTI1_IRQn, 2); // Enable interrupt - nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - chThdSleepMilliseconds(100); - } while(!image_finished); - TRACE_DEBUG("CAM > Image %02x %02x %02x %02x", ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - TRACE_INFO("CAM > Capture finished"); -} - - - -/** - * Initializes GPIO (for DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(1)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov2640_old4.c b/tracker/software/drivers/ov2640_old4.c deleted file mode 100644 index 5fe0a31..0000000 --- a/tracker/software/drivers/ov2640_old4.c +++ /dev/null @@ -1,1131 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSYNC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(2) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN | COM8_BNDF_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - /* Clear any pending inerrupts. */ - dmaStreamClearInterrupt(dmastp); - dmaStreamEnable(dmastp); - return 0; -} - -inline int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - dmaStreamRelease(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Deprecate - Nothing really to do at half way point. */ - return; - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* End of transfer. */ - palSetLine(LINE_IO_LED1); - - /* - * Stop PCLK from LPTIM1 and disable TIM1 DMA trigger. - * Stop and release DMA channel. - * Either DMA count full or VSNC traling edge can terminate frame capture - */ - TIM1->DIER &= ~TIM_DIER_TDE; - LPTIM1->CR &= ~LPTIM_CR_CNTSTRT; - dma_stop(); - return; - } - /* - * TODO: Anything else is an error. - * Maybe set an error flag? - */ -} - -/* - * The TIM1 interrupt handler (to be deprecated - not used). - */ - - /* Not defined by Chibios. */ -#define STM32_TIM1_TRG_HANDLER VectorA8 -#define STM32_TIM1_UP_NUMBER 25 - -OSAL_IRQ_HANDLER(STM32_TIM1_TRG_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - TIM1->SR &= ~TIM_SR_TIF; - - OSAL_IRQ_EPILOGUE(); - -} - -static bool LptimRdy; -static bool image_finished; - -/* - * The LPTIM interrupt handler. - */ -OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { - - /* Note: - * STM32F4 vectors defined by Chibios currently stop at 98. - * Need to allocate more space in vector table for LPTIM1. - * LPTIM1 is vector 97. Vector table is expanded in increments of 8. - * Change CORTEX_NUM_PARAMS in cmparams.h to 106. - */ - OSAL_IRQ_PROLOGUE(); - /* Reset interrupt flag for ARR. */ - LPTIM1->ICR = LPTIM_ICR_ARRMCF; - /* - * LPTIM interrupts can be disabled at this stage. - * We don't need this interrupt again until a new capture is started. - */ - LPTIM1->IER &= ~LPTIM_IER_ARRMIE; - - palToggleLine(LINE_IO_LED1); - - /* - * The first interrupt indicates LPTIM core has been initialized by PCLK. - * This flag is used to synchronise capture start. - * If on leading edge of VSYNC lptim_rdy is true then capture can start. - * If not wait for the next VSYNC. - * This is needed because of LPTIM core setup requirement when clocked externally. - */ - LptimRdy = true; - - OSAL_IRQ_EPILOGUE(); - -} - -// This is the vector for HREF (EXTI2) (stolen from hal_ext_lld_isr.c) -/* To be deprecated - not used. */ -CH_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - if (LptimRdy) { - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - /* - * Start or re-start dma. The transfer count already set will be used. - * The M0AR (DMA memory address) register is set for autoincrement. - * It will be pointing to the next buffer address when DMA is re-started. - */ - //dma_start(); - /* Set TIM1 trigger to initate DMA. */ - //TIM1->DIER |= TIM_DIER_TDE; - } - } - - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -bool vsync = false; - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -/* - * Note: VSYNC is a pulse the full length of a frame. - * This is contrary to the OV2640 datasheet which shows VSYNC as pulses. -*/ -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - if (LptimRdy) { - // VSYNC handling - if(!vsync && palReadLine(LINE_CAM_VSYNC)) { - /* - * Rising edge of VSYNC after LPTIM1 has been initiualized. - * Start DMA channel. - * Enable TIM1 trigger of DMA. - */ - dma_start(); - TIM1->DIER |= TIM_DIER_TDE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - vsync = true; - } else if(vsync) { - /* VSYNC falling edge - end of JPEG frame. - * Stop & release the DMA channel. - * Disable TIM1 trigger of DMA and stop PCLK via LPTIM1 - * These should have already been disabled in DMA interrupt if was filled. - */ - dma_stop(); - TIM1->DIER &= ~TIM_DIER_TDE; - LPTIM1->CR &= ~LPTIM_CR_CNTSTRT; - - /* Disable VYSNC edge interrupts. */ - nvicDisableVector(EXTI1_IRQn); - //nvicDisableVector(EXTI2_IRQn); - /* Turn on capture LED and signal the semaphore (data can be processed). */ - palSetLine(LINE_IO_LED1); - image_finished = true; - vsync = false; - } - } else { - /* - * LPTIM1 is not yet initialised. - * So we enable LPTIM1 to start counting. - * The PCLK should be low at the leading edge of VSYNC. - * Thus we get a clean start of LPTIM1 clocking on next leading edge of PCLK. - * After the LPTIM core is initialised PCLK and LPTIM_OUT >should< be synchronous. - * This needs to be verified as the ST RM document is not precise on this matter. - */ - LPTIM1->CR |= LPTIM_CR_CNTSTRT; - } - - palToggleLine(LINE_IO_LED1); - - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - -bool OV2640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(6) | - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - /*STM32_DMA_CR_CIRC |*/ - STM32_DMA_CR_TCIE /*| - STM32_DMA_CR_HTIE*/; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - - // Setup timer for PCLCK - rccResetLPTIM1(); - rccEnableLPTIM1(FALSE); - - /* - * The setting of CKSEL & COUNTMODE are not completely clear. - * The change below switches to using internal clock sampling the external clock. - * - */ - //LPTIM1->CFGR = (LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL_1); - LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1); - LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; - LPTIM1->CR |= LPTIM_CR_ENABLE; - LPTIM1->IER |= LPTIM_IER_ARRMIE; - - LPTIM1->CMP = 0; - LPTIM1->ARR = 1; - - /* Set vector and clear flag. */ - nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt - LptimRdy = false; - - /* - * Setup slave timer to trigger DMA. - * We have to use TIM1 because... - * > it can be triggered from LPTIM1 - * > and TIM1_TRIG is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccResetTIM1(); - rccEnableTIM1(FALSE); - - TIM1->SMCR = TIM_SMCR_TS_1; // Select ITR2 as trigger - TIM1->SMCR |= TIM_SMCR_SMS_2; // Set timer in reset mode - /* - * IC1 is mapped to TRC which means we are in Input mode. - * The timer will reset and trigger DMA on the leading edge of LPTIM1_OUT. - * The counter will count up while LPTIM1_OUT is high. - * We don't care what the count is. - * We just use the DMA initiated by the trigger which is independant of counting. - */ - TIM1->CCMR1 |= (TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC1S_1); - //TIM1->DIER |= TIM_DIER_TDE; // Enable DMA on trigger in. (=> Is done in VSYNC and HREF interrupts) - //TIM1->DIER |= TIM_DIER_TIE; // Enable interrupt on trigger request - - //TIM1->CR1 |= TIM_CR1_CEN; // Enable the timer - - //nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, 7); // Enable interrupt - - //TIM1->CR1 |= TIM_CR1_CEN; /* Enable the timer. */ - - image_finished = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 /*| EXTI_IMR_MR2*/; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 /*| EXTI_RTSR_TR2*/; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 /*| EXTI_FTSR_TR2*/; // Listen on falling edge too - - nvicEnableVector(EXTI1_IRQn, 2); // Enable interrupt - //nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - chThdSleepMilliseconds(100); - } while(!image_finished); - - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - - TRACE_DEBUG("CAM > Have a look for SOI"); - uint32_t soi; // Start of Image - for(soi=0; soi<65533; soi++) - { - if(ov2640_conf->ram_buffer[soi] == 0xFF && ov2640_conf->ram_buffer[soi+1] == 0xD8) - break; - } - - if(soi == 65533) { - TRACE_ERROR("CAM > Could not find SOI flag"); - return false; // We failed to sample the picture correctly because we didn't find the JPEG SOI flag - } - - TRACE_DEBUG("SOI=%d", soi) - - // Found SOI, move bytes - for(uint32_t i=0; i<65535; i++) - ov2640_conf->ram_buffer[i] = ov2640_conf->ram_buffer[i+soi]; - - TRACE_DEBUG("CAM > Image %02x %02x %02x %02x", ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - TRACE_INFO("CAM > Capture finished"); - - return true; -} - - - -/** - * Initializes GPIO (for DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(1)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST); - - palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(1)); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov2640_old5.c b/tracker/software/drivers/ov2640_old5.c deleted file mode 100644 index fae5d8a..0000000 --- a/tracker/software/drivers/ov2640_old5.c +++ /dev/null @@ -1,1069 +0,0 @@ -/** - * This is the OV2640 driver - * I2C configuring concept has been taken from - * https://github.com/iqyx/ov2640-stm32/blob/master/F4discovery/main.c - */ - -/* - * ov2640 Camera Driver - * - * Copyright (C) 2010 Alberto Panizzo - * - * Based on ov772x, ov9640 drivers and previous non merged implementations. - * - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2006, OmniVision - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "ch.h" -#include "hal.h" -#include "ov2640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV2640_I2C_ADR 0x30 - - -#define VAL_SET(x, mask, rshift, lshift) \ - ((((x) >> rshift) & mask) << lshift) -/* - * DSP registers - * register offset for BANK_SEL == BANK_SEL_DSP - */ -#define R_BYPASS 0x05 /* Bypass DSP */ -#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ -#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ -#define QS 0x44 /* Quantization Scale Factor */ -#define CTRLI 0x50 -#define CTRLI_LP_DP 0x80 -#define CTRLI_ROUND 0x40 -#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) -#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) -#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ -#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ -#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define XOFFL 0x53 /* OFFSET_X[7:0] */ -#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define YOFFL 0x54 /* OFFSET_Y[7:0] */ -#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) -#define VHYX 0x55 /* Offset and size completion */ -#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) -#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) -#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) -#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) -#define DPRP 0x56 -#define TEST 0x57 /* Horizontal size completion */ -#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) -#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ -#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ -#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) -#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ -#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) -#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) -#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) -#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ -#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ -#define CTRL2 0x86 /* DSP Module enable 2 */ -#define CTRL2_DCW_EN 0x20 -#define CTRL2_SDE_EN 0x10 -#define CTRL2_UV_ADJ_EN 0x08 -#define CTRL2_UV_AVG_EN 0x04 -#define CTRL2_CMX_EN 0x01 -#define CTRL3 0x87 /* DSP Module enable 3 */ -#define CTRL3_BPC_EN 0x80 -#define CTRL3_WPC_EN 0x40 -#define SIZEL 0x8C /* Image Size Completion */ -#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) -#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) -#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) -#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ -#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ -#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) -#define CTRL0 0xC2 /* DSP Module enable 0 */ -#define CTRL0_AEC_EN 0x80 -#define CTRL0_AEC_SEL 0x40 -#define CTRL0_STAT_SEL 0x20 -#define CTRL0_VFIRST 0x10 -#define CTRL0_YUV422 0x08 -#define CTRL0_YUV_EN 0x04 -#define CTRL0_RGB_EN 0x02 -#define CTRL0_RAW_EN 0x01 -#define CTRL1 0xC3 /* DSP Module enable 1 */ -#define CTRL1_CIP 0x80 -#define CTRL1_DMY 0x40 -#define CTRL1_RAW_GMA 0x20 -#define CTRL1_DG 0x10 -#define CTRL1_AWB 0x08 -#define CTRL1_AWB_GAIN 0x04 -#define CTRL1_LENC 0x02 -#define CTRL1_PRE 0x01 -#define R_DVP_SP 0xD3 /* DVP output speed control */ -#define R_DVP_SP_AUTO_MODE 0x80 -#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); - * = sysclk (48)/(2*[6:0]) (RAW);*/ -#define IMAGE_MODE 0xDA /* Image Output Format Select */ -#define IMAGE_MODE_Y8_DVP_EN 0x40 -#define IMAGE_MODE_JPEG_EN 0x10 -#define IMAGE_MODE_YUV422 0x00 -#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ -#define IMAGE_MODE_RGB565 0x08 -#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output - * mode (0 for HREF is same as sensor) */ -#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP - * 1: Low byte first UYVY (C2[4] =0) - * VYUY (C2[4] =1) - * 0: High byte first YUYV (C2[4]=0) - * YVYU (C2[4] = 1) */ -#define RESET 0xE0 /* Reset */ -#define RESET_MICROC 0x40 -#define RESET_SCCB 0x20 -#define RESET_JPEG 0x10 -#define RESET_DVP 0x04 -#define RESET_IPU 0x02 -#define RESET_CIF 0x01 -#define REGED 0xED /* Register ED */ -#define REGED_CLK_OUT_DIS 0x10 -#define MS_SP 0xF0 /* SCCB Master Speed */ -#define SS_ID 0xF7 /* SCCB Slave ID */ -#define SS_CTRL 0xF8 /* SCCB Slave Control */ -#define SS_CTRL_ADD_AUTO_INC 0x20 -#define SS_CTRL_EN 0x08 -#define SS_CTRL_DELAY_CLK 0x04 -#define SS_CTRL_ACC_EN 0x02 -#define SS_CTRL_SEN_PASS_THR 0x01 -#define MC_BIST 0xF9 /* Microcontroller misc register */ -#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ -#define MC_BIST_BOOT_ROM_SEL 0x40 -#define MC_BIST_12KB_SEL 0x20 -#define MC_BIST_12KB_MASK 0x30 -#define MC_BIST_512KB_SEL 0x08 -#define MC_BIST_512KB_MASK 0x0C -#define MC_BIST_BUSY_BIT_R 0x02 -#define MC_BIST_MC_RES_ONE_SH_W 0x02 -#define MC_BIST_LAUNCH 0x01 -#define BANK_SEL 0xFF /* Register Bank Select */ -#define BANK_SEL_DSP 0x00 -#define BANK_SEL_SENS 0x01 - -/* - * Sensor registers - * register offset for BANK_SEL == BANK_SEL_SENS - */ -#define GAIN 0x00 /* AGC - Gain control gain setting */ -#define COM1 0x03 /* Common control 1 */ -#define COM1_1_DUMMY_FR 0x40 -#define COM1_3_DUMMY_FR 0x80 -#define COM1_7_DUMMY_FR 0xC0 -#define COM1_VWIN_LSB_UXGA 0x0F -#define COM1_VWIN_LSB_SVGA 0x0A -#define COM1_VWIN_LSB_CIF 0x06 -#define REG04 0x04 /* Register 04 */ -#define REG04_DEF 0x20 /* Always set */ -#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ -#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ -#define REG04_VREF_EN 0x10 -#define REG04_HREF_EN 0x08 -#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) -#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ -#define COM2 0x09 /* Common control 2 */ -#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ - /* Output drive capability */ -#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ -#define PID 0x0A /* Product ID Number MSB */ -#define VER 0x0B /* Product ID Number LSB */ -#define COM3 0x0C /* Common control 3 */ -#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ -#define COM3_BAND_AUTO 0x02 /* Auto Banding */ -#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the - * snapshot sequence*/ -#define AEC 0x10 /* AEC[9:2] Exposure Value */ -#define CLKRC 0x11 /* Internal clock */ -#define CLKRC_EN 0x80 -#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ -#define COM7 0x12 /* Common control 7 */ -#define COM7_SRST 0x80 /* Initiates system reset. All registers are - * set to factory default values after which - * the chip resumes normal operation */ -#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ -#define COM7_RES_SVGA 0x40 /* SVGA */ -#define COM7_RES_CIF 0x20 /* CIF */ -#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ -#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ -#define COM8 0x13 /* Common control 8 */ -#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ -#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ -#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ -#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ -#define COM9 0x14 /* Common control 9 - * Automatic gain ceiling - maximum AGC value [7:5]*/ -#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ -#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ -#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ -#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ -#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ -#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ -#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ -#define COM10 0x15 /* Common control 10 */ -#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ -#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of - * PCLK (user can latch data at the next - * falling edge of PCLK). - * 0 otherwise. */ -#define COM10_HREF_INV 0x08 /* Invert HREF polarity: - * HREF negative for valid data*/ -#define COM10_VSYNC_INV 0x02 /* Invert VSYNC polarity */ -#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ -#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ -#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ -#define VEND 0x1A /* Vertical Window end MSB 8 bit */ -#define MIDH 0x1C /* Manufacturer ID byte - high */ -#define MIDL 0x1D /* Manufacturer ID byte - low */ -#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ -#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ -#define VV 0x26 /* AGC/AEC Fast mode operating region */ -#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) -#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) -#define REG2A 0x2A /* Dummy pixel insert MSB */ -#define FRARL 0x2B /* Dummy pixel insert LSB */ -#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ -#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ -#define YAVG 0x2F /* Y/G Channel Average value */ -#define REG32 0x32 /* Common Control 32 */ -#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ -#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ -#define ARCOM2 0x34 /* Zoom: Horizontal start point */ -#define REG45 0x45 /* Register 45 */ -#define FLL 0x46 /* Frame Length Adjustment LSBs */ -#define FLH 0x47 /* Frame Length Adjustment MSBs */ -#define COM19 0x48 /* Zoom: Vertical start point */ -#define ZOOMS 0x49 /* Zoom: Vertical start point */ -#define COM22 0x4B /* Flash light control */ -#define COM25 0x4E /* For Banding operations */ -#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ -#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ -#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ -#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ -#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ -#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ -#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ -#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ - -#define MANUFACTURER_ID 0x7FA2 -#define PID_OV2640 0x2626 -#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) - -struct regval_list { - uint8_t reg; - uint8_t val; -}; - -/* Supported resolutions */ -enum ov2640_width { - W_QCIF = 176, - W_QVGA = 320, - W_CIF = 352, - W_VGA = 640, - W_SVGA = 800, - W_XGA = 1024, - W_SXGA = 1280, - W_UXGA = 1600, -}; - -enum ov2640_height { - H_QCIF = 144, - H_QVGA = 240, - H_CIF = 288, - H_VGA = 480, - H_SVGA = 600, - H_XGA = 768, - H_SXGA = 1024, - H_UXGA = 1200, -}; - -struct ov2640_win_size { - char *name; - enum ov2640_width width; - enum ov2640_height height; - const struct regval_list *regs; -}; - - -/* - * Registers settings. Most of them are undocumented. Some documentation is - * is available in the OV2640 datasheet, the OV2640 hardware app notes and - * the OV2640 software app notes documents. - */ - -#define ENDMARKER { 0xff, 0xff } - -static const struct regval_list ov2640_init_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0x2c, 0xff }, - { 0x2e, 0xdf }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x3c, 0x32 }, - { CLKRC, CLKRC_DIV_SET(3) }, - { COM2, COM2_OCAP_Nx_SET(3) }, - { REG04, REG04_DEF | REG04_HREF_EN }, - { COM8, COM8_DEF | COM8_AGC_EN | COM8_AEC_EN }, - //~ { AEC, 0x00 }, - { COM9, COM9_AGC_GAIN_8x | 0x08}, - { 0x2c, 0x0c }, - { 0x33, 0x78 }, - { 0x3a, 0x33 }, - { 0x3b, 0xfb }, - { 0x3e, 0x00 }, - { 0x43, 0x11 }, - { 0x16, 0x10 }, - { 0x39, 0x02 }, - { 0x35, 0x88 }, - { 0x22, 0x0a }, - { 0x37, 0x40 }, - { 0x23, 0x00 }, - { ARCOM2, 0xa0 }, - { 0x06, 0x02 }, - { 0x06, 0x88 }, - { 0x07, 0xc0 }, - { 0x0d, 0xb7 }, - { 0x0e, 0x01 }, - { 0x4c, 0x00 }, - { 0x4a, 0x81 }, - { 0x21, 0x99 }, - { AEW, 0x40 }, - { AEB, 0x38 }, - { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, - { 0x5c, 0x00 }, - { 0x63, 0x00 }, - { FLL, 0x22 }, - { COM3, 0x38 | COM3_BAND_AUTO }, - { REG5D, 0x55 }, - { REG5E, 0x7d }, - { REG5F, 0x7d }, - { REG60, 0x55 }, - { HISTO_LOW, 0x70 }, - { HISTO_HIGH, 0x80 }, - { 0x7c, 0x05 }, - { 0x20, 0x80 }, - { 0x28, 0x30 }, - { 0x6c, 0x00 }, - { 0x6d, 0x80 }, - { 0x6e, 0x00 }, - { 0x70, 0x02 }, - { 0x71, 0x94 }, - { 0x73, 0xc1 }, - { 0x3d, 0x34 }, - { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, - { 0x5a, 0x57 }, - { BD50, 0xbb }, - { BD60, 0x9c }, - { BANK_SEL, BANK_SEL_DSP }, - { 0xe5, 0x7f }, - { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, - { 0x41, 0x24 }, - { RESET, RESET_JPEG | RESET_DVP }, - { 0x76, 0xff }, - { 0x33, 0xa0 }, - { 0x42, 0x20 }, - { 0x43, 0x18 }, - { 0x4c, 0x00 }, - { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, - { 0x88, 0x3f }, - { 0xd7, 0x03 }, - { 0xd9, 0x10 }, - { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, - { 0xc8, 0x08 }, - { 0xc9, 0x80 }, - { BPADDR, 0x00 }, - { BPDATA, 0x00 }, - { BPADDR, 0x03 }, - { BPDATA, 0x48 }, - { BPDATA, 0x48 }, - { BPADDR, 0x08 }, - { BPDATA, 0x20 }, - { BPDATA, 0x10 }, - { BPDATA, 0x0e }, - { 0x90, 0x00 }, - { 0x91, 0x0e }, - { 0x91, 0x1a }, - { 0x91, 0x31 }, - { 0x91, 0x5a }, - { 0x91, 0x69 }, - { 0x91, 0x75 }, - { 0x91, 0x7e }, - { 0x91, 0x88 }, - { 0x91, 0x8f }, - { 0x91, 0x96 }, - { 0x91, 0xa3 }, - { 0x91, 0xaf }, - { 0x91, 0xc4 }, - { 0x91, 0xd7 }, - { 0x91, 0xe8 }, - { 0x91, 0x20 }, - { 0x92, 0x00 }, - { 0x93, 0x06 }, - { 0x93, 0xe3 }, - { 0x93, 0x03 }, - { 0x93, 0x03 }, - { 0x93, 0x00 }, - { 0x93, 0x02 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x93, 0x00 }, - { 0x96, 0x00 }, - { 0x97, 0x08 }, - { 0x97, 0x19 }, - { 0x97, 0x02 }, - { 0x97, 0x0c }, - { 0x97, 0x24 }, - { 0x97, 0x30 }, - { 0x97, 0x28 }, - { 0x97, 0x26 }, - { 0x97, 0x02 }, - { 0x97, 0x98 }, - { 0x97, 0x80 }, - { 0x97, 0x00 }, - { 0x97, 0x00 }, - { 0xa4, 0x00 }, - { 0xa8, 0x00 }, - { 0xc5, 0x11 }, - { 0xc6, 0x51 }, - { 0xbf, 0x80 }, - { 0xc7, 0x10 }, /* white balance */ - { 0xb6, 0x66 }, - { 0xb8, 0xA5 }, - { 0xb7, 0x64 }, - { 0xb9, 0x7C }, - { 0xb3, 0xaf }, - { 0xb4, 0x97 }, - { 0xb5, 0xFF }, - { 0xb0, 0xC5 }, - { 0xb1, 0x94 }, - { 0xb2, 0x0f }, - { 0xc4, 0x5c }, - { 0xa6, 0x00 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x1b }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0xa7, 0x20 }, - { 0xa7, 0xd8 }, - { 0xa7, 0x19 }, - { 0xa7, 0x31 }, - { 0xa7, 0x00 }, - { 0xa7, 0x18 }, - { 0x7f, 0x00 }, - { 0xe5, 0x1f }, - { 0xe1, 0x77 }, - { 0xdd, 0x7f }, - { QS, 0x0C }, - { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN }, - ENDMARKER, -}; - -/* - * Register settings for window size - * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. - * Then the different zooming configurations will setup the output image size. - */ -static const struct regval_list ov2640_size_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { RESET, RESET_DVP }, - { HSIZE8, HSIZE8_SET(W_UXGA) }, - { VSIZE8, VSIZE8_SET(H_UXGA) }, - { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | - CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, - { HSIZE, HSIZE_SET(W_UXGA) }, - { VSIZE, VSIZE_SET(H_UXGA) }, - { XOFFL, XOFFL_SET(0) }, - { YOFFL, YOFFL_SET(0) }, - { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) | - VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, - { TEST, TEST_HSIZE_SET(W_UXGA) }, - ENDMARKER, -}; - -#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ - { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ - CTRLI_H_DIV_SET(h_div)}, \ - { ZMOW, ZMOW_OUTW_SET(x) }, \ - { ZMOH, ZMOH_OUTH_SET(y) }, \ - { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ - { R_DVP_SP, pclk_div }, \ - { RESET, 0x00} - -static const struct regval_list ov2640_qcif_regs[] = { - PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_qvga_regs[] = { - PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4), - ENDMARKER, -}; - -static const struct regval_list ov2640_cif_regs[] = { - PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8), - ENDMARKER, -}; - -static const struct regval_list ov2640_vga_regs[] = { - PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_svga_regs[] = { - PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2), - ENDMARKER, -}; - -static const struct regval_list ov2640_xga_regs[] = { - PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2), - { CTRLI, 0x00}, - ENDMARKER, -}; - -static const struct regval_list ov2640_sxga_regs[] = { - PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2), - { CTRLI, 0x00}, - { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uxga_regs[] = { - PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0), - { CTRLI, 0x00}, - { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, - ENDMARKER, -}; - -#define OV2640_SIZE(n, w, h, r) \ - {.name = n, .width = w , .height = h, .regs = r } - -static const struct ov2640_win_size ov2640_supported_win_sizes[] = { - OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs), - OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs), - OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs), - OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs), - OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs), - OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs), - OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs), - OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs), -}; - -/* - * Register settings for pixel formats - */ -static const struct regval_list ov2640_format_change_preamble_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_yuyv_regs[] = { - { IMAGE_MODE, IMAGE_MODE_YUV422 }, - { 0xd7, 0x03 }, - { 0x33, 0xa0 }, - { 0xe5, 0x1f }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_uyvy_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, - { 0xd7, 0x01 }, - { 0x33, 0xa0 }, - { 0xe1, 0x67 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_be_regs[] = { - { IMAGE_MODE, IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_rgb565_le_regs[] = { - { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, - { 0xd7, 0x03 }, - { RESET, 0x00 }, - { R_BYPASS, R_BYPASS_USE_DSP }, - ENDMARKER, -}; - -static const struct regval_list ov2640_jpeg_regs[] = { - { BANK_SEL, BANK_SEL_DSP }, - { 0xe0, 0x14 }, - { 0xe1, 0x77 }, - { 0xe5, 0x1f }, - { 0xd7, 0x03 }, - { IMAGE_MODE, IMAGE_MODE_JPEG_EN }, - { 0xe0, 0x00 }, - { BANK_SEL, BANK_SEL_SENS }, - { 0x04, 0x08 }, - ENDMARKER, -}; - -ssdv_conf_t *ov2640_conf; -uint32_t size; - -/** - * Captures an image from the camera. - */ -bool OV2640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV2640_Capture(); - - return true; -} - -bool OV2640_BufferOverflow(void) -{ - return ov2640_conf->ram_buffer[0] != 0xFF || ov2640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV2640_getBuffer(uint8_t** buffer) { - *buffer = ov2640_conf->ram_buffer; - return ov2640_conf->size_sampled; -} - - -#if 0 - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - /* Clear any pending inerrupts. */ - dmaStreamClearInterrupt(dmastp); - dmaStreamEnable(dmastp); - return 0; -} - -inline int32_t dma_stop(void) { - dmaStreamDisable(dmastp); - dmaStreamRelease(dmastp); - return 0; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Deprecate - Nothing really to do at half way point. */ - return; - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* End of transfer. */ - palSetLine(LINE_IO_LED1); - - /* - * Stop TIM8 DMA trigger. - * Stop and release DMA channel. - * Either DMA count full or VSNC traling edge can terminate frame capture - */ - TIM8->DIER &= ~TIM_DIER_CC1DE; - dma_stop(); - return; - } - /* - * TODO: Anything else is an error. - * Maybe set an error flag? - */ -} - -static bool image_finished; - - -// This is the vector for HREF (EXTI2) (stolen from hal_ext_lld_isr.c) - -CH_FAST_IRQ_HANDLER(Vector60) { - CH_IRQ_PROLOGUE(); - - uint8_t gpioc = GPIOC->IDR; - // HREF handling - if(gpioc & 0x4) { - // HREF rising edge, start capturing data on pixel clock - /* - * Start or re-start dma. The transfer count already set will be used. - * The M0AR (DMA memory address) register is set for autoincrement. - * It will be pointing to the next buffer address when DMA is re-started. - */ - //dma_start(); - /* Set TIM8 trigger to initate DMA. */ - TIM8->DIER |= TIM_DIER_CC1DE; - } else { - /* Remove TIM8 trigger to initate DMA. */ - TIM8->DIER &= ~TIM_DIER_CC1DE; - } - - EXTI->PR |= EXTI_PR_PR2; - CH_IRQ_EPILOGUE(); -} - -bool vsync = false; - -// This is the vector for EXTI1 (stolen from hal_ext_lld_isr.c) -/* - * Note: VSYNC is a pulse the full length of a frame. - * This is contrary to the OV2640 datasheet which shows VSYNC as pulses. -*/ -CH_FAST_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - // VSYNC handling - if(!vsync && palReadLine(LINE_CAM_VSYNC)) { - /* - * Rising edge of VSYNC after LPTIM1 has been initiualized. - * Start DMA channel. - * Enable TIM8 trigger of DMA. - */ - dma_start(); - TIM8->DIER |= TIM_DIER_CC1DE; - palClearLine(LINE_IO_LED1); // Indicate that picture will be captured - vsync = true; - } else if(vsync) { - /* VSYNC falling edge - end of JPEG frame. - * Stop & release the DMA channel. - * Disable TIM8 trigger of DMA and stop PCLK via LPTIM1 - * These should have already been disabled in DMA interrupt if was filled. - */ - dma_stop(); - TIM8->DIER &= ~TIM_DIER_CC1DE; - - /* Disable VYSNC edge interrupts. */ - nvicDisableVector(EXTI1_IRQn); - //nvicDisableVector(EXTI2_IRQn); - /* Turn on capture LED and signal the semaphore (data can be processed). */ - palSetLine(LINE_IO_LED1); - image_finished = true; - vsync = false; - } - - palToggleLine(LINE_IO_LED1); - - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - -bool OV2640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM8_CH1 - DMA2 stream 2, channel 7 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 2)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(7) | - STM32_DMA_CR_PL(2) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_MBURST_INCR16; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov2640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov2640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - dmaStreamSetFIFO(dmastp, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); - - /* - * Setup timer to trigger DMA. - * We have to use TIM8 because... - * > TIM8_CH1 is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccResetTIM8(); - rccEnableTIM8(FALSE); - - TIM8->CCMR1 = TIM_CCMR1_CC1S_0; // Select channel 1 as input - TIM8->CCER |= TIM_CCER_CC1E; // Enable capture channel - TIM8->CCER |= TIM_CCER_CC1P; // Select trailing edge - - image_finished = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC | SYSCFG_EXTICR1_EXTI2_PC; - - EXTI->IMR = EXTI_IMR_MR1 | EXTI_IMR_MR2; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1 | EXTI_RTSR_TR2; // Listen on rising edge - EXTI->FTSR = EXTI_FTSR_TR1 | EXTI_FTSR_TR2; // Listen on falling edge too - - nvicEnableVector(EXTI1_IRQn, 2); // Enable interrupt - nvicEnableVector(EXTI2_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - //TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - chThdSleepMilliseconds(100); - } while(!image_finished); - - int32_t size=65535; - while(ov2640_conf->ram_buffer[size] == 0 && size >= 0) - size--; - TRACE_DEBUG("CAM > Image %d %02x %02x %02x %02x", size, ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - - TRACE_DEBUG("CAM > Have a look for SOI"); - uint32_t soi; // Start of Image - for(soi=0; soi<65533; soi++) - { - if(ov2640_conf->ram_buffer[soi] == 0xFF && ov2640_conf->ram_buffer[soi+1] == 0xD8) - break; - } - - if(soi == 65533) { - TRACE_ERROR("CAM > Could not find SOI flag"); - return false; // We failed to sample the picture correctly because we didn't find the JPEG SOI flag - } - - TRACE_DEBUG("SOI=%d", soi) - - // Found SOI, move bytes - for(uint32_t i=0; i<65535; i++) - ov2640_conf->ram_buffer[i] = ov2640_conf->ram_buffer[i+soi]; - - TRACE_DEBUG("CAM > Image %02x %02x %02x %02x", ov2640_conf->ram_buffer[0], ov2640_conf->ram_buffer[1], ov2640_conf->ram_buffer[2], ov2640_conf->ram_buffer[3]); - TRACE_INFO("CAM > Capture finished"); - - return true; -} -#else - -bool OV2640_Capture(void) -{ - TRACE_INFO("CAM > Start capture"); - while(1) - { - while(palReadLine(LINE_CAM_VSYNC)); - while(!palReadLine(LINE_CAM_VSYNC)); - - uint8_t gpioc; - uint8_t gpioa; - ov2640_conf->size_sampled = 0; - while(true) - { - do { - gpioc = GPIOC->IDR & 0x7; - } while((gpioc & 0x1) != 0x1); // Wait for PCLK to rise - - gpioa = GPIOA->IDR; - - switch(gpioc) { - case 0x3: - break; - case 0x7: - ov2640_conf->ram_buffer[ov2640_conf->size_sampled++] = gpioa; - break; - default: - return true; - } - - // Wait for falling edge - while(GPIOC->IDR & 0x1); - } - } -} - - - -#endif - -/** - * Initializes GPIO (for pseudo DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV2640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - /* PC6 AF3 = TIM8_CH1. */ - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(3)); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPadMode(GPIOC, 0, PAL_MODE_INPUT); - palSetPadMode(GPIOB, 15, PAL_MODE_INPUT); -} - -void OV2640_TransmitConfig(void) -{ - // Set to page 1 - I2C_write8_locked(OV2640_I2C_ADR, 0xff, 0x01); - I2C_write8_locked(OV2640_I2C_ADR, 0x12, 0x80); - chThdSleepMilliseconds(50); - - /* Write selected arrays to the camera to initialize it and set the - * desired output format. */ - for(uint32_t i=0; (ov2640_init_regs[i].reg != 0xff) || (ov2640_init_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_init_regs[i].reg, ov2640_init_regs[i].val); - - for(uint32_t i=0; (ov2640_size_change_preamble_regs[i].reg != 0xff) || (ov2640_size_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_size_change_preamble_regs[i].reg, ov2640_size_change_preamble_regs[i].val); - - switch(ov2640_conf->res) { - case RES_QCIF: - for(uint32_t i=0; (ov2640_qcif_regs[i].reg != 0xff) || (ov2640_qcif_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qcif_regs[i].reg, ov2640_qcif_regs[i].val); - break; - - case RES_QVGA: - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (ov2640_vga_regs[i].reg != 0xff) || (ov2640_vga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_vga_regs[i].reg, ov2640_vga_regs[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (ov2640_xga_regs[i].reg != 0xff) || (ov2640_xga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_xga_regs[i].reg, ov2640_xga_regs[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (ov2640_uxga_regs[i].reg != 0xff) || (ov2640_uxga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_uxga_regs[i].reg, ov2640_uxga_regs[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (ov2640_qvga_regs[i].reg != 0xff) || (ov2640_qvga_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_qvga_regs[i].reg, ov2640_qvga_regs[i].val); - } - - for(uint32_t i=0; (ov2640_format_change_preamble_regs[i].reg != 0xff) || (ov2640_format_change_preamble_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_format_change_preamble_regs[i].reg, ov2640_format_change_preamble_regs[i].val); - for(uint32_t i=0; (ov2640_yuyv_regs[i].reg != 0xff) || (ov2640_yuyv_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_yuyv_regs[i].reg, ov2640_yuyv_regs[i].val); - - for(uint32_t i=0; (ov2640_jpeg_regs[i].reg != 0xff) || (ov2640_jpeg_regs[i].val != 0xff); i++) - I2C_write8_locked(OV2640_I2C_ADR, ov2640_jpeg_regs[i].reg, ov2640_jpeg_regs[i].val); -} - -void OV2640_init(ssdv_conf_t *config) { - ov2640_conf = config; - - // Take I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_lock(); - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov2640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV2640_InitGPIO(); - - // Power on OV2640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV2640 - TRACE_INFO("CAM > Transmit config to camera"); - OV2640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV2640_deinit(void) { - // Power off OV2640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); - - // Release I2C (due to silicon bug of OV2640, it interferes if byte 0x30 transmitted on I2C bus) - I2C_unlock(); -} - -bool OV2640_isAvailable(void) -{ - I2C_lock(); - - // Configure pins - OV2640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint16_t val; - bool ret; - if(I2C_read16_locked(OV2640_I2C_ADR, 0x0A, &val)) - ret = val == PID_OV2640; - else - ret = false; - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - I2C_unlock(); - - return ret; -} - diff --git a/tracker/software/drivers/ov5640_working_patch_tim8.c b/tracker/software/drivers/ov5640_working_patch_tim8.c deleted file mode 100644 index dc08908..0000000 --- a/tracker/software/drivers/ov5640_working_patch_tim8.c +++ /dev/null @@ -1,1234 +0,0 @@ -/* - * Registers by Arducam https://github.com/ArduCAM/Arduino/blob/master/ArduCAM/ov5640_regs.h - * https://github.com/ArduCAM/Arduino/blob/master/ArduCAM/ArduCAM.cpp - */ - -#include "ch.h" -#include "hal.h" -#include "ov5640.h" -#include "pi2c.h" -#include "board.h" -#include "defines.h" -#include "debug.h" -#include - -#define OV5640_I2C_ADR 0x3C - -struct regval_list { - uint16_t reg; - uint8_t val; -}; - -static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] = -{ - { 0x4740, 0x04 }, - - { 0x4050, 0x6e }, - { 0x4051, 0x8f }, - - { 0x3008, 0x42 }, - { 0x3103, 0x03 }, - { 0x3017, 0x7f }, - { 0x3018, 0xff }, - { 0x302c, 0x02 }, - { 0x3108, 0x31 }, - { 0x3630, 0x2e },//2e - { 0x3632, 0xe2 }, - { 0x3633, 0x23 },//23 - { 0x3621, 0xe0 }, - { 0x3704, 0xa0 }, - { 0x3703, 0x5a }, - { 0x3715, 0x78 }, - { 0x3717, 0x01 }, - { 0x370b, 0x60 }, - { 0x3705, 0x1a }, - { 0x3905, 0x02 }, - { 0x3906, 0x10 }, - { 0x3901, 0x0a }, - { 0x3731, 0x12 }, - { 0x3600, 0x08 }, - { 0x3601, 0x33 }, - { 0x302d, 0x60 }, - { 0x3620, 0x52 }, - { 0x371b, 0x20 }, - { 0x471c, 0x50 }, - - { 0x3a18, 0x00 }, - { 0x3a19, 0xf8 }, - - { 0x3635, 0x1c },//1c - { 0x3634, 0x40 }, - { 0x3622, 0x01 }, - - { 0x3c04, 0x28 }, - { 0x3c05, 0x98 }, - { 0x3c06, 0x00 }, - { 0x3c07, 0x08 }, - { 0x3c08, 0x00 }, - { 0x3c09, 0x1c }, - { 0x3c0a, 0x9c }, - { 0x3c0b, 0x40 }, - - { 0x3820, 0x41 }, - { 0x3821, 0x01 }, //07 - - //windows setup - { 0x3800, 0x00 }, - { 0x3801, 0x00 }, - { 0x3802, 0x00 }, - { 0x3803, 0x04 }, - { 0x3804, 0x0a }, - { 0x3805, 0x3f }, - { 0x3806, 0x07 }, - { 0x3807, 0x9b }, - { 0x3808, 0x05 }, - { 0x3809, 0x00 }, - { 0x380a, 0x03 }, - { 0x380b, 0xc0 }, - { 0x3810, 0x00 }, - { 0x3811, 0x10 }, - { 0x3812, 0x00 }, - { 0x3813, 0x06 }, - { 0x3814, 0x31 }, - { 0x3815, 0x31 }, - - { 0x3034, 0x1a }, - { 0x3035, 0x11 }, //15fps - { 0x3036, 0x46 }, - { 0x3037, 0x13 }, - { 0x3038, 0x00 }, - { 0x3039, 0x00 }, - - { 0x380c, 0x07 }, - { 0x380d, 0x68 }, - { 0x380e, 0x03 }, //03 - { 0x380f, 0xd8 }, //d8 - - { 0x3c01, 0xb4 }, - { 0x3c00, 0x04 }, - { 0x3a08, 0x00 }, - { 0x3a09, 0x93 }, - { 0x3a0e, 0x06 }, - { 0x3a0a, 0x00 }, - { 0x3a0b, 0x7b }, - { 0x3a0d, 0x08 }, - - { 0x3a00, 0x3c }, //15fps-10fps - { 0x3a02, 0x05 }, - { 0x3a03, 0xc4 }, - { 0x3a14, 0x05 }, - { 0x3a15, 0xc4 }, - - { 0x3618, 0x00 }, - { 0x3612, 0x29 }, - { 0x3708, 0x64 }, - { 0x3709, 0x52 }, - { 0x370c, 0x03 }, - - { 0x4001, 0x02 }, - { 0x4004, 0x02 }, - { 0x3000, 0x00 }, - { 0x3002, 0x1c }, - { 0x3004, 0xff }, - { 0x3006, 0xc3 }, - { 0x300e, 0x58 }, - { 0x302e, 0x00 }, - { 0x4300, 0x30 }, - { 0x501f, 0x00 }, - { 0x4713, 0x03 }, - { 0x4407, 0x04 }, - { 0x460b, 0x35 }, - { 0x460c, 0x22 },//add by bright - { 0x3824, 0x01 },//add by bright - { 0x5001, 0xa3 }, - - { 0x3406, 0x01 },//awbinit - { 0x3400, 0x06 }, - { 0x3401, 0x80 }, - { 0x3402, 0x04 }, - { 0x3403, 0x00 }, - { 0x3404, 0x06 }, - { 0x3405, 0x00 }, - //awb - { 0x5180, 0xff }, - { 0x5181, 0xf2 }, - { 0x5182, 0x00 }, - { 0x5183, 0x14 }, - { 0x5184, 0x25 }, - { 0x5185, 0x24 }, - { 0x5186, 0x16 }, - { 0x5187, 0x16 }, - { 0x5188, 0x16 }, - { 0x5189, 0x62 }, - { 0x518a, 0x62 }, - { 0x518b, 0xf0 }, - { 0x518c, 0xb2 }, - { 0x518d, 0x50 }, - { 0x518e, 0x30 }, - { 0x518f, 0x30 }, - { 0x5190, 0x50 }, - { 0x5191, 0xf8 }, - { 0x5192, 0x04 }, - { 0x5193, 0x70 }, - { 0x5194, 0xf0 }, - { 0x5195, 0xf0 }, - { 0x5196, 0x03 }, - { 0x5197, 0x01 }, - { 0x5198, 0x04 }, - { 0x5199, 0x12 }, - { 0x519a, 0x04 }, - { 0x519b, 0x00 }, - { 0x519c, 0x06 }, - { 0x519d, 0x82 }, - { 0x519e, 0x38 }, - //color matrix - { 0x5381, 0x1e }, - { 0x5382, 0x5b }, - { 0x5383, 0x14 }, - { 0x5384, 0x06 }, - { 0x5385, 0x82 }, - { 0x5386, 0x88 }, - { 0x5387, 0x7c }, - { 0x5388, 0x60 }, - { 0x5389, 0x1c }, - { 0x538a, 0x01 }, - { 0x538b, 0x98 }, - //sharp&noise - { 0x5300, 0x08 }, - { 0x5301, 0x30 }, - { 0x5302, 0x3f }, - { 0x5303, 0x10 }, - { 0x5304, 0x08 }, - { 0x5305, 0x30 }, - { 0x5306, 0x18 }, - { 0x5307, 0x28 }, - { 0x5309, 0x08 }, - { 0x530a, 0x30 }, - { 0x530b, 0x04 }, - { 0x530c, 0x06 }, - //gamma - { 0x5480, 0x01 }, - { 0x5481, 0x06 }, - { 0x5482, 0x12 }, - { 0x5483, 0x24 }, - { 0x5484, 0x4a }, - { 0x5485, 0x58 }, - { 0x5486, 0x65 }, - { 0x5487, 0x72 }, - { 0x5488, 0x7d }, - { 0x5489, 0x88 }, - { 0x548a, 0x92 }, - { 0x548b, 0xa3 }, - { 0x548c, 0xb2 }, - { 0x548d, 0xc8 }, - { 0x548e, 0xdd }, - { 0x548f, 0xf0 }, - { 0x5490, 0x15 }, - //UV adjust - { 0x5580, 0x06 }, - { 0x5583, 0x40 }, - { 0x5584, 0x20 }, - { 0x5589, 0x10 }, - { 0x558a, 0x00 }, - { 0x558b, 0xf8 }, - //lens shading - { 0x5000, 0xa7 }, - { 0x5800, 0x20 }, - { 0x5801, 0x19 }, - { 0x5802, 0x17 }, - { 0x5803, 0x16 }, - { 0x5804, 0x18 }, - { 0x5805, 0x21 }, - { 0x5806, 0x0F }, - { 0x5807, 0x0A }, - { 0x5808, 0x07 }, - { 0x5809, 0x07 }, - { 0x580a, 0x0A }, - { 0x580b, 0x0C }, - { 0x580c, 0x0A }, - { 0x580d, 0x03 }, - { 0x580e, 0x01 }, - { 0x580f, 0x01 }, - { 0x5810, 0x03 }, - { 0x5811, 0x09 }, - { 0x5812, 0x0A }, - { 0x5813, 0x03 }, - { 0x5814, 0x01 }, - { 0x5815, 0x01 }, - { 0x5816, 0x03 }, - { 0x5817, 0x08 }, - { 0x5818, 0x10 }, - { 0x5819, 0x0A }, - { 0x581a, 0x06 }, - { 0x581b, 0x06 }, - { 0x581c, 0x08 }, - { 0x581d, 0x0E }, - { 0x581e, 0x22 }, - { 0x581f, 0x18 }, - { 0x5820, 0x13 }, - { 0x5821, 0x12 }, - { 0x5822, 0x16 }, - { 0x5823, 0x1E }, - { 0x5824, 0x64 }, - { 0x5825, 0x2A }, - { 0x5826, 0x2C }, - { 0x5827, 0x2A }, - { 0x5828, 0x46 }, - { 0x5829, 0x2A }, - { 0x582a, 0x26 }, - { 0x582b, 0x24 }, - { 0x582c, 0x26 }, - { 0x582d, 0x2A }, - { 0x582e, 0x28 }, - { 0x582f, 0x42 }, - { 0x5830, 0x40 }, - { 0x5831, 0x42 }, - { 0x5832, 0x08 }, - { 0x5833, 0x28 }, - { 0x5834, 0x26 }, - { 0x5835, 0x24 }, - { 0x5836, 0x26 }, - { 0x5837, 0x2A }, - { 0x5838, 0x44 }, - { 0x5839, 0x4A }, - { 0x583a, 0x2C }, - { 0x583b, 0x2a }, - { 0x583c, 0x46 }, - { 0x583d, 0xCE }, - - { 0x5688, 0x22 }, - { 0x5689, 0x22 }, - { 0x568a, 0x42 }, - { 0x568b, 0x24 }, - { 0x568c, 0x42 }, - { 0x568d, 0x24 }, - { 0x568e, 0x22 }, - { 0x568f, 0x22 }, - - { 0x5025, 0x00 }, - - { 0x3a0f, 0x30 }, - { 0x3a10, 0x28 }, - { 0x3a1b, 0x30 }, - { 0x3a1e, 0x28 }, - { 0x3a11, 0x61 }, - { 0x3a1f, 0x10 }, - - { 0x4005, 0x1a }, - { 0x3406, 0x00 },//awbinit - { 0x3503, 0x00 },//awbinit - { 0x3008, 0x02 }, - { 0xffff, 0xff }, -}; - - - -static const struct regval_list ov5640_vga_preview[] = -{ - // YUV VGA 30fps, night mode 5fps - // Input Clock = 24Mhz, PCLK = 56MHz - { 0x3035, 0x11 }, // PLL - { 0x3036, 0x46 }, // PLL - { 0x3c07, 0x08 }, // light meter 1 threshold [7:0] - { 0x3820, 0x41 }, // Sensor flip off, ISP flip on - { 0x3821, 0x01 }, // Sensor mirror on, ISP mirror on, H binning on - { 0x3814, 0x31 }, // X INC - { 0x3815, 0x31 }, // Y INC - { 0x3800, 0x00 }, // HS - { 0x3801, 0x00 }, // HS - { 0x3802, 0x00 }, // VS - { 0x3803, 0x04 }, // VS - { 0x3804, 0x0a }, // HW (HE) - { 0x3805, 0x3f }, // HW (HE) - { 0x3806, 0x07 }, // VH (VE) - { 0x3807, 0x9b }, // VH (VE) - { 0x3808, 0x02 }, // DVPHO - { 0x3809, 0x80 }, // DVPHO - { 0x380a, 0x01 }, // DVPVO - { 0x380b, 0xe0 }, // DVPVO - { 0x380c, 0x07 }, // HTS - { 0x380d, 0x68 }, // HTS - { 0x380e, 0x03 }, // VTS - { 0x380f, 0xd8 }, // VTS - { 0x3813, 0x06 }, // Timing Voffset - { 0x3618, 0x00 }, - { 0x3612, 0x29 }, - { 0x3709, 0x52 }, - { 0x370c, 0x03 }, - { 0x3a02, 0x17 }, // 60Hz max exposure, night mode 5fps - { 0x3a03, 0x10 }, // 60Hz max exposure - // banding filters are calculated automatically in camera driver - //{ 0x3a08, 0x01 }, // B50 step - //{ 0x3a09, 0x27 }, // B50 step - //{ 0x3a0a, 0x00 }, // B60 step - //{ 0x3a0b, 0xf6 }, // B60 step - //{ 0x3a0e, 0x03 }, // 50Hz max band - //{ 0x3a0d, 0x04 }, // 60Hz max band - { 0x3a14, 0x17 }, // 50Hz max exposure, night mode 5fps - { 0x3a15, 0x10 }, // 50Hz max exposure - { 0x4004, 0x02 }, // BLC 2 lines - { 0x3002, 0x1c }, // reset JFIFO, SFIFO, JPEG - { 0x3006, 0xc3 }, // disable clock of JPEG2x, JPEG - { 0x4713, 0x03 }, // JPEG mode 3 - { 0x4407, 0x04 }, // Quantization scale - { 0x460b, 0x35 }, - { 0x460c, 0x22 }, - { 0x4837, 0x22 }, // DVP CLK divider - { 0x3824, 0x02 }, // DVP CLK divider - { 0x5001, 0xa3 }, // SDE on, scale on, UV average off, color matrix on, AWB on - { 0x3503, 0x00 }, // AEC/AGC on -}; - -static const struct regval_list OV5640_RGB_QVGA[] = -{ - {0x3008, 0x02}, - {0x3035, 0x11}, - {0x4740, 0x21}, - {0x4300, 0x61}, - {0x3808, 0x01}, - {0x3809, 0x40}, - {0x380a, 0x00}, - {0x380b, 0xf0}, - {0x501f, 0x01}, - {0xffff, 0xff}, -}; - -//2592x1944 QSXGA -static const struct regval_list OV5640_JPEG_QSXGA[] = -{ - {0x3820 ,0x41}, - {0x3821 ,0x26}, - {0x3814 ,0x11}, - {0x3815 ,0x11}, - {0x3803 ,0x00}, - {0x3807 ,0x9f}, - {0x3808 ,0x0a}, - {0x3809 ,0x20}, - {0x380a ,0x07}, - {0x380b ,0x98}, - {0x380c ,0x0b}, - {0x380d ,0x1c}, - {0x380e ,0x07}, - {0x380f ,0xb0}, - {0x3813 ,0x04}, - {0x3618 ,0x04}, - {0x3612 ,0x4b}, - {0x3708 ,0x64}, - {0x3709 ,0x12}, - {0x370c ,0x00}, - {0x3a02 ,0x07}, - {0x3a03 ,0xb0}, - {0x3a0e ,0x06}, - {0x3a0d ,0x08}, - {0x3a14 ,0x07}, - {0x3a15 ,0xb0}, - {0x4001 ,0x02}, - {0x4004 ,0x06}, - {0x3002 ,0x00}, - {0x3006 ,0xff}, - {0x3824 ,0x04}, - {0x5001 ,0x83}, - {0x3036 ,0x69}, - {0x3035 ,0x11}, - {0x4005 ,0x1A}, - {0xffff, 0xff}, -}; - -//5MP -static const struct regval_list OV5640_5MP_JPEG[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0xA }, - {0x3809 ,0x20}, - {0x380a ,0x7 }, - {0x380b ,0x98}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//320x240 QVGA -static const struct regval_list OV5640_QSXGA2QVGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x1 }, - {0x3809 ,0x40}, - {0x380a ,0x0 }, - {0x380b ,0xf0}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//640x480 VGA -static const struct regval_list OV5640_QSXGA2VGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x2 }, - {0x3809 ,0x80}, - {0x380a ,0x1 }, - {0x380b ,0xe0}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//800x480 WVGA -static const struct regval_list OV5640_QSXGA2WVGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x3 }, - {0x3809 ,0x20}, - {0x380a ,0x1 }, - {0x380b ,0xe0}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x3810, 0x00}, - {0x3811, 0x10}, - {0x3812, 0x01}, - {0x3813, 0x48}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//352x288 CIF -static const struct regval_list OV5640_QSXGA2CIF[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x1 }, - {0x3809 ,0x60}, - {0x380a ,0x1 }, - {0x380b ,0x20}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x3810, 0x00}, - {0x3811, 0x10}, - {0x3812, 0x00}, - {0x3813, 0x70}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//1280x960 SXGA -static const struct regval_list OV5640_QSXGA2SXGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x5 }, - {0x3809 ,0x0 }, - {0x380a ,0x3 }, - {0x380b ,0xc0}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//2048x1536 QXGA -static const struct regval_list OV5640_QSXGA2QXGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x8 }, - {0x3809 ,0x0 }, - {0x380a ,0x6 }, - {0x380b ,0x0 }, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - - -//1600x1200 UXGA -static const struct regval_list OV5640_QSXGA2UXGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x6 }, - {0x3809 ,0x40}, - {0x380a ,0x4 }, - {0x380b ,0xb0}, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - -//1024x768 XGA -static const struct regval_list OV5640_QSXGA2XGA[] = -{ - {0x3800 ,0x00}, - {0x3801 ,0x00}, - {0x3802 ,0x00}, - {0x3803 ,0x00}, - {0x3804 ,0xA }, - {0x3805 ,0x3f}, - {0x3806 ,0x7 }, - {0x3807 ,0x9f}, - {0x3808 ,0x4 }, - {0x3809 ,0x0 }, - {0x380a ,0x3 }, - {0x380b ,0x0 }, - {0x380c ,0xc }, - {0x380d ,0x80}, - {0x380e ,0x7 }, - {0x380f ,0xd0}, - {0x5001 ,0xa3}, - {0x5680 ,0x0 }, - {0x5681 ,0x0 }, - {0x5682 ,0xA }, - {0x5683 ,0x20}, - {0x5684 ,0x0 }, - {0x5685 ,0x0 }, - {0x5686 ,0x7 }, - {0x5687 ,0x98}, - {0xffff, 0xff}, -}; - - -static ssdv_conf_t *ov5640_conf; - -/* TODO: Implement a state machine instead of multiple flags. */ -//static bool LptimRdy; -static bool capture_finished; -static bool capture_error; -static bool vsync; -static bool dma_fault; -static bool dma_overrun; - -/** - * Captures an image from the camera. - */ -bool OV5640_Snapshot2RAM(void) -{ - // Capture enable - TRACE_INFO("CAM > Capture image"); - OV5640_Capture(); - - return true; -} - -bool OV5640_BufferOverflow(void) -{ - return ov5640_conf->ram_buffer[0] != 0xFF || ov5640_conf->ram_buffer[1] != 0xD8; // Check for JPEG SOI header -} - -uint32_t OV5640_getBuffer(uint8_t** buffer) { - *buffer = ov5640_conf->ram_buffer; - return ov5640_conf->size_sampled; -} - -const stm32_dma_stream_t *dmastp; - -inline int32_t dma_start(void) { - /* Clear any pending interrupts. */ - dmaStreamClearInterrupt(dmastp); - dmaStreamEnable(dmastp); - return 0; -} - -/* - * Stop DMA release stream and return count remaining. - * Note that any DMA FIFO transfer will complete. - * The Chibios DMAV2 driver waits for EN to clear before proceeding. - */ -inline uint16_t dma_stop(void) { - dmaStreamDisable(dmastp); - uint16_t transfer = dmaStreamGetTransactionSize(dmastp); - dmaStreamRelease(dmastp); - return transfer; -} - -static void dma_interrupt(void *p, uint32_t flags) { - (void)p; - - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* - * Nothing really to do at half way point for now. - * Implementing DBM will use HTIF. - */ - return; - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Disable VYSNC edge interrupts. */ - //nvicDisableVector(EXTI1_IRQn); - //capture_finished = true; - - /* - * If DMA has run to end within a frame then this is an error. - * In single buffer mode DMA should always be terminated by VSYNC. - * - * Stop PCLK from LPTIM1 and disable TIM1 DMA trigger. - * Dont stop the DMA here. Its going to be stopped by the leading edge of VSYNC. - */ - TIM8->DIER &= ~TIM_DIER_CC1DE; - TIM8->CCER &= ~TIM_CCER_CC1E; - //LPTIM8->CR &= ~LPTIM_CR_CNTSTRT; - dma_overrun = true; - capture_error = true; - return; - } - /* - * TODO: Anything else is an error. - * Maybe set an error flag? - */ -} - -/* - * The LPTIM interrupt handler. - */ -//OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { - - /* Note: - * STM32F4 vectors defined by Chibios currently stop at 98. - * Need to allocate more space in vector table for LPTIM1. - * LPTIM1 is vector 97. Vector table is expanded in increments of 8. - * Change CORTEX_NUM_PARAMS in cmparams.h to 106. - */ - //OSAL_IRQ_PROLOGUE(); - /* Reset interrupt flag for ARR. */ - //LPTIM1->ICR = LPTIM_ICR_ARRMCF; - /* - * LPTIM interrupts can be disabled at this stage. - * We don't need this interrupt again until a new capture is started. - */ - //LPTIM1->IER &= ~LPTIM_IER_ARRMIE; - - /* - * The first interrupt indicates LPTIM core has been initialized by PCLK. - * This flag is used to synchronise capture start. - * If on leading edge of VSYNC lptim_rdy is true then capture can start. - * If not wait for the next VSYNC. - * This is needed because of LPTIM core setup requirement when clocked externally. - */ - //LptimRdy = true; - - //OSAL_IRQ_EPILOGUE(); -//} - -/* - * Note: VSYNC is a pulse at the start of each frame. - * This is unlike the OV2640 where VSYNC is active for the entire frame. -*/ -CH_IRQ_HANDLER(Vector5C) { - CH_IRQ_PROLOGUE(); - - //if (LptimRdy) { - // VSYNC handling - if(!vsync) { - /* - * Rising edge of VSYNC after LPTIM1 has been initialised. - * Start DMA channel. - * Enable TIM1 trigger of DMA. - */ - dma_start(); - TIM8->DIER |= TIM_DIER_CC1DE; - vsync = true; - } else { - /* VSYNC leading with vsync true. - * This means end of capture for the frame. - * Stop & release the DMA channel. - * Disable TIM1 trigger of DMA and stop PCLK counting on LPTIM1. - * If buffer was filled in DMA then that is an error. - * We check that here. - */ - dma_stop(); - TIM8->DIER &= ~TIM_DIER_CC1DE; - TIM8->CCER &= ~TIM_CCER_CC1E; - //LPTIM8->CR &= ~LPTIM_CR_CNTSTRT; - - /* - * Disable VSYNC edge interrupts. - * Flag image capture complete. - */ - nvicDisableVector(EXTI1_IRQn); - capture_finished = true; - } - //} else { - /* - * LPTIM1 is not yet initialised. - * So we enable LPTIM1 to start counting. - */ - //LPTIM1->CR |= LPTIM_CR_CNTSTRT; - //} - - EXTI->PR |= EXTI_PR_PR1; - CH_IRQ_EPILOGUE(); -} - -bool OV5640_Capture(void) -{ - /* - * Note: - * If there are no Chibios devices enabled that use DMA then... - * In makefile add entry to UDEFS: - * UDEFS = -DSTM32_DMA_REQUIRED - */ - - /* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ - dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 2)); - uint32_t dmamode = STM32_DMA_CR_CHSEL(7) | - STM32_DMA_CR_PL(3) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_WORD | - STM32_DMA_CR_MBURST_INCR4 | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - - dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); - - dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here - dmaStreamSetMemory0(dmastp, ov5640_conf->ram_buffer); // Thats the buffer address - dmaStreamSetTransactionSize(dmastp, ov5640_conf->ram_size); // Thats the buffer size - - dmaStreamSetMode(dmastp, dmamode); // Setup DMA - dmaStreamSetFIFO(dmastp, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); - dmaStreamClearInterrupt(dmastp); - - dma_overrun = false; - dma_fault = false; - - // Setup timer for PCLK - //rccResetLPTIM1(); - //rccEnableLPTIM1(FALSE); - - /* - * LPTIM1 is run in external count mode (CKSEL = 0, COUNTMODE = 1). - * CKPOL is set so leading and trailing edge of PCLK increment the counter. - * The internal clocking (checking edges of LPTIM1_IN) is set to use APB. - * The internal clock must be >4 times the frequency of the input (PCLK). - * NOTE: This does not guarantee that LPTIM1_OUT is coincident with PCLK. - * Depending on PCLK state when LPTIM1 is enabled, LPMTIM1_OUT be inverted. - * - * Possible fix... - * Using CKSEL = 1 where PCLK is the actual clock may still be possible. - * This would ensure coincidence between LPTIM1_OUT and PCLK. - * If using CKSEL = 1 LPTIM1 needs 5 external clocks to reach kernel ready. - * Using CKSEL = 1 only allows for leading or trailing edge counting. - * Thus we would be sure which edge of PCLK incremented the LPTIM1 counter. - * Have to test to see if CMP and ARR interrupts work when CKSEL = 1. - * - * Continuing... - * LPTIM1 is enabled on the leading edge of VSYNC. - * After enabling LPTIM1 wait for the first interrupt (ARRIF). - * Waiting for ARRIF indicates that LPTIM1 kernel is ready. - * Note that waiting for interrupt when using COUNTMODE is redundant. - * The ST RM says a delay of only 2 counter (APB) clocks are required. - * But leave the interrupt check in place for now as it does no harm. - * - * The interrupt must be disabled on the first interrupt (else flood). - * - * LPTIM1_OUT is gated to TIM1 internal trigger input 2. - */ - //LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL); - //LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; - //LPTIM1->CR |= LPTIM_CR_ENABLE; - //LPTIM1->IER |= LPTIM_IER_ARRMIE; - - /* - * TODO: When using COUNTMODE CMP and ARR should be 1 & 2? - * It is intended that after counter start CNT = 0. - * Then CNT reaches 1 on first PCLK edge and 2 on the second edge. - * Using 0 and 1 means LPTIM1_OUT gets CMP match as soon as LPMTIM1 is ready. - * This means LPTIM1_OUT will be set and TIM1 will be triggered immediately. - * A DMA transfer will then occur. - * The next edge of PCLK will make CNT = 2 and ARR will match. - * LPTIM1 will then be reset (synchronous with APB presumably). - * LPTIM1_OUT will clear briefly prior to setting again on reset CMP match. - * This will allow TIM1 to be re-triggered. - */ - //LPTIM1->CMP = 0; - //LPTIM1->ARR = 1; - - /* Set vector and clear flag. */ - //nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt - //LptimRdy = false; - - /* - * Setup slave timer to trigger DMA. - * We have to use TIM1 because... - * > it can be triggered from LPTIM1 - * > and TIM1_TRIG is in DMA2 and we need DMA2 for peripheral -> memory transfer - */ - rccEnableTIM8(FALSE); - rccResetTIM8(); - - /* - * TIM1_IC1 is mapped to TRC which means we are in trigger input mode. - * TIM1 is set in slave reset mode with input from ITR2. - * The timer will reset and trigger DMA on the leading edge of LPTIM1_OUT. - * The counter will count up while LPTIM1_OUT is high. - * We don't care about the count. - * We simply use the DMA initiated by the trigger input. - */ - //TIM8->SMCR = TIM_SMCR_TS_1; - //TIM8->SMCR |= TIM_SMCR_SMS_2; - TIM8->CCMR1 |= (TIM_CCMR1_CC1S_0/* | TIM_CCMR1_CC1S_1*/); - TIM8->CCER = TIM_CCER_CC1E; - - capture_finished = false; - capture_error = false; - vsync = false; - - // Setup EXTI: EXTI1 PC for PC1 (VSYNC) and EXIT2 PC for PC2 (HREF) - SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC; - EXTI->IMR = EXTI_IMR_MR1; // Activate interrupt for chan1 (=>PC1) and chan2 (=>PC2) - EXTI->RTSR = EXTI_RTSR_TR1; // Listen on rising edge - nvicEnableVector(EXTI1_IRQn, 1); // Enable interrupt - - do { // Have a look for some bytes in memory for testing if capturing works - TRACE_INFO("CAM > Capturing..."); - chThdSleepMilliseconds(1000); - } while(!capture_finished && !capture_error); - - if (capture_error) { - TRACE_ERROR("CAM > Error capturing image"); - return false; - } - - TRACE_INFO("CAM > Capture finished"); - - return true; -} - - - -/** - * Initializes GPIO (for pseudo DCMI) - * The high speed clock supports communication by I2C (XCLK = 16MHz) - */ -void OV5640_InitGPIO(void) -{ - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - /* PC6 AF3 = TIM8_CH1. */ - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0)); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPadMode(GPIOB, 15, PAL_MODE_INPUT_PULLUP); - palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(3)); -} - -void OV5640_TransmitConfig(void) -{ - chThdSleepMilliseconds(1000); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3103, 0x11); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3008, 0x82); - chThdSleepMilliseconds(100); - - for(uint32_t i=0; (OV5640YUV_Sensor_Dvp_Init[i].reg != 0xffff) || (OV5640YUV_Sensor_Dvp_Init[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640YUV_Sensor_Dvp_Init[i].reg, OV5640YUV_Sensor_Dvp_Init[i].val); - - chThdSleepMilliseconds(500); - - for(uint32_t i=0; (OV5640_JPEG_QSXGA[i].reg != 0xffff) || (OV5640_JPEG_QSXGA[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_JPEG_QSXGA[i].reg, OV5640_JPEG_QSXGA[i].val); - - - switch(ov5640_conf->res) { - case RES_QVGA: - for(uint32_t i=0; (OV5640_QSXGA2QVGA[i].reg != 0xffff) || (OV5640_QSXGA2QVGA[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2QVGA[i].reg, OV5640_QSXGA2QVGA[i].val); - break; - - case RES_VGA: - for(uint32_t i=0; (OV5640_QSXGA2VGA[i].reg != 0xffff) || (OV5640_QSXGA2VGA[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2VGA[i].reg, OV5640_QSXGA2VGA[i].val); - break; - - case RES_XGA: - for(uint32_t i=0; (OV5640_QSXGA2XGA[i].reg != 0xffff) || (OV5640_QSXGA2XGA[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2XGA[i].reg, OV5640_QSXGA2XGA[i].val); - break; - - case RES_UXGA: - for(uint32_t i=0; (OV5640_QSXGA2UXGA[i].reg != 0xffff) || (OV5640_QSXGA2UXGA[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2UXGA[i].reg, OV5640_QSXGA2UXGA[i].val); - break; - - default: // Default QVGA - for(uint32_t i=0; (OV5640_QSXGA2QVGA[i].reg != 0xffff) || (OV5640_QSXGA2QVGA[i].val != 0xff); i++) - I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2QVGA[i].reg, OV5640_QSXGA2QVGA[i].val); - } - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x4407, 0x04); // Quantization scale - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x03); // start group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3406, 0x00); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3400, 0x04); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3401, 0x00); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3402, 0x04); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3403, 0x00); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3404, 0x04); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3405, 0x00); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x13); // end group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0xa3); // lanuch group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5183 ,0x0 ); - - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x03); // start group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5381, 0x1c); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5382, 0x5a); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5383, 0x06); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5384, 0x1a); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5385, 0x66); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5386, 0x80); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5387, 0x82); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5388, 0x80); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5389, 0x02); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x538b, 0x98); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x538a, 0x01); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x13); // end group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0xa3); // launch group 3 - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x03); // start group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5587, 0x00); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5588, 0x01); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x13); // end group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0xa3); // launch group 3 - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x03); // start group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x03); // start group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5586, 0x20); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5585, 0x00); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x13); // end group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0xa3); // launch group 3 - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x03); // start group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5580, 0x06); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5583, 0x40); // sat U - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5584, 0x10); // sat V - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x5003, 0x08); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0x13); // end group 3 - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3212, 0xa3); // launch group - - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3a0f, 0x38); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3a10, 0x30); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3a11, 0x61); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3a1b, 0x38); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3a1e, 0x30); - I2C_write8_16bitreg(OV5640_I2C_ADR, 0x3a1f, 0x10); -} - -void OV5640_init(ssdv_conf_t *config) { - ov5640_conf = config; - - // Clearing buffer - uint32_t i; - for(i=0; iram_size; i++) - ov5640_conf->ram_buffer[i] = 0; - - TRACE_INFO("CAM > Init pins"); - OV5640_InitGPIO(); - - // Power on OV5640 - TRACE_INFO("CAM > Switch on"); - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - // Send settings to OV5640 - TRACE_INFO("CAM > Transmit config to camera"); - OV5640_TransmitConfig(); - - chThdSleepMilliseconds(3000); -} - -void OV5640_deinit(void) { - // Power off OV5640 - TRACE_INFO("CAM > Switch off"); - - palSetLineMode(LINE_CAM_HREF, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_PCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_XCLK, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT); - - palSetLineMode(LINE_CAM_EN, PAL_MODE_INPUT); - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); -} - -bool OV5640_isAvailable(void) -{ - // Configure pins - OV5640_InitGPIO(); - - // Switch on camera - palSetLine(LINE_CAM_EN); // Switch on camera - palSetLine(LINE_CAM_RESET); // Toggle reset - - chThdSleepMilliseconds(100); - - uint8_t val, val2; - bool ret; - - if(I2C_read8_16bitreg(OV5640_I2C_ADR, 0x300A, &val) && I2C_read8_16bitreg(OV5640_I2C_ADR, 0x300B, &val2)) { - ret = val == 0x56 && val2 == 0x40; - } else { - ret = false; - } - - palClearLine(LINE_CAM_EN); // Switch off camera - palSetLineMode(LINE_CAM_RESET, PAL_MODE_INPUT); // CAM_RESET - - return ret; -} -