kopia lustrzana https://github.com/DL7AD/pecanpico9
Reduced clocking speed
rodzic
35f7164a7d
commit
a7e9147ed3
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@ -31,7 +31,7 @@ static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] =
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{ 0x3017, 0x7f },
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{ 0x3018, 0xff },
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{ 0x302c, 0x02 },
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{ 0x3108, 0x01 },
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{ 0x3108, 0x31 },
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{ 0x3630, 0x2e },//2e
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{ 0x3632, 0xe2 },
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{ 0x3633, 0x23 },//23
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@ -396,7 +396,7 @@ static const struct regval_list OV5640_RGB_QVGA[] =
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//2592x1944 QSXGA
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static const struct regval_list OV5640_JPEG_QSXGA[] =
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{
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{0x3820 ,0x40},
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{0x3820 ,0x41},
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{0x3821 ,0x26},
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{0x3814 ,0x11},
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{0x3815 ,0x11},
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@ -796,13 +796,12 @@ static void dma_interrupt(void *p, uint32_t flags) {
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* In single buffer mode DMA should always be terminated by VSYNC.
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*
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* Stop PCLK from LPTIM1 and disable TIM1 DMA trigger.
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* Wait for next VSYNC leading edge to tear down DMA stream.
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* Dont stop the DMA here. Its going to be stopped by the leading edge of VSYNC.
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*/
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TIM1->DIER &= ~TIM_DIER_TDE;
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LPTIM1->CR &= ~LPTIM_CR_CNTSTRT;
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dma_overrun = true;
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capture_error = true;
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//dma_stop();
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return;
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}
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/*
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@ -811,24 +810,6 @@ static void dma_interrupt(void *p, uint32_t flags) {
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*/
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}
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/*
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* The TIM1 interrupt handler (to be deprecated - not used).
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*/
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/* Not defined by Chibios. */
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#define STM32_TIM1_TRG_HANDLER VectorA8
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#define STM32_TIM1_UP_NUMBER 25
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OSAL_IRQ_HANDLER(STM32_TIM1_TRG_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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TIM1->SR &= ~TIM_SR_TIF;
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OSAL_IRQ_EPILOGUE();
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}
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/*
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* The LPTIM interrupt handler.
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*/
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@ -897,7 +878,6 @@ CH_IRQ_HANDLER(Vector5C) {
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*/
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nvicDisableVector(EXTI1_IRQn);
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capture_finished = true;
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//vsync = false;
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}
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} else {
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/*
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@ -921,8 +901,8 @@ bool OV5640_Capture(void)
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*/
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/* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */
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dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0));
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uint32_t dmamode = STM32_DMA_CR_CHSEL(6) |
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dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0));
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uint32_t dmamode = STM32_DMA_CR_CHSEL(6) |
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STM32_DMA_CR_PL(3) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_WORD |
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@ -978,7 +958,7 @@ bool OV5640_Capture(void)
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*
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* LPTIM1_OUT is gated to TIM1 internal trigger input 2.
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*/
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LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1);
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LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL);
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LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP;
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LPTIM1->CR |= LPTIM_CR_ENABLE;
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LPTIM1->IER |= LPTIM_IER_ARRMIE;
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@ -46,7 +46,7 @@
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 26
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#define STM32_PLLN_VALUE 192
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLQ_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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