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Add DMA DBM as multi-buffer handling for OV5640

Develop
CInsights 2017-08-21 21:23:55 +10:00
rodzic 685d4c9165
commit 61defb05aa
4 zmienionych plików z 468 dodań i 342 usunięć
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3
tracker/software/Makefile
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@ -10,7 +10,7 @@ endif
# C specific options here (added to USE_OPT). # C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),) ifeq ($(USE_COPT),)
USE_COPT = USE_COPT = -std=c11
endif endif
# C++ specific options here (added to USE_OPT). # C++ specific options here (added to USE_OPT).
@ -87,6 +87,7 @@ PROJECT = ch
# Imported source files and paths # Imported source files and paths
CHIBIOS = ChibiOS CHIBIOS = ChibiOS
#CHIBIOS = C:\ChibiStudio\chibios_trunk
# Startup files. # Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
# HAL-OSAL files (optional). # HAL-OSAL files (optional).

2
tracker/software/config.c
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@ -3,7 +3,7 @@
#include "debug.h" #include "debug.h"
module_conf_t config[9]; module_conf_t config[9];
uint8_t ssdv_buffer[65535] __attribute__((aligned(1024))); uint8_t ssdv_buffer[65535] __attribute__((aligned(32)));
/* /*
* Position module configuration description * Position module configuration description

287
tracker/software/drivers/ov5640.c
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@ -799,6 +799,31 @@ uint32_t OV5640_getBuffer(uint8_t** buffer) {
const stm32_dma_stream_t *dmastp; const stm32_dma_stream_t *dmastp;
#if OV5640_USE_DMA_DBM == TRUE
uint16_t dma_index;
uint16_t dma_buffers;
#define DMA_SEGMENT_SIZE 1024
#define DMA_FIFO_BURST_ALIGN 32
#if !defined(dmaStreamGetCurrentTarget)
/**
* @brief Get DMA stream current target.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @return Current target index
*
* @special
*/
#define dmaStreamGetCurrentTarget(dmastp) \
((uint8_t)(((dmastp)->stream->CR >> DMA_SxCR_CT_Pos) & 1U))
#endif /* !defined(dmaStreamGetCurrentTarget) */
#endif /* OV5640_USE_DMA_DBM == TRUE */
inline int32_t dma_start(void) { inline int32_t dma_start(void) {
/* Clear any pending interrupts. */ /* Clear any pending interrupts. */
dmaStreamClearInterrupt(dmastp); dmaStreamClearInterrupt(dmastp);
@ -818,50 +843,126 @@ inline uint16_t dma_stop(void) {
return transfer; return transfer;
} }
#if OV5640_USE_DMA_DBM == TRUE
static void dma_interrupt(void *p, uint32_t flags) { static void dma_interrupt(void *p, uint32_t flags) {
(void)p; /* No parameter passed. */
(void)p;
if ((flags & STM32_DMA_ISR_HTIF) != 0) { if (flags & (STM32_DMA_ISR_FEIF | STM32_DMA_ISR_TEIF)) {
/* /*
* Nothing really to do at half way point for now. * DMA transfer error or FIFO error.
* Implementing DBM will use HTIF. * See 9.34.19 of RM0430.
*/ */
return; dmaStreamClearInterrupt(dmastp);
} TIM1->DIER &= ~TIM_DIER_TDE;
if ((flags & STM32_DMA_ISR_TCIF) != 0) { dma_fault = true;
/* Disable VYSNC edge interrupts. */ capture_error = true;
//nvicDisableVector(EXTI1_IRQn); return;
//capture_finished = true; }
/* if (flags & STM32_DMA_ISR_HTIF) {
* If DMA has run to end within a frame then this is an error. /*
* In single buffer mode DMA should always be terminated by VSYNC. * Half transfer complete.
* * Check if DMA is writing to the last buffer.
* Stop PCLK from LPTIM1 and disable TIM1 DMA trigger. */
* Dont stop the DMA here. Its going to be stopped by the leading edge of VSYNC. if (dma_index == (dma_buffers - 1)) {
*/ /*
TIM1->DIER &= ~TIM_DIER_TDE; * This is the last buffer so we have to terminate DMA.
LPTIM1->CR &= ~LPTIM_CR_CNTSTRT; * The DBM switch is done in h/w.
dma_overrun = true; * DMA could write beyond total buffer if not stopped.
capture_error = true; *
return; * Because we have run to last DMA buffer this is treated as an error.
} * The DMA should normally be terminated by VSYNC before last buffer.
/* * Stop DMA and TIM DMA trigger and flag error.
* TODO: Anything else is an error. */
* Maybe set an error flag?
*/ dmaStreamClearInterrupt(dmastp);
TIM1->DIER &= ~TIM_DIER_TDE;
dma_overrun = true;
capture_error = true;
return;
}
/*
* Else Safe to allow buffer to fill.
* DMA DBM will switch buffers in h/w when this one is full.
* Just clear the interrupt and wait for TCIF.
*/
dmaStreamClearInterrupt(dmastp);
return;
}
if (flags & STM32_DMA_ISR_TCIF) {
/*
* Full buffer transfer complete.
* Update non-active memory address register.
* DMA will use new address at h/w DBM switch.
*/
dmaStreamClearInterrupt(dmastp);
if (dmaStreamGetCurrentTarget(dmastp) == 1) {
dmaStreamSetMemory0(dmastp, &ov5640_conf->ram_buffer[++dma_index * DMA_SEGMENT_SIZE]);
} else {
dmaStreamSetMemory1(dmastp, &ov5640_conf->ram_buffer[++dma_index * DMA_SEGMENT_SIZE]);
}
return;
}
} }
#else
static void dma_interrupt(void *p, uint32_t flags) {
(void)p;
if (flags & (STM32_DMA_ISR_FEIF | STM32_DMA_ISR_TEIF)) {
/*
* DMA transfer error or FIFO error.
* See 9.34.19 of RM0430.
*/
dmaStreamClearInterrupt(dmastp);
TIM1->DIER &= ~TIM_DIER_TDE;
dma_fault = true;
capture_error = true;
return;
}
if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/*
* Nothing really to do at half way point for now.
* Implementing DBM will use HTIF.
*/
return;
}
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Disable VYSNC edge interrupts. */
//nvicDisableVector(EXTI1_IRQn);
//capture_finished = true;
/*
* If DMA has run to end within a frame then this is an error.
* In single buffer mode DMA should always be terminated by VSYNC.
*
* Stop PCLK from LPTIM1 and disable TIM1 DMA trigger.
* Dont stop the DMA here. Its going to be stopped by the leading edge of VSYNC.
*/
TIM1->DIER &= ~TIM_DIER_TDE;
LPTIM1->CR &= ~LPTIM_CR_CNTSTRT;
dma_overrun = true;
capture_error = true;
return;
}
}
#endif /* USE_OV5640_DMA_DBM */
/* /*
* The LPTIM interrupt handler. * The LPTIM interrupt handler.
*/ */
OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) { OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) {
/* Note: /* Note:
* STM32F4 vectors defined by Chibios currently stop at 98. * LPTIM1 is vector 97.
* Need to allocate more space in vector table for LPTIM1. * Check CORTEX_NUM_PARAMS in cmparams.h >= 106.
* LPTIM1 is vector 97. Vector table is expanded in increments of 8. * Vector table is expanded in increments of 8.
* Change CORTEX_NUM_PARAMS in cmparams.h to 106.
*/ */
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
/* Reset interrupt flag for ARR. */ /* Reset interrupt flag for ARR. */
@ -885,9 +986,9 @@ OSAL_IRQ_HANDLER(STM32_LPTIM1_HANDLER) {
} }
/* /*
* Note: VSYNC is a pulse at the start of each frame. * VSYNC is asserted during a frame.
* This is unlike the OV2640 where VSYNC is active for the entire frame. * See OV5640 datasheet for details.
*/ */
CH_IRQ_HANDLER(Vector5C) { CH_IRQ_HANDLER(Vector5C) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -953,70 +1054,92 @@ bool OV5640_Capture(void)
STM32_DMA_CR_MINC | STM32_DMA_CR_MINC |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE | STM32_DMA_CR_TEIE |
#if OV5640_USE_DMA_DBM == TRUE
STM32_DMA_CR_DBM |
#endif
STM32_DMA_CR_TCIE; STM32_DMA_CR_TCIE;
dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL); dmaStreamAllocate(dmastp, 2, (stm32_dmaisr_t)dma_interrupt, NULL);
dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here dmaStreamSetPeripheral(dmastp, &GPIOA->IDR); // We want to read the data from here
dmaStreamSetMemory0(dmastp, ov5640_conf->ram_buffer); // Thats the buffer address #if OV5640_USE_DMA_DBM == TRUE
dmaStreamSetTransactionSize(dmastp, ov5640_conf->ram_size); // Thats the buffer size /*
* Buffer address must be word aligned.
* Also note requirement for burst transfers from FIFO.
* Bursts from FIFO to memory must not cross a 1K address boundary.
* See RM0430 9.3.12
*
* TODO: To use DMA_FIFO_BURST_ALIGN in setting of ssdv buffer alignment.
* Currently this is set to 32 manually in config.c.
*/
dmaStreamSetMode(dmastp, dmamode); // Setup DMA if (((uint32_t)ov5640_conf->ram_buffer % DMA_FIFO_BURST_ALIGN) != 0)
dmaStreamSetFIFO(dmastp, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); return false;
dmaStreamClearInterrupt(dmastp);
dma_overrun = false; /*
dma_fault = false; * Set the initial buffer addresses.
* The updating of DMA:MxAR is done in the the DMA interrupt function.
*/
dmaStreamSetMemory0(dmastp, &ov5640_conf->ram_buffer[0]);
dmaStreamSetMemory1(dmastp, &ov5640_conf->ram_buffer[DMA_SEGMENT_SIZE]);
/*
* Calculate the number of whole buffers.
* TODO: Make this include remainder memory as partial buffer?
*/
dma_buffers = (ov5640_conf->ram_size / DMA_SEGMENT_SIZE);
if (dma_buffers == 0)
return false;
/* Start with buffer index 0. */
dma_index = 0;
#else
dmaStreamSetMemory0(dmastp, ov5640_conf->ram_buffer); // Thats the buffer address
dmaStreamSetTransactionSize(dmastp, ov5640_conf->ram_size); // Thats the buffer size
#endif
dmaStreamSetMode(dmastp, dmamode); // Setup DMA
dmaStreamSetFIFO(dmastp, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL \
| STM32_DMA_FCR_FEIE);
dmaStreamClearInterrupt(dmastp);
dma_overrun = false;
dma_fault = false;
// Setup timer for PCLK // Setup timer for PCLK
rccResetLPTIM1(); rccResetLPTIM1();
rccEnableLPTIM1(FALSE); rccEnableLPTIM1(FALSE);
/* /*
* LPTIM1 is run in external count mode (CKSEL = 0, COUNTMODE = 1). * LPTIM1 is run in external count mode (CKSEL = 0, COUNTMODE = 1).
* CKPOL is set so leading and trailing edge of PCLK increment the counter. * CKPOL is set so leading and trailing edge of PCLK increment the counter.
* The internal clocking (checking edges of LPTIM1_IN) is set to use APB. * The internal clocking (checking edges of LPTIM1_IN) is set to use APB.
* The internal clock must be >4 times the frequency of the input (PCLK). * The internal clock must be >4 times the frequency of the input (PCLK).
* NOTE: This does not guarantee that LPTIM1_OUT is coincident with PCLK. * NOTE: This does not guarantee that LPTIM1_OUT is coincident with PCLK.
* Depending on PCLK state when LPTIM1 is enabled, LPMTIM1_OUT be inverted. * Depending on PCLK state when LPTIM1 is enabled OUT may get inverted.
*
* Possible fix...
* Using CKSEL = 1 where PCLK is the actual clock may still be possible.
* This would ensure coincidence between LPTIM1_OUT and PCLK.
* If using CKSEL = 1 LPTIM1 needs 5 external clocks to reach kernel ready.
* Using CKSEL = 1 only allows for leading or trailing edge counting.
* Thus we would be sure which edge of PCLK incremented the LPTIM1 counter.
* Have to test to see if CMP and ARR interrupts work when CKSEL = 1.
* *
* Continuing... * LPTIM1 is enabled on the VSYNC edge interrupt.
* LPTIM1 is enabled on the leading edge of VSYNC. * After enabling LPTIM1 wait for the first interrupt (ARRIF).
* After enabling LPTIM1 wait for the first interrupt (ARRIF). * The interrupt must be disabled on the first interrupt (else flood).
* Waiting for ARRIF indicates that LPTIM1 kernel is ready. *
* Note that waiting for interrupt when using COUNTMODE is redundant. * LPTIM1_OUT is gated to TIM1 internal trigger input 2.
* The ST RM says a delay of only 2 counter (APB) clocks are required. */
* But leave the interrupt check in place for now as it does no harm.
*
* The interrupt must be disabled on the first interrupt (else flood).
*
* LPTIM1_OUT is gated to TIM1 internal trigger input 2.
*/
LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL); LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL);
LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP; LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP;
LPTIM1->CR |= LPTIM_CR_ENABLE; LPTIM1->CR |= LPTIM_CR_ENABLE;
LPTIM1->IER |= LPTIM_IER_ARRMIE; LPTIM1->IER |= LPTIM_IER_ARRMIE;
/* /*
* TODO: When using COUNTMODE CMP and ARR should be 1 & 2? * When LPTIM1 is enabled and ready LPTIM1_OUT will be not set.
* It is intended that after counter start CNT = 0. * WAVPOL inverts LPTIM1_OUT so it is not set.
* Then CNT reaches 1 on first PCLK edge and 2 on the second edge. * On the next PCLK edge LPTIM1 will count and match ARR.
* Using 0 and 1 means LPTIM1_OUT gets CMP match as soon as LPMTIM1 is ready. * LPTIM1_OUT will set briefly and then clear again due ARR match.
* This means LPTIM1_OUT will be set and TIM1 will be triggered immediately. * This triggers TIM1 with the short pulse from LPTIM1_OUT.
* A DMA transfer will then occur. * TODO:
* The next edge of PCLK will make CNT = 2 and ARR will match. * This use of LPTIM1 works probably by good luck for now.
* LPTIM1 will then be reset (synchronous with APB presumably). * Switch to direct triggering of TIM using Capture input is better.
* LPTIM1_OUT will clear briefly prior to setting again on reset CMP match. * Requires a PCB change.
* This will allow TIM1 to be re-triggered. */
*/
LPTIM1->CMP = 0; LPTIM1->CMP = 0;
LPTIM1->ARR = 1; LPTIM1->ARR = 1;

2
tracker/software/drivers/ov5640.h
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@ -9,6 +9,8 @@
#include "hal.h" #include "hal.h"
#include "types.h" #include "types.h"
#define OV5640_USE_DMA_DBM TRUE
bool OV5640_Snapshot2RAM(void); bool OV5640_Snapshot2RAM(void);
bool OV5640_Capture(void); bool OV5640_Capture(void);
void OV5640_InitGPIO(void); void OV5640_InitGPIO(void);