kopia lustrzana https://github.com/DL7AD/pecanpico9
				
				
				
			Finalized clockling (so far) for power savings.
All dividers for all clocks are static except for HPRE. HPRE is dynamically changed between /1 and /8. It is usually set to /8. If the camera is capturing the image, it is set to /1. This is necessary while the sampling method needs a to sample the fast data from the camera. After capture, the prescaler is switched back to /8. HPRE will affect the speed of AHB1 and AHB2. Both have the same speed. At image capture, both are running at 48Mhz and 6Mhz at all other times. The clock change has a drastic effect of the power consumption. -------------------------------------------------- Running at 1.8V Position packet transmission, APRS AFSK, one packet every 1min (GPS off) Image transmission, APRS AFSK, one packet every 20sec, redundant TX => average consumption 55mW -------------------------------------------------- Running at 1.8V Position packet transmission, APRS AFSK, one packet every 1min (GPS off) => average consumption 34mWDevelop
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				|  | @ -250,7 +250,7 @@ void start_user_modules(void) | ||||||
| 	config[3].ssdv_conf.ram_size = sizeof(ssdv_buffer);		// Buffer size
 | 	config[3].ssdv_conf.ram_size = sizeof(ssdv_buffer);		// Buffer size
 | ||||||
| 	config[3].ssdv_conf.res = RES_QVGA;						// Resolution VGA
 | 	config[3].ssdv_conf.res = RES_QVGA;						// Resolution VGA
 | ||||||
| 	config[3].ssdv_conf.redundantTx = true;					// Transmit packets twice
 | 	config[3].ssdv_conf.redundantTx = true;					// Transmit packets twice
 | ||||||
| 	start_image_thread(&config[3]); | 	//start_image_thread(&config[3]);
 | ||||||
| 
 | 
 | ||||||
| 	// Module POSITION, Morse 2m OOK
 | 	// Module POSITION, Morse 2m OOK
 | ||||||
| 	/*config[4].power = 127;								// Power 10 dBm
 | 	/*config[4].power = 127;								// Power 10 dBm
 | ||||||
|  |  | ||||||
|  | @ -10,7 +10,7 @@ | ||||||
| 
 | 
 | ||||||
| #define TRACK_CYCLE_TIME		60			/* Tracking cycle (all peripheral data [airpressure, GPS, temperature, ...] is collected each x seconds */ | #define TRACK_CYCLE_TIME		60			/* Tracking cycle (all peripheral data [airpressure, GPS, temperature, ...] is collected each x seconds */ | ||||||
| 
 | 
 | ||||||
| #define LOG_CYCLE_TIME			30			/* Log cycle time in seconds */ | #define LOG_CYCLE_TIME			60			/* Log cycle time in seconds */ | ||||||
| #define LOG_FLASH_ADDR1			0x080C0000	/* Log flash memory address 1 */ | #define LOG_FLASH_ADDR1			0x080C0000	/* Log flash memory address 1 */ | ||||||
| #define LOG_FLASH_ADDR2			0x080E0000	/* Log flash memory address 2 */ | #define LOG_FLASH_ADDR2			0x080E0000	/* Log flash memory address 2 */ | ||||||
| #define LOG_SECTOR_SIZE			0x20000		/* Log flash memory size */ | #define LOG_SECTOR_SIZE			0x20000		/* Log flash memory size */ | ||||||
|  | @ -21,7 +21,7 @@ | ||||||
| #define TRACE_TIME				TRUE		/* Enables time tracing on debugging port */ | #define TRACE_TIME				TRUE		/* Enables time tracing on debugging port */ | ||||||
| #define TRACE_FILE				FALSE		/* Enables file and line tracing on debugging port */ | #define TRACE_FILE				FALSE		/* Enables file and line tracing on debugging port */ | ||||||
| 
 | 
 | ||||||
| #define RUN_3V					TRUE		/* Lets the tracker run a 3V otherwise 1.8V. 3V is needed to do 20dBm radio output power. | #define RUN_3V					FALSE		/* Lets the tracker run a 3V otherwise 1.8V. 3V is needed to do 20dBm radio output power. | ||||||
| 											 * With 1.8V only 15dBm can be done. Some serial-USB adapters also need a 3V IO level in | 											 * With 1.8V only 15dBm can be done. Some serial-USB adapters also need a 3V IO level in | ||||||
| 											 * order to work. However 3V takes a lot of power in idle. You can save energy using 1.8V. */ | 											 * order to work. However 3V takes a lot of power in idle. You can save energy using 1.8V. */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -96,7 +96,7 @@ static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] = | ||||||
| 	{ 0x3034, 0x1a },  | 	{ 0x3034, 0x1a },  | ||||||
| 	{ 0x3035, 0x11 }, //15fps
 | 	{ 0x3035, 0x11 }, //15fps
 | ||||||
| 	{ 0x3036, 0x46 },  | 	{ 0x3036, 0x46 },  | ||||||
| 	{ 0x3037, 0x14 },  | 	{ 0x3037, 0x12 },  | ||||||
| 	{ 0x3038, 0x00 },  | 	{ 0x3038, 0x00 },  | ||||||
| 	{ 0x3039, 0x00 },  | 	{ 0x3039, 0x00 },  | ||||||
| 
 | 
 | ||||||
|  | @ -993,6 +993,15 @@ CH_IRQ_HANDLER(Vector5C) { | ||||||
| 	if (LptimRdy) { | 	if (LptimRdy) { | ||||||
| 		// VSYNC handling
 | 		// VSYNC handling
 | ||||||
| 		if(!vsync) { | 		if(!vsync) { | ||||||
|  | 			// Increase AHB clock to 6 MHz
 | ||||||
|  | 			uint32_t new = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | FLASH_ACR_LATENCY_3WS; | ||||||
|  | 			FLASH->ACR = new; | ||||||
|  | 			while(FLASH->ACR != new); | ||||||
|  | 
 | ||||||
|  | 			new = (RCC->CFGR & ~RCC_CFGR_HPRE_Msk) | RCC_CFGR_HPRE_DIV1; | ||||||
|  | 			RCC->CFGR = new; | ||||||
|  | 			while(RCC->CFGR != new); | ||||||
|  | 
 | ||||||
| 			/*
 | 			/*
 | ||||||
| 			 * Rising edge of VSYNC after LPTIM1 has been initialised. | 			 * Rising edge of VSYNC after LPTIM1 has been initialised. | ||||||
| 			 * Start DMA channel. | 			 * Start DMA channel. | ||||||
|  | @ -1002,6 +1011,15 @@ CH_IRQ_HANDLER(Vector5C) { | ||||||
| 			TIM1->DIER |= TIM_DIER_TDE; | 			TIM1->DIER |= TIM_DIER_TDE; | ||||||
| 			vsync = true; | 			vsync = true; | ||||||
| 		} else { | 		} else { | ||||||
|  | 			// Reduce AHB clock to 6 MHz
 | ||||||
|  | 			uint32_t new = (RCC->CFGR & ~RCC_CFGR_HPRE_Msk) | RCC_CFGR_HPRE_DIV8; | ||||||
|  | 			RCC->CFGR = new; | ||||||
|  | 			while(RCC->CFGR != new); | ||||||
|  | 
 | ||||||
|  | 			new = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | FLASH_ACR_LATENCY_0WS; | ||||||
|  | 			FLASH->ACR = new; | ||||||
|  | 			while(FLASH->ACR != new); | ||||||
|  | 
 | ||||||
| 			/* VSYNC leading with vsync true.
 | 			/* VSYNC leading with vsync true.
 | ||||||
| 			 * This means end of capture for the frame. | 			 * This means end of capture for the frame. | ||||||
| 			 * Stop & release the DMA channel. | 			 * Stop & release the DMA channel. | ||||||
|  | @ -1034,12 +1052,12 @@ CH_IRQ_HANDLER(Vector5C) { | ||||||
| 
 | 
 | ||||||
| bool OV5640_Capture(void) | bool OV5640_Capture(void) | ||||||
| { | { | ||||||
|   /*
 | 	/*
 | ||||||
|    * Note: | 	 * Note: | ||||||
|    *  If there are no Chibios devices enabled that use DMA then... | 	 *  If there are no Chibios devices enabled that use DMA then... | ||||||
|    *  In makefile add entry to UDEFS: | 	 *  In makefile add entry to UDEFS: | ||||||
|    *   UDEFS = -DSTM32_DMA_REQUIRED | 	 *   UDEFS = -DSTM32_DMA_REQUIRED | ||||||
|    */ | 	 */ | ||||||
| 
 | 
 | ||||||
| 	/* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ | 	/* Setup DMA for transfer on TIM1_TRIG - DMA2 stream 0, channel 6 */ | ||||||
| 	dmastp  = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); | 	dmastp  = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 0)); | ||||||
|  | @ -1374,8 +1392,6 @@ bool OV5640_isAvailable(void) | ||||||
| 	palSetLine(LINE_CAM_EN); 		// Switch on camera
 | 	palSetLine(LINE_CAM_EN); 		// Switch on camera
 | ||||||
| 	palSetLine(LINE_CAM_RESET); // Toggle reset
 | 	palSetLine(LINE_CAM_RESET); // Toggle reset
 | ||||||
| 
 | 
 | ||||||
| 	OV5640_getLightIntensity(); |  | ||||||
| 
 |  | ||||||
| 	chThdSleepMilliseconds(100); | 	chThdSleepMilliseconds(100); | ||||||
| 
 | 
 | ||||||
| 	uint8_t val, val2; | 	uint8_t val, val2; | ||||||
|  |  | ||||||
|  | @ -50,7 +50,7 @@ | ||||||
| #define STM32_PLLQ_VALUE                    4 | #define STM32_PLLQ_VALUE                    4 | ||||||
| #define STM32_HPRE                          STM32_HPRE_DIV8 | #define STM32_HPRE                          STM32_HPRE_DIV8 | ||||||
| #define STM32_PPRE1                         STM32_PPRE1_DIV1 | #define STM32_PPRE1                         STM32_PPRE1_DIV1 | ||||||
| #define STM32_PPRE2                         STM32_PPRE2_DIV4 | #define STM32_PPRE2                         STM32_PPRE2_DIV1 | ||||||
| #define STM32_RTCSEL                        STM32_RTCSEL_LSI | #define STM32_RTCSEL                        STM32_RTCSEL_LSI | ||||||
| #define STM32_RTCPRE_VALUE                  8 | #define STM32_RTCPRE_VALUE                  8 | ||||||
| #define STM32_MCO1SEL                       STM32_MCO1SEL_HSE | #define STM32_MCO1SEL                       STM32_MCO1SEL_HSE | ||||||
|  |  | ||||||
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