kopia lustrzana https://github.com/DL7AD/pecanpico10
Merge branch 'master' of github.com:DL7AD/pecanpico10
Sven Steudte
commit
aea408f392
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@ -142,115 +142,115 @@ static void Si446x_setProperty32(uint16_t reg, uint8_t val1, uint8_t val2, uint8
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static void Si446x_init(void) {
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TRACE_INFO("SI > Init radio");
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// Configure Radio pins
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palSetLineMode(LINE_SPI_SCK, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // SCK
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palSetLineMode(LINE_SPI_MISO, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // MISO
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palSetLineMode(LINE_SPI_MOSI, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // MOSI
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palSetLineMode(LINE_RADIO_CS, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // RADIO CS
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palSetLineMode(LINE_RADIO_SDN, PAL_MODE_OUTPUT_PUSHPULL); // RADIO SDN
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// Configure Radio pins
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palSetLineMode(LINE_SPI_SCK, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // SCK
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palSetLineMode(LINE_SPI_MISO, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // MISO
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palSetLineMode(LINE_SPI_MOSI, PAL_MODE_ALTERNATE(6) | PAL_STM32_OSPEED_HIGHEST); // MOSI
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palSetLineMode(LINE_RADIO_CS, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // RADIO CS
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palSetLineMode(LINE_RADIO_SDN, PAL_MODE_OUTPUT_PUSHPULL); // RADIO SDN
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// Pull CS HIGH
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palSetLine(LINE_RADIO_CS);
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// Pull CS HIGH
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palSetLine(LINE_RADIO_CS);
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// Reset radio
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palSetLine(LINE_RADIO_SDN);
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chThdSleep(TIME_MS2I(10));
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// Reset radio
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palSetLine(LINE_RADIO_SDN);
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chThdSleep(TIME_MS2I(10));
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// Power up transmitter
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palClearLine(LINE_RADIO_SDN); // Radio SDN low (power up transmitter)
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chThdSleep(TIME_MS2I(10)); // Wait for transmitter to power up
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// Power up transceiver
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palClearLine(LINE_RADIO_SDN); // Radio SDN low (power up transceiver)
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chThdSleep(TIME_MS2I(10)); // Wait for transceiver to power up
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// Power up (transmits oscillator type)
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const uint8_t x3 = (Si446x_CCLK >> 24) & 0x0FF;
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const uint8_t x2 = (Si446x_CCLK >> 16) & 0x0FF;
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const uint8_t x1 = (Si446x_CCLK >> 8) & 0x0FF;
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const uint8_t x0 = (Si446x_CCLK >> 0) & 0x0FF;
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const uint8_t init_command[] = {0x02, 0x01, (Si446x_CLK_TCXO_EN & 0x1), x3, x2, x1, x0};
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Si446x_write(init_command, 7);
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chThdSleep(TIME_MS2I(25));
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// Power up (send oscillator type)
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const uint8_t x3 = (Si446x_CCLK >> 24) & 0x0FF;
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const uint8_t x2 = (Si446x_CCLK >> 16) & 0x0FF;
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const uint8_t x1 = (Si446x_CCLK >> 8) & 0x0FF;
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const uint8_t x0 = (Si446x_CCLK >> 0) & 0x0FF;
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const uint8_t init_command[] = {0x02, 0x01, (Si446x_CLK_TCXO_EN & 0x1), x3, x2, x1, x0};
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Si446x_write(init_command, 7);
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chThdSleep(TIME_MS2I(25));
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// Set transmitter GPIOs
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uint8_t gpio_pin_cfg_command[] = {
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0x13, // Command type = GPIO settings
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0x00, // GPIO0 GPIO_MODE = DONOTHING
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0x14, // GPIO1 GPIO_MODE = RX_DATA
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0x21, // GPIO2 GPIO_MODE = RX_STATE
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0x20, // GPIO3 GPIO_MODE = TX_STATE
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0x1B, // NIRQ NIRQ_MODE = CCA
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0x0B, // SDO SDO_MODE = SDO
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0x00 // GEN_CONFIG
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};
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Si446x_write(gpio_pin_cfg_command, 8);
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chThdSleep(TIME_MS2I(25));
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// Set transceiver GPIOs
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uint8_t gpio_pin_cfg_command[] = {
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0x13, // Command type = GPIO settings
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0x00, // GPIO0 GPIO_MODE = DONOTHING
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0x15, // GPIO1 GPIO_MODE = RAW_RX_DATA
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0x21, // GPIO2 GPIO_MODE = RX_STATE
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0x20, // GPIO3 GPIO_MODE = TX_STATE
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0x1B, // NIRQ NIRQ_MODE = CCA
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0x0B, // SDO SDO_MODE = SDO
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0x00 // GEN_CONFIG
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};
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Si446x_write(gpio_pin_cfg_command, 8);
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chThdSleep(TIME_MS2I(25));
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#if !Si446x_CLK_TCXO_EN
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Si446x_setProperty8(Si446x_GLOBAL_XO_TUNE, 0x00);
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#endif
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#if !Si446x_CLK_TCXO_EN
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Si446x_setProperty8(Si446x_GLOBAL_XO_TUNE, 0x00);
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#endif
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Si446x_setProperty8(Si446x_FRR_CTL_A_MODE, 0x00);
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Si446x_setProperty8(Si446x_FRR_CTL_B_MODE, 0x00);
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Si446x_setProperty8(Si446x_FRR_CTL_C_MODE, 0x00);
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Si446x_setProperty8(Si446x_FRR_CTL_D_MODE, 0x00);
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Si446x_setProperty8(Si446x_INT_CTL_ENABLE, 0x00);
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Si446x_setProperty8(Si446x_GLOBAL_CONFIG, 0x70);
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Si446x_setProperty8(Si446x_FRR_CTL_A_MODE, 0x00);
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Si446x_setProperty8(Si446x_FRR_CTL_B_MODE, 0x00);
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Si446x_setProperty8(Si446x_FRR_CTL_C_MODE, 0x00);
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Si446x_setProperty8(Si446x_FRR_CTL_D_MODE, 0x00);
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Si446x_setProperty8(Si446x_INT_CTL_ENABLE, 0x00);
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Si446x_setProperty8(Si446x_GLOBAL_CONFIG, 0x60);
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// Reset FIFO
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const uint8_t reset_fifo[] = {0x15, 0x01};
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Si446x_write(reset_fifo, 2);
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const uint8_t unreset_fifo[] = {0x15, 0x00};
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Si446x_write(unreset_fifo, 2);
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// Reset FIFO
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const uint8_t reset_fifo[] = {0x15, 0x01};
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Si446x_write(reset_fifo, 2);
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const uint8_t unreset_fifo[] = {0x15, 0x00};
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Si446x_write(unreset_fifo, 2);
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Si446x_setProperty8(Si446x_PREAMBLE_TX_LENGTH, 0x00);
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Si446x_setProperty8(Si446x_SYNC_CONFIG, 0x80);
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Si446x_setProperty8(Si446x_PREAMBLE_TX_LENGTH, 0x00);
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Si446x_setProperty8(Si446x_SYNC_CONFIG, 0x80);
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Si446x_setProperty8(Si446x_GLOBAL_CLK_CFG, 0x00);
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Si446x_setProperty8(Si446x_MODEM_RSSI_CONTROL, 0x00);
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Si446x_setProperty8(Si446x_PREAMBLE_CONFIG_STD_1, 0x14);
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Si446x_setProperty8(Si446x_PKT_CONFIG1, 0x41);
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Si446x_setProperty8(Si446x_MODEM_MAP_CONTROL, 0x00);
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Si446x_setProperty8(Si446x_MODEM_DSM_CTRL, 0x07);
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Si446x_setProperty8(Si446x_MODEM_CLKGEN_BAND, 0x0D);
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Si446x_setProperty8(Si446x_GLOBAL_CLK_CFG, 0x00);
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Si446x_setProperty8(Si446x_MODEM_RSSI_CONTROL, 0x00);
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Si446x_setProperty8(Si446x_PREAMBLE_CONFIG_STD_1, 0x14);
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Si446x_setProperty8(Si446x_PKT_CONFIG1, 0x40);
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Si446x_setProperty8(Si446x_MODEM_MAP_CONTROL, 0x00);
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Si446x_setProperty8(Si446x_MODEM_DSM_CTRL, 0x07);
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Si446x_setProperty8(Si446x_MODEM_CLKGEN_BAND, 0x0D);
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Si446x_setProperty24(Si446x_MODEM_FREQ_DEV, 0x00, 0x00, 0x79);
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Si446x_setProperty8(Si446x_MODEM_TX_RAMP_DELAY, 0x01);
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Si446x_setProperty8(Si446x_PA_TC, 0x3D);
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Si446x_setProperty8(Si446x_FREQ_CONTROL_INTE, 0x41);
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Si446x_setProperty24(Si446x_FREQ_CONTROL_FRAC, 0x0B, 0xB1, 0x3B);
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Si446x_setProperty16(Si446x_FREQ_CONTROL_CHANNEL_STEP_SIZE, 0x0B, 0xD1);
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Si446x_setProperty8(Si446x_FREQ_CONTROL_W_SIZE, 0x20);
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Si446x_setProperty8(Si446x_FREQ_CONTROL_VCOCNT_RX_ADJ, 0xFA);
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Si446x_setProperty8(Si446x_MODEM_MDM_CTRL, 0x80);
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Si446x_setProperty8(Si446x_MODEM_IF_CONTROL, 0x08);
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Si446x_setProperty24(Si446x_MODEM_IF_FREQ, 0x02, 0x80, 0x00);
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Si446x_setProperty8(Si446x_MODEM_DECIMATION_CFG1, 0x20);
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Si446x_setProperty8(Si446x_MODEM_DECIMATION_CFG0, 0x10);
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Si446x_setProperty16(Si446x_MODEM_BCR_OSR, 0x00, 0x52);
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Si446x_setProperty24(Si446x_MODEM_BCR_NCO_OFFSET, 0x06, 0x3D, 0x10);
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Si446x_setProperty16(Si446x_MODEM_BCR_GAIN, 0x03, 0x1F);
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Si446x_setProperty8(Si446x_MODEM_BCR_GEAR, 0x00);
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Si446x_setProperty8(Si446x_MODEM_BCR_MISC1, 0xC2);
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Si446x_setProperty8(Si446x_MODEM_AFC_GEAR, 0x54);
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Si446x_setProperty8(Si446x_MODEM_AFC_WAIT, 0x36);
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Si446x_setProperty16(Si446x_MODEM_AFC_GAIN, 0x82, 0xAA);
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Si446x_setProperty16(Si446x_MODEM_AFC_LIMITER, 0x00, 0x95);
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Si446x_setProperty8(Si446x_MODEM_AFC_MISC, 0x80);
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Si446x_setProperty8(Si446x_MODEM_AGC_CONTROL, 0xE2);
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Si446x_setProperty8(Si446x_MODEM_AGC_WINDOW_SIZE, 0x11);
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Si446x_setProperty8(Si446x_MODEM_AGC_RFPD_DECAY, 0x12);
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Si446x_setProperty8(Si446x_MODEM_AGC_IFPD_DECAY, 0x12);
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Si446x_setProperty8(Si446x_MODEM_FSK4_GAIN1, 0x00);
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Si446x_setProperty8(Si446x_MODEM_FSK4_GAIN0, 0x02);
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Si446x_setProperty16(Si446x_MODEM_FSK4_TH, 0x02, 0x6D);
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Si446x_setProperty8(Si446x_MODEM_FSK4_MAP, 0x00);
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Si446x_setProperty8(Si446x_MODEM_OOK_PDTC, 0x28);
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Si446x_setProperty8(Si446x_MODEM_OOK_CNT1, 0x84);
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Si446x_setProperty8(Si446x_MODEM_OOK_MISC, 0x23);
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Si446x_setProperty8(Si446x_MODEM_RAW_SEARCH, 0xDE);
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Si446x_setProperty8(Si446x_MODEM_RAW_CONTROL, 0x8F);
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Si446x_setProperty16(Si446x_MODEM_RAW_EYE, 0x00, 0x0F);
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Si446x_setProperty8(Si446x_MODEM_ANT_DIV_MODE, 0x01);
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Si446x_setProperty8(Si446x_MODEM_ANT_DIV_CONTROL, 0x80);
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Si446x_setProperty8(Si446x_MODEM_RSSI_COMP, 0x40);
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Si446x_setProperty24(Si446x_MODEM_FREQ_DEV, 0x00, 0x00, 0x79);
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Si446x_setProperty8(Si446x_MODEM_TX_RAMP_DELAY, 0x01);
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Si446x_setProperty8(Si446x_PA_TC, 0x3D);
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Si446x_setProperty8(Si446x_FREQ_CONTROL_INTE, 0x41);
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Si446x_setProperty24(Si446x_FREQ_CONTROL_FRAC, 0x0B, 0xB1, 0x3B);
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Si446x_setProperty16(Si446x_FREQ_CONTROL_CHANNEL_STEP_SIZE, 0x0B, 0xD1);
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Si446x_setProperty8(Si446x_FREQ_CONTROL_W_SIZE, 0x20);
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Si446x_setProperty8(Si446x_FREQ_CONTROL_VCOCNT_RX_ADJ, 0xFA);
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Si446x_setProperty8(Si446x_MODEM_MDM_CTRL, 0x80);
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Si446x_setProperty8(Si446x_MODEM_IF_CONTROL, 0x08);
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Si446x_setProperty24(Si446x_MODEM_IF_FREQ, 0x02, 0x80, 0x00);
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Si446x_setProperty8(Si446x_MODEM_DECIMATION_CFG1, 0x70);
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Si446x_setProperty8(Si446x_MODEM_DECIMATION_CFG0, 0x10);
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Si446x_setProperty16(Si446x_MODEM_BCR_OSR, 0x01, 0xC3);
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Si446x_setProperty24(Si446x_MODEM_BCR_NCO_OFFSET, 0x01, 0x22, 0x60);
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Si446x_setProperty16(Si446x_MODEM_BCR_GAIN, 0x00, 0x91);
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Si446x_setProperty8(Si446x_MODEM_BCR_GEAR, 0x00);
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Si446x_setProperty8(Si446x_MODEM_BCR_MISC1, 0xC2);
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Si446x_setProperty8(Si446x_MODEM_AFC_GEAR, 0x54);
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Si446x_setProperty8(Si446x_MODEM_AFC_WAIT, 0x36);
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Si446x_setProperty16(Si446x_MODEM_AFC_GAIN, 0x80, 0xAB);
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Si446x_setProperty16(Si446x_MODEM_AFC_LIMITER, 0x02, 0x50);
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Si446x_setProperty8(Si446x_MODEM_AFC_MISC, 0x80);
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Si446x_setProperty8(Si446x_MODEM_AGC_CONTROL, 0xE2);
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Si446x_setProperty8(Si446x_MODEM_AGC_WINDOW_SIZE, 0x11);
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Si446x_setProperty8(Si446x_MODEM_AGC_RFPD_DECAY, 0x63);
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Si446x_setProperty8(Si446x_MODEM_AGC_IFPD_DECAY, 0x63);
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Si446x_setProperty8(Si446x_MODEM_FSK4_GAIN1, 0x00);
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Si446x_setProperty8(Si446x_MODEM_FSK4_GAIN0, 0x02);
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Si446x_setProperty16(Si446x_MODEM_FSK4_TH, 0x35, 0x55);
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Si446x_setProperty8(Si446x_MODEM_FSK4_MAP, 0x00);
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Si446x_setProperty8(Si446x_MODEM_OOK_PDTC, 0x2A);
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Si446x_setProperty8(Si446x_MODEM_OOK_CNT1, 0x85);
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Si446x_setProperty8(Si446x_MODEM_OOK_MISC, 0x23);
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Si446x_setProperty8(Si446x_MODEM_RAW_SEARCH, 0xD6);
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Si446x_setProperty8(Si446x_MODEM_RAW_CONTROL, 0x8F);
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Si446x_setProperty16(Si446x_MODEM_RAW_EYE, 0x00, 0x3B);
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Si446x_setProperty8(Si446x_MODEM_ANT_DIV_MODE, 0x01);
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Si446x_setProperty8(Si446x_MODEM_ANT_DIV_CONTROL, 0x80);
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Si446x_setProperty8(Si446x_MODEM_RSSI_COMP, 0x40);
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// Temperature readout
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lastTemp = Si446x_getTemperature();
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@ -517,57 +517,57 @@ static void Si446x_setModemAFSK_TX(void)
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static void Si446x_setModemAFSK_RX(void)
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{
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// Setup the NCO modulo and oversampling mode
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uint32_t s = Si446x_CCLK;
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uint8_t f3 = (s >> 24) & 0xFF;
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uint8_t f2 = (s >> 16) & 0xFF;
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uint8_t f1 = (s >> 8) & 0xFF;
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uint8_t f0 = (s >> 0) & 0xFF;
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Si446x_setProperty32(Si446x_MODEM_TX_NCO_MODE, f3, f2, f1, f0);
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// Setup the NCO modulo and oversampling mode
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uint32_t s = Si446x_CCLK;
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uint8_t f3 = (s >> 24) & 0xFF;
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uint8_t f2 = (s >> 16) & 0xFF;
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uint8_t f1 = (s >> 8) & 0xFF;
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uint8_t f0 = (s >> 0) & 0xFF;
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Si446x_setProperty32(Si446x_MODEM_TX_NCO_MODE, f3, f2, f1, f0);
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// Setup the NCO data rate for APRS
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Si446x_setProperty24(Si446x_MODEM_DATA_RATE, 0x04, 0x07, 0x40);
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// Setup the NCO data rate for APRS
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Si446x_setProperty24(Si446x_MODEM_DATA_RATE, 0x00, 0x2E, 0xE0);
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// Use 2FSK in DIRECT_MODE
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Si446x_setProperty8(Si446x_MODEM_MOD_TYPE, 0x0A);
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// Use 2FSK in DIRECT_MODE
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Si446x_setProperty8(Si446x_MODEM_MOD_TYPE, 0x0A);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE13_7_0, 0xA2);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE12_7_0, 0xA0);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE11_7_0, 0x97);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE10_7_0, 0x8A);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE9_7_0, 0x79);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE8_7_0, 0x66);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE7_7_0, 0x52);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE6_7_0, 0x3F);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE5_7_0, 0x2E);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE4_7_0, 0x1F);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE3_7_0, 0x14);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE2_7_0, 0x0B);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE1_7_0, 0x06);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE0_7_0, 0x02);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM0, 0x00);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM1, 0x00);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM2, 0x00);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM3, 0x00);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE13_7_0, 0xFF);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE12_7_0, 0xC4);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE11_7_0, 0x30);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE10_7_0, 0x7F);
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Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE9_7_0, 0x5F);
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||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE8_7_0, 0xB5);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE7_7_0, 0xB8);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE6_7_0, 0xDE);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE5_7_0, 0x05);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE4_7_0, 0x17);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE3_7_0, 0x16);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE2_7_0, 0x0C);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE1_7_0, 0x03);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COE0_7_0, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM0, 0x15);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM1, 0xFF);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM2, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX1_CHFLT_COEM3, 0x00);
|
||||
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE13_7_0, 0xA2);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE12_7_0, 0xA0);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE11_7_0, 0x97);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE10_7_0, 0x8A);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE9_7_0, 0x79);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE8_7_0, 0x66);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE7_7_0, 0x52);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE6_7_0, 0x3F);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE5_7_0, 0x2E);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE4_7_0, 0x1F);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE3_7_0, 0x14);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE2_7_0, 0x0B);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE1_7_0, 0x06);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE0_7_0, 0x02);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM0, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM1, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM2, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM3, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE13_7_0, 0xFF);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE12_7_0, 0xC4);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE11_7_0, 0x30);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE10_7_0, 0x7F);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE9_7_0, 0xF5);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE8_7_0, 0xB5);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE7_7_0, 0xB8);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE6_7_0, 0xDE);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE5_7_0, 0x05);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE4_7_0, 0x17);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE3_7_0, 0x16);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE2_7_0, 0x0C);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE1_7_0, 0x03);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COE0_7_0, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM0, 0x15);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM1, 0xFF);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM2, 0x00);
|
||||
Si446x_setProperty8(Si446x_MODEM_CHFLT_RX2_CHFLT_COEM3, 0x00);
|
||||
}
|
||||
|
||||
static void Si446x_setModem2FSK(uint32_t speed)
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@
|
|||
/*
|
||||
* PAL driver system settings.
|
||||
*/
|
||||
#define STM32_DISABLE_EXTI1_HANDLER
|
||||
//#define STM32_DISABLE_EXTI1_HANDLER
|
||||
#define STM32_DISABLE_EXTI5_9_HANDLER
|
||||
|
||||
/*
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue