kopia lustrzana https://github.com/mycr0ft/upython_si5351
52 wiersze
1.5 KiB
Python
52 wiersze
1.5 KiB
Python
from machine import SPI, Pin, I2C
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import SI5351
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import time
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i2c = I2C( scl=Pin(5), sda=Pin(4), freq=400000)
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devlist = i2c.scan()
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print(devlist)
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clockgen = SI5351.SI5351( i2c)
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clockgen.begin()
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clockgen.setClockBuilderData()
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# INTEGER ONLY MODE --> most accurate output */
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# Setup PLLA to integer only mode @ 900MHz (must be 600..900MHz) */
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# Set Multisynth 0 to 112.5MHz using integer only mode (div by 4/6/8) */
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# 25MHz * 36 = 900 MHz, then 900 MHz / 8 = 112.5 MHz */
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print("Set PLLA to 900MHz")
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clockgen.setupPLL(36, 0, 1, pllsource='A')
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print("Set Output #0 to {:2.2f}MHz".format(900/8))
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clockgen.setupMultisynth( output=0, div=8, num=0, denom=1, pllsource="A")
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# FRACTIONAL MODE --> More flexible but introduce clock jitter
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# Setup PLLB to fractional mode @616.66667MHz (XTAL * 24 + 2/3)
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# Setup Multisynth 1 to 13.55311MHz (PLLB/45.5) */
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mult = 32
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pllb = 25e6*mult
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print( 'PLLB = {:5.2e} Hz'.format(pllb))
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clockgen.setupPLL( mult, 0, 1, "B")
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divider = 32
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num2 = 2
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denom2 =10
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m2 = pllb/(divider+num2/denom2)
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print( "Set Output #1 to {:5.4E} Hz".format(m2) )
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clockgen.setupMultisynth( 1, divider, num2, denom2, pllsource="B")
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# Multisynth 2 is not yet used and won't be enabled, but can be */
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# Use PLLB @ 616.66667MHz, then divide by 900 -> 685.185 KHz */
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# then divide by 64 for 10.706 KHz */
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# configured using either PLL in either integer or fractional mode */
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print("Set Output #2 to {:5.1e} Hz".format(400e6/200/2.0))
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clockgen.setupMultisynth(2, 100, 0, 1, pllsource="B")
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clockgen.setupRdiv(2, 4)
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# Enable the clocks
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clockgen.enableOutputs(True)
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