Example of using PLLsoftreset

test_clockgen.py

@@ -8,8 +8,12 @@ print(devlist)
 
 clockgen = SI5351.SI5351( i2c) 
 clockgen.begin()
+
+# you could just apply a pre-built set of values generated by the clock builder desktop app.
 clockgen.setClockBuilderData()
 
+# otherwise, feel free to configure the clocks yourself:
+
 # INTEGER ONLY MODE --> most accurate output */  
 # Setup PLLA to integer only mode @ 900MHz (must be 600..900MHz) */
 # Set Multisynth 0 to 112.5MHz using integer only mode (div by 4/6/8) */
@@ -46,6 +50,9 @@ print("Set Output #2 to {:5.1e} Hz".format(400e6/200/2.0))
 clockgen.setupMultisynth(2, 100, 0, 1, pllsource="B")
 clockgen.setupRdiv(2, 4)
 
+# Soft-reset the PLLs before enabling - see datasheet p17
+clockgen.PLLsoftreset()
+
 # Enable the clocks
 clockgen.enableOutputs(True)